diff options
Diffstat (limited to 'arch/mips/isa')
| -rw-r--r-- | arch/mips/isa/base.isa | 7 | ||||
| -rw-r--r-- | arch/mips/isa/decoder.isa | 8 |
2 files changed, 7 insertions, 8 deletions
diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa index 89837c136..139a6d876 100644 --- a/arch/mips/isa/base.isa +++ b/arch/mips/isa/base.isa @@ -67,12 +67,11 @@ output decoder {{ ccprintf(ss, "%-10s ", mnemonic); if(_numDestRegs > 0){ - if(_numSrcRegs > 0) - ss << ","; printReg(ss, _destRegIdx[0]); } if(_numSrcRegs > 0) { + ss << ","; printReg(ss, _srcRegIdx[0]); } @@ -82,8 +81,8 @@ output decoder {{ } - if(mnemonic == "sll"){ - ccprintf(ss," %d",SA); + if(mnemonic == "sll" || mnemonic == "sra"){ + ccprintf(ss,", %d",SA); } return ss.str(); diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index 3a8a4dfd8..f5dd3d911 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -865,11 +865,11 @@ decode OPCODE_HI default Unknown::unknown() { format LoadMemory { 0x0: lb({{ Rt.sw = Mem.sb; }}); 0x1: lh({{ Rt.sw = Mem.sh; }}); - 0x2: lwl({{ Rt.sw = Mem.sw; }});//, WordAlign); + 0x2: lwl({{ uint32_t temp = Mem.uw<31:16> << 16; Rt.uw &= 0x00FF; Rt.uw |= temp;}}, {{ EA = (Rs + disp) & ~3; }}); 0x3: lw({{ Rt.sw = Mem.sw; }}); 0x4: lbu({{ Rt.uw = Mem.ub; }}); 0x5: lhu({{ Rt.uw = Mem.uh; }}); - 0x6: lwr({{ Rt.uw = Mem.uw; }});//, WordAlign); + 0x6: lwr({{ uint32_t temp = 0x00FF & Mem.uw<15:0>; Rt.uw &= 0xFF00; Rt.uw |= temp; }}, {{ EA = (Rs + disp) & ~3; }}); } 0x7: FailUnimpl::reserved(); @@ -879,9 +879,9 @@ decode OPCODE_HI default Unknown::unknown() { format StoreMemory { 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 0x1: sh({{ Mem.uh = Rt<15:0>; }}); - 0x2: swl({{ Mem.uw = Rt<31:0>; }});//,WordAlign); + 0x2: swl({{ Mem.uh = Rt<31:16>; }}, {{ EA = (Rs + disp) & ~3; }}); 0x3: sw({{ Mem.uw = Rt<31:0>; }}); - 0x6: swr({{ Mem.uw = Rt<31:0>; }});//,WordAlign); + 0x6: swr({{ Mem.uh = Rt<15:0>; }},{{ EA = ((Rs + disp) & ~3) + 4;}}); } format WarnUnimpl { |