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-rw-r--r--arch/mips/isa/base.isa11
-rw-r--r--arch/mips/isa/bitfields.isa5
-rw-r--r--arch/mips/isa/decoder.isa311
-rw-r--r--arch/mips/isa/formats.isa3
-rw-r--r--arch/mips/isa/formats/basic.isa4
-rw-r--r--arch/mips/isa/formats/branch.isa81
-rw-r--r--arch/mips/isa/formats/fp.isa41
-rw-r--r--arch/mips/isa/formats/int.isa63
-rw-r--r--arch/mips/isa/formats/mem.isa9
-rw-r--r--arch/mips/isa/formats/noop.isa10
-rw-r--r--arch/mips/isa/formats/trap.isa11
-rw-r--r--arch/mips/isa/formats/unimp.isa4
-rw-r--r--arch/mips/isa/formats/unknown.isa2
-rw-r--r--arch/mips/isa/formats/util.isa69
-rw-r--r--arch/mips/isa/operands.isa11
15 files changed, 350 insertions, 285 deletions
diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa
index 7600632d3..4125b5101 100644
--- a/arch/mips/isa/base.isa
+++ b/arch/mips/isa/base.isa
@@ -7,7 +7,13 @@
//Outputs to decoder.hh
output header {{
+
#define R31 31
+#include "arch/mips/faults.hh"
+#include "arch/mips/isa_traits.hh"
+
+ using namespace MipsISA;
+
/**
* Base class for all MIPS static instructions.
@@ -19,12 +25,12 @@ output header {{
/// Make MipsISA register dependence tags directly visible in
/// this class and derived classes. Maybe these should really
/// live here and not in the MipsISA namespace.
- enum DependenceTags {
+ /*enum DependenceTags {
FP_Base_DepTag = MipsISA::FP_Base_DepTag,
Fpcr_DepTag = MipsISA::Fpcr_DepTag,
Uniq_DepTag = MipsISA::Uniq_DepTag,
IPR_Base_DepTag = MipsISA::IPR_Base_DepTag
- };
+ };*/
// Constructor
MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
@@ -67,6 +73,7 @@ output decoder {{
{
printReg(ss, _srcRegIdx[0]);
}
+
if(_numSrcRegs > 1)
{
ss << ",";
diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa
index 3a01b64ee..58d487ad2 100644
--- a/arch/mips/isa/bitfields.isa
+++ b/arch/mips/isa/bitfields.isa
@@ -33,10 +33,12 @@ def bitfield INTIMM <15: 0>; // integer immediate (literal)
// Floating-point operate format
def bitfield FMT <25:21>;
+def bitfield FR <25:21>;
def bitfield FT <20:16>;
def bitfield FS <15:11>;
def bitfield FD <10:6>;
+def bitfield CC <20:18>;
def bitfield ND <17:17>;
def bitfield TF <16:16>;
def bitfield MOVCI <16:16>;
@@ -45,6 +47,9 @@ def bitfield SRL <21:21>;
def bitfield SRLV < 6: 6>;
def bitfield SA <10: 6>;
+// CP0 Register Select
+def bitfield SEL < 2: 0>;
+
// Interrupts
def bitfield SC < 5: 5>;
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index f16da7f87..b2410f9b9 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -20,8 +20,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode FUNCTION_LO {
0x1: decode MOVCI {
format BasicOp {
- 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}});
- 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}});
+ 0: movf({{ if (xc->readMiscReg(FPCR,0) != CC) Rd = Rs}});
+ 1: movt({{ if (xc->readMiscReg(FPCR,0) == CC) Rd = Rs}});
}
}
@@ -60,9 +60,9 @@ decode OPCODE_HI default Unknown::unknown() {
//to distinguish JR from JR.HB and JALR from JALR.HB"
format Jump {
0x0: decode HINT {
- 0:jr({{ NNPC = Rs; }},IsReturn);
+ 0:jr({{ NNPC = Rs & ~1; }},IsReturn);
- 1:jr_hb({{ NNPC = Rs; clear_exe_inst_hazards(); }},IsReturn);
+ 1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn);
}
0x1: decode HINT {
@@ -86,10 +86,10 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: decode FUNCTION_LO {
format BasicOp {
- 0x0: mfhi({{ Rd = xc->miscRegs.hi; }});
- 0x1: mthi({{ xc->miscRegs.hi = Rs; }});
- 0x2: mflo({{ Rd = xc->miscRegs.lo; }});
- 0x3: mtlo({{ xc->miscRegs.lo = Rs; }});
+ 0x0: mfhi({{ Rd = xc->readMiscReg(Hi,0); }});
+ 0x1: mthi({{ xc->setMiscReg(Hi,0,Rs); }});
+ 0x2: mflo({{ Rd = xc->readMiscReg(Lo,0); }});
+ 0x3: mtlo({{ xc->setMiscReg(Lo,0,Rs); }});
}
}
@@ -97,39 +97,38 @@ decode OPCODE_HI default Unknown::unknown() {
format IntOp {
0x0: mult({{
int64_t temp1 = Rs.sw * Rt.sw;
- xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>;
+ xc->setMiscReg(Hi,0,temp1<63:32>);
+ xc->setMiscReg(Lo,0,temp1<31:0>);
}});
0x1: multu({{
int64_t temp1 = Rs.uw * Rt.uw;
- xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>
- Rd.sw = Rs.uw * Rt.uw;
+ xc->setMiscReg(Hi,0,temp1<63:32>);
+ xc->setMiscReg(Lo,0,temp1<31:0>);
}});
0x2: div({{
- xc->miscRegs.hi = Rs.sw % Rt.sw;
- xc->miscRegs.lo = Rs.sw / Rt.sw;
+ xc->setMiscReg(Hi,0,Rs.sw % Rt.sw);
+ xc->setMiscReg(Lo,0,Rs.sw / Rt.sw);
}});
0x3: divu({{
- xc->miscRegs.hi = Rs.uw % Rt.uw;
- xc->miscRegs.lo = Rs.uw / Rt.uw;
+ xc->setMiscReg(Hi,0,Rs.uw % Rt.uw);
+ xc->setMiscReg(Lo,0,Rs.uw / Rt.uw);
}});
}
}
0x4: decode FUNCTION_LO {
format IntOp {
- 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}});
- 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}});
- 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}});
- 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}});
- 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}});
- 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}});
- 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}});
- 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}});
+ 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}});
+ 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
+ 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
+ 0x3: subu({{ Rd.sw = Rs.sw - Rt.uw;}});
+ 0x4: and({{ Rd = Rs & Rt;}});
+ 0x5: or({{ Rd = Rs | Rt;}});
+ 0x6: xor({{ Rd = Rs ^ Rt;}});
+ 0x7: nor({{ Rd = ~(Rs | Rt);}});
}
}
@@ -141,8 +140,8 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x6: decode FUNCTION_LO {
- format BasicOp {
- 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
+ format Trap {
+ 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
@@ -167,7 +166,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x1: decode REGIMM_LO {
- format BasicOp {
+ format Trap {
0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
@@ -198,14 +197,14 @@ decode OPCODE_HI default Unknown::unknown() {
}
format Jump {
- 0x2: j({{ NNPC = (NPC & 0xF0000000) & (0x00000000 & JMPTARG << 2);}});
+ 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
- 0x3: jal({{ NNPC = (NPC & 0xF0000000) & (0x00000000 & JMPTARG << 2);}},IsCall,IsReturn);
+ 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn);
}
format Branch {
- 0x4: beq({{ cond = (Rs.sw == 0); }});
- 0x5: bne({{ cond = (Rs.sw != 0); }});
+ 0x4: beq({{ cond = (Rs.sw == Rt.sw); }});
+ 0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
0x6: blez({{ cond = (Rs.sw <= 0); }});
0x7: bgtz({{ cond = (Rs.sw > 0); }});
}
@@ -213,10 +212,10 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: decode OPCODE_LO {
format IntOp {
- 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }});
- 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}});
- 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }});
- 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }});
+ 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
+ 0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
+ 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
+ 0x3: sltiu({{ Rt.sw = ( Rs.sw < imm ) ? 1 : 0 }});
0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
@@ -229,33 +228,17 @@ decode OPCODE_HI default Unknown::unknown() {
//Table A-11 MIPS32 COP0 Encoding of rs Field
0x0: decode RS_MSB {
0x0: decode RS {
- format BasicOp {
+ format System {
0x0: mfc0({{
- //The contents of the coprocessor 0 register specified by the
- //combination of rd and sel are loaded into general register
- //rt. Note that not all coprocessor 0 registers support the
- //sel field. In those instances, the sel field must be zero.
-
- if (SEL > 0)
- panic("Can't Handle Cop0 with register select yet\n");
-
- uint64_t reg_num = Rd.uw;
+ //uint64_t reg_num = Rd.uw;
- Rt = xc->miscRegs.cop0[reg_num];
+ Rt = xc->readMiscReg(RD,SEL);
}});
0x4: mtc0({{
- //The contents of the coprocessor 0 register specified by the
- //combination of rd and sel are loaded into general register
- //rt. Note that not all coprocessor 0 registers support the
- //sel field. In those instances, the sel field must be zero.
-
- if (SEL > 0)
- panic("Can't Handle Cop0 with register select yet\n");
+ //uint64_t reg_num = Rd.uw;
- uint64_t reg_num = Rd.uw;
-
- xc->miscRegs.cop0[reg_num] = Rt;
+ xc->setMiscReg(RD,SEL,Rt);
}});
0x8: mftr({{
@@ -279,64 +262,84 @@ decode OPCODE_HI default Unknown::unknown() {
0xA: rdpgpr({{
//Accessing Previous Shadow Set Register Number
- uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
- uint64_t reg_num = Rt.uw;
+ //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/;
+ //uint64_t reg_num = Rt.uw;
- Rd = xc->shadowIntRegFile[prev][reg_num];
+ //Rd = xc->regs.IntRegFile[prev];
+ //Rd = xc->shadowIntRegFile[prev][reg_num];
}});
0xB: decode RD {
0x0: decode SC {
0x0: dvpe({{
- Rt.sw = xc->miscRegs.cop0.MVPControl;
- xc->miscRegs.cop0.MVPControl[EVP] = 0;
+ int idx;
+ int sel;
+ getMiscRegIdx(MVPControl,idx,sel);
+ Rt.sw = xc->readMiscReg(idx,sel);
+ xc->setMiscReg(idx,sel,0);
}});
0x1: evpe({{
- Rt.sw = xc->miscRegs.cop0.MVPControl;
- xc->miscRegs.cop0.MVPControl[EVP] = 1;
+ int idx;
+ int sel;
+ getMiscRegIdx(MVPControl,idx,sel);
+ Rt.sw = xc->readMiscReg(idx,sel);
+ xc->setMiscReg(idx,sel,1);
}});
}
0x1: decode SC {
0x0: dmt({{
- Rt.sw = xc->miscRegs.cop0.VPEControl;
- xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0;
+ int idx;
+ int sel;
+ getMiscRegIdx(VPEControl,idx,sel);
+ Rt.sw = xc->readMiscReg(idx,sel);
+ xc->setMiscReg(idx,sel,0);
}});
0x1: emt({{
- Rt.sw = xc->miscRegs.cop0.VPEControl;
- xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1;
+ int idx;
+ int sel;
+ getMiscRegIdx(VPEControl,idx,sel);
+ Rt.sw = xc->readMiscReg(idx,sel);
+ xc->setMiscReg(idx,sel,1);
}});
}
0xC: decode SC {
0x0: di({{
- Rt.sw = xc->miscRegs.cop0.Status;
- xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0;
+ int idx;
+ int sel;
+ getMiscRegIdx(Status,idx,sel);
+ Rt.sw = xc->readMiscReg(idx,sel);
+ xc->setMiscReg(idx,sel,0);
}});
0x1: ei({{
- Rt.sw = xc->miscRegs.cop0.Status;
- xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1;
+ int idx;
+ int sel;
+ getMiscRegIdx(Status,idx,sel);
+ Rt.sw = xc->readMiscReg(idx,sel);
+ xc->setMiscReg(idx,sel,1);
}});
}
}
0xE: wrpgpr({{
//Accessing Previous Shadow Set Register Number
- uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
- uint64_t reg_num = Rd.uw;
+ //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/);
+ //uint64_t reg_num = Rd.uw;
- xc->shadowIntRegFile[prev][reg_num] = Rt;
+ //xc->regs.IntRegFile[prev];
+ //xc->shadowIntRegFile[prev][reg_num] = Rt;
}});
}
}
//Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
0x1: decode FUNCTION {
- format BasicOp {
+ format System {
0x01: tlbr({{ }});
0x02: tlbwi({{ }});
0x06: tlbwr({{ }});
@@ -357,27 +360,27 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode RS_HI {
0x0: decode RS_LO {
format FloatOp {
- 0x0: mfc1({{ Rt = Fs<31:0>; }});
- 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}});
- 0x3: mfhc1({{ Rt = Fs<63:32>;}});
- 0x4: mtc1({{ Fs<31:0> = Rt}});
- 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}});
- 0x7: mftc1({{ Fs<63:32> = Rt}});
+ 0x0: mfc1({{ /*Rt.uw = Fs.ud<31:0>;*/ }});
+ 0x2: cfc1({{ /*Rt.uw = xc->readMiscReg(FPCR[Fs]);*/}});
+ 0x3: mfhc1({{ /*Rt.uw = Fs.ud<63:32>*/;}});
+ 0x4: mtc1({{ /*Fs = Rt.uw*/}});
+ 0x6: ctc1({{ /*xc->setMiscReg(FPCR[Fs],Rt);*/}});
+ 0x7: mthc1({{ /*Fs<63:32> = Rt.uw*/}});
}
}
0x1: decode ND {
0x0: decode TF {
format Branch {
- 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
- 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
+ 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR,0) == 0); }});
+ 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR,0) == 1); }});
}
}
0x1: decode TF {
format BranchLikely {
- 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
- 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
+ 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR,0) == 0); }});
+ 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR,0) == 1); }});
}
}
}
@@ -396,7 +399,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}});
0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}});
0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}});
- 0x5: abss({{ Fd.sf = abs(Fs.sf);}});
+ 0x5: abss({{ Fd.sf = fabs(Fs.sf);}});
0x6: movs({{ Fd.sf = Fs.sf;}});
0x7: negs({{ Fd.sf = -1 * Fs.sf;}});
}
@@ -422,8 +425,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp {
- 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }});
- 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}});
+ 0x0: movfs({{if (xc->readMiscReg(FPCR,0) != CC) Fd = Fs; }});
+ 0x1: movts({{if (xc->readMiscReg(FPCR,0) == CC) Fd = Fs;}});
}
}
@@ -434,29 +437,29 @@ decode OPCODE_HI default Unknown::unknown() {
format Float64Op {
0x5: recips({{ Fd = 1 / Fs; }});
- 0x6: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}});
+ 0x6: rsqrts({{ Fd = 1 / sqrt((double)Fs.ud);}});
}
}
0x4: decode RS_LO {
format FloatOp {
- 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ 0x1: cvt_d_s({{ int rnd_mode = xc->readMiscReg(FCSR,0);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
}});
- 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ 0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR,0);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
}});
}
//only legal for 64 bit
format Float64Op {
- 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ 0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR,0);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
}});
- 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }});
+ 0x6: cvt_ps_s({{ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/ }});
}
}
}
@@ -470,7 +473,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: muld({{ Fd.df = Fs.df * Ft.df;}});
0x3: divd({{ Fd.df = Fs.df / Ft.df;}});
0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}});
- 0x5: absd({{ Fd.df = abs(Fs.df);}});
+ 0x5: absd({{ Fd.df = fabs(Fs.df);}});
0x6: movd({{ Fd.df = Fs.df;}});
0x7: negd({{ Fd.df = -1 * Fs.df;}});
}
@@ -496,8 +499,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp {
- 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }});
- 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }});
+ 0x0: movfd({{if (xc->readMiscReg(FPCR,0) != CC) Fd.df = Fs.df; }});
+ 0x1: movtd({{if (xc->readMiscReg(FPCR,0) == CC) Fd.df = Fs.df; }});
}
}
@@ -515,12 +518,12 @@ decode OPCODE_HI default Unknown::unknown() {
0x4: decode RS_LO {
format FloatOp {
0x0: cvt_s_d({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR,0);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE);
}});
0x4: cvt_w_d({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR,0);
Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE);
}});
}
@@ -528,7 +531,7 @@ decode OPCODE_HI default Unknown::unknown() {
//only legal for 64 bit
format Float64Op {
0x5: cvt_l_d({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR,0);
Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
}});
}
@@ -539,12 +542,12 @@ decode OPCODE_HI default Unknown::unknown() {
0x4: decode FUNCTION {
format FloatOp {
0x20: cvt_s({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR,0);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD);
}});
0x21: cvt_d({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR,0);
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD);
}});
}
@@ -556,12 +559,12 @@ decode OPCODE_HI default Unknown::unknown() {
0x5: decode FUNCTION_HI {
format FloatOp {
0x10: cvt_s_l({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR,0);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG);
}});
0x11: cvt_d_l({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR,0);
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG);
}});
}
@@ -590,12 +593,12 @@ decode OPCODE_HI default Unknown::unknown() {
0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
- Fd.df = abs(Fs.df);
+ Fd.df = fabs(Fs.df);
}});
0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
- Fd.df = Fs<31:0> | Ft<31:0>;
+ //Fd.df = Fs<31:0> | Ft<31:0>;
}});
0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
@@ -608,21 +611,21 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: decode RS_LO {
0x1: decode MOVCF {
format Float64Op {
- 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
- 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
+ 0x0: movfps({{if (xc->readMiscReg(FPCR,0) != CC) Fd = Fs;}});
+ 0x1: movtps({{if (xc->readMiscReg(FPCR,0) == CC) Fd = Fs;}});
}
}
format BasicOp {
- 0x2: movzps({{ if ( FPConditionCode(CC) == 0) Fd = Fs; }});
- 0x3: movnps({{ if ( FPConditionCode(CC) == 0) Fd = Fs; }});
+ 0x2: movzps({{if (xc->readMiscReg(FPCR,0) != CC) Fd = Fs; }});
+ 0x3: movnps({{if (xc->readMiscReg(FPCR,0) == CC) Fd = Fs; }});
}
}
0x4: decode RS_LO {
0x0: Float64Op::cvt_s_pu({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR,0);
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI);
}});
}
@@ -630,13 +633,13 @@ decode OPCODE_HI default Unknown::unknown() {
0x5: decode RS_LO {
format Float64Op {
0x0: cvt_s_pl({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR,0);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
}});
- 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}});
- 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}});
- 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}});
- 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}});
+ 0x4: pll({{ /*Fd.df = Fs<31:0> | Ft<31:0>*/}});
+ 0x5: plu({{ /*Fd.df = Fs<31:0> | Ft<63:32>*/}});
+ 0x6: pul({{ /*Fd.df = Fs<63:32> | Ft<31:0>*/}});
+ 0x7: puu({{ /*Fd.df = Fs<63:32 | Ft<63:32>*/}});
}
}
}
@@ -682,23 +685,23 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: decode FUNCTION_HI {
0x0: decode FUNCTION_LO {
format LoadMemory2 {
- 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.sf; }});
- 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }});
+ 0x0: lwxc1({{ EA = Rs + Rt; }},{{ /*F_t<31:0> = Mem.sf; */}});
+ 0x1: ldxc1({{ EA = Rs + Rt; }},{{ /*F_t<63:0> = Mem.df;*/ }});
0x5: luxc1({{ //Need to make EA<2:0> = 0
EA = Rs + Rt;
}},
- {{ Ft<31:0> = Mem.df; }});
+ {{ /*F_t<31:0> = Mem.df; */}});
}
}
0x1: decode FUNCTION_LO {
format StoreMemory2 {
- 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.sf = Ft<31:0>; }});
- 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.df = Ft<63:0>}});
+ 0x0: swxc1({{ EA = Rs + Rt; }},{{ /*Mem.sf = Ft<31:0>; */}});
+ 0x1: sdxc1({{ EA = Rs + Rt; }},{{ /*Mem.df = Ft<63:0> */}});
0x5: suxc1({{ //Need to make EA<2:0> = 0
EA = Rs + Rt;
}},
- {{ Mem.df = Ft<63:0>;}});
+ {{ /*Mem.df = F_t<63:0>;*/}});
}
0x7: WarnUnimpl::prefx();
@@ -768,33 +771,33 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode FUNCTION_LO {
format IntOp {
0x0: madd({{
- int64_t temp1 = Hi.sw << 32 | Lo.sw >> 32;
+ int64_t temp1 = xc->readMiscReg(Hi,0) << 32 | xc->readMiscReg(Lo,0) >> 32;
temp1 = temp1 + (Rs.sw * Rt.sw);
- xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>
+ xc->setMiscReg(Hi,0,temp1<63:32>);
+ xc->setMiscReg(Lo,0,temp1<31:0>);
}});
0x1: maddu({{
- int64_t temp1 = Hi.uw << 32 | Lo.uw >> 32;
+ int64_t temp1 = xc->readMiscReg(Hi,0) << 32 | xc->readMiscReg(Lo,0) >> 32;
temp1 = temp1 + (Rs.uw * Rt.uw);
- xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>
+ xc->setMiscReg(Hi,0,temp1<63:32>);
+ xc->setMiscReg(Lo,0,temp1<31:0>);
}});
- 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
+ 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
0x4: msub({{
- int64_t temp1 = Hi.sw << 32 | Lo.sw >> 32;
+ int64_t temp1 = xc->readMiscReg(Hi,0) << 32 | xc->readMiscReg(Lo,0) >> 32;
temp1 = temp1 - (Rs.sw * Rt.sw);
- xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>
+ xc->setMiscReg(Hi,0,temp1<63:32>);
+ xc->setMiscReg(Lo,0,temp1<31:0>);
}});
0x5: msubu({{
- int64_t temp1 = Hi.uw << 32 | Lo.uw >> 32;
+ int64_t temp1 = xc->readMiscReg(Hi,0) << 32 | xc->readMiscReg(Lo,0) >> 32;
temp1 = temp1 - (Rs.uw * Rt.uw);
- xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>
+ xc->setMiscReg(Hi,0,temp1<63:32>);
+ xc->setMiscReg(Lo,0,temp1<31:0>);
}});
}
}
@@ -802,25 +805,25 @@ decode OPCODE_HI default Unknown::unknown() {
0x4: decode FUNCTION_LO {
format BasicOp {
0x0: clz({{
- int cnt = 0;
+ /*int cnt = 0;
int idx = 0;
- while ( Rs.uw<idx>!= 1) {
+ while ( Rs.uw<idx> != 1) {
cnt++;
idx--;
}
- Rd.uw = cnt;
+ Rd.uw = cnt;*/
}});
0x1: clo({{
- int cnt = 0;
+ /*int cnt = 0;
int idx = 0;
- while ( Rs.uw<idx>!= 0) {
+ while ( Rs.uw<idx> != 0) {
cnt++;
idx--;
}
- Rd.uw = cnt;
+ Rd.uw = cnt;*/
}});
}
}
@@ -860,20 +863,20 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x6: decode FUNCTION_LO {
- 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}});
+ 0x7: BasicOp::rdhwr({{ /*Rt = xc->hwRegs[RD];*/ }});
}
}
}
0x4: decode OPCODE_LO default FailUnimpl::reserved() {
format LoadMemory {
- 0x0: lb({{ Rb.sw = Mem.sb; }});
- 0x1: lh({{ Rb.sw = Mem.sh; }});
- 0x2: lwl({{ Rb.sw = Mem.sw; }});//, WordAlign);
- 0x3: lw({{ Rb.uq = Mem.sb; }});
- 0x4: lbu({{ Rb.uw = Mem.ub; }});
- 0x5: lhu({{ Rb.uw = Mem.uh; }});
- 0x6: lwr({{ Rb.uw = Mem.uw; }});//, WordAlign);
+ 0x0: lb({{ Rt.sw = Mem.sb; }});
+ 0x1: lh({{ Rt.sw = Mem.sh; }});
+ 0x2: lwl({{ Rt.sw = Mem.sw; }});//, WordAlign);
+ 0x3: lw({{ Rt.sw = Mem.sb; }});
+ 0x4: lbu({{ Rt.uw = Mem.ub; }});
+ 0x5: lhu({{ Rt.uw = Mem.uh; }});
+ 0x6: lwr({{ Rt.uw = Mem.uw; }});//, WordAlign);
}
0x7: FailUnimpl::reserved();
@@ -898,19 +901,19 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: WarnUnimpl::ll();
format LoadMemory {
- 0x1: lwc1({{ Ft<31:0> = Mem.sf; }});
- 0x5: ldc1({{ Ft<63:0> = Mem.df; }});
+ 0x1: lwc1({{ /*F_t<31:0> = Mem.sf; */}});
+ 0x5: ldc1({{ /*F_t<63:0> = Mem.df; */}});
}
}
+
0x7: decode OPCODE_LO default FailUnimpl::reserved() {
0x0: WarnUnimpl::sc();
format StoreMemory {
- 0x1: swc1({{ Mem.sf = Ft<31:0>; }});
- 0x5: sdc1({{ Mem.df = Ft<63:0>; }});
+ 0x1: swc1({{ //Mem.sf = Ft<31:0>; }});
+ 0x5: sdc1({{ //Mem.df = Ft<63:0>; }});
}
-
}
}
diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa
index a6aec9437..f7a9e4ce2 100644
--- a/arch/mips/isa/formats.isa
+++ b/arch/mips/isa/formats.isa
@@ -10,6 +10,9 @@
//Include utility formats/functions
##include "m5/arch/mips/isa/formats/util.isa"
+//Include the cop0 formats
+##include "m5/arch/mips/isa/formats/cop0.isa"
+
//Include the integer formats
##include "m5/arch/mips/isa/formats/int.isa"
diff --git a/arch/mips/isa/formats/basic.isa b/arch/mips/isa/formats/basic.isa
index 3b62aa5c3..c02af7ddc 100644
--- a/arch/mips/isa/formats/basic.isa
+++ b/arch/mips/isa/formats/basic.isa
@@ -31,14 +31,14 @@ def template BasicConstructor {{
def template BasicExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
- Fault fault = No_Fault;
+ Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
- if(fault == No_Fault)
+ if(fault == NoFault)
{
%(op_wb)s;
}
diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
index c896e9b2d..0d2ad7855 100644
--- a/arch/mips/isa/formats/branch.isa
+++ b/arch/mips/isa/formats/branch.isa
@@ -7,6 +7,9 @@
output header {{
+#include <iostream>
+ using namespace std;
+
/**
* Base class for instructions whose disassembly is not purely a
* function of the machine instruction (i.e., it depends on the
@@ -52,6 +55,10 @@ output header {{
: PCDependentDisassembly(mnem, _machInst, __opClass),
disp(OFFSET << 2)
{
+ //If Bit 17 is 1 then Sign Extend
+ if ( (disp & 0x00020000) > 0 ) {
+ disp |= 0xFFFE0000;
+ }
}
Addr branchTarget(Addr branchPC) const;
@@ -74,6 +81,7 @@ output header {{
: PCDependentDisassembly(mnem, _machInst, __opClass),
disp(OFFSET << 2)
{
+
}
Addr branchTarget(Addr branchPC) const;
@@ -93,11 +101,13 @@ output header {{
/// Displacement to target address (signed).
int32_t disp;
+ uint32_t target;
+
public:
/// Constructor
Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
- disp(OFFSET)
+ disp(JMPTARG << 2)
{
}
@@ -159,23 +169,17 @@ output decoder {{
// either a source (the condition for conditional
// branches) or a destination (the link reg for
// unconditional branches)
- if (_numSrcRegs > 0) {
+ if (_numSrcRegs == 1) {
printReg(ss, _srcRegIdx[0]);
ss << ",";
- }
- else if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
+ } else if(_numSrcRegs == 2) {
+ printReg(ss, _srcRegIdx[0]);
ss << ",";
- }
-
-#ifdef SS_COMPATIBLE_DISASSEMBLY
- if (_numSrcRegs == 0 && _numDestRegs == 0) {
- printReg(ss, 31);
+ printReg(ss, _srcRegIdx[1]);
ss << ",";
}
-#endif
- Addr target = pc + 4 + disp;
+ Addr target = pc + 8 + disp;
std::string str;
if (symtab && symtab->findSymbol(target, str))
@@ -206,13 +210,6 @@ output decoder {{
ss << ",";
}
-#ifdef SS_COMPATIBLE_DISASSEMBLY
- if (_numSrcRegs == 0 && _numDestRegs == 0) {
- printReg(ss, 31);
- ss << ",";
- }
-#endif
-
Addr target = pc + 4 + disp;
std::string str;
@@ -231,20 +228,25 @@ output decoder {{
ccprintf(ss, "%-10s ", mnemonic);
-#ifdef SS_COMPATIBLE_DISASSEMBLY
- if (_numDestRegs == 0) {
- printReg(ss, 31);
- ss << ",";
- }
-#endif
-
- if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
+ if ( mnemonic == "jal" ) {
+ Addr npc = pc + 4;
+ ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
+ } else if (_numSrcRegs == 0) {
+ std::string str;
+ if (symtab && symtab->findSymbol(disp, str))
+ ss << str;
+ else
+ ccprintf(ss, "0x%x", disp);
+ } else if (_numSrcRegs == 1) {
+ printReg(ss, _srcRegIdx[0]);
+ } else if(_numSrcRegs == 2) {
+ printReg(ss, _srcRegIdx[0]);
ss << ",";
+ printReg(ss, _srcRegIdx[1]);
+ } else {
+ panic(">= 3 Source Registers!!!");
}
- ccprintf(ss, "(r%d)", RT);
-
return ss.str();
}
}};
@@ -253,16 +255,18 @@ def format Branch(code,*flags) {{
#Add Link Code if Link instruction
strlen = len(name)
if name[strlen-2:] == 'al':
- code += 'R31 = NNPC;\n'
+ code += 'r31 = NNPC;\n'
#Condition code
code = 'bool cond;\n' + code
code += 'if (cond) {\n'
- #code += '//NPC=NPC: just placeholder to force parser to writeback NPC\n'
- #code += ' NPC = NPC; \n'
code += ' NNPC = NPC + disp;\n'
+ code += '} else {\n'
+ code += ' NNPC = NNPC;\n'
code += '} \n'
+ code += 'cout << hex << "NPC: " << NPC << " + " << disp << " = " << NNPC << endl;'
+
iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
('IsDirectControl', 'IsCondControl'))
@@ -277,13 +281,11 @@ def format BranchLikely(code,*flags) {{
#Add Link Code if Link instruction
strlen = len(name)
if name[strlen-3:] == 'all':
- code += 'R31 = NNPC;\n'
+ code += 'r31 = NNPC;\n'
#Condition code
code = 'bool cond;\n' + code
code += 'if (cond) {'
- #code += '//NPC=NPC: just placeholder to force parser to writeback NPC\n'
- #code += 'NPC = NPC; \n'
code += 'NNPC = NPC + disp;\n'
code += '} \n'
@@ -300,8 +302,11 @@ def format BranchLikely(code,*flags) {{
def format Jump(code,*flags) {{
#Add Link Code if Link instruction
strlen = len(name)
- if strlen >= 3 and name[2:3] == 'al':
- code = 'R31 = NNPC;\n' + code
+ if strlen > 1 and name[1:] == 'al':
+ code = 'r31 = NNPC;\n' + code
+
+ #code += 'if(NNPC == 0x80000638) { NNPC = r31; cout << "SKIPPING JUMP TO SIM_GET_MEM_CONF" << endl;}'
+ #code += 'target = NNPC;'
iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\
('IsIndirectControl', 'IsUncondControl'))
diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa
index 7dd1e8442..34b71acf7 100644
--- a/arch/mips/isa/formats/fp.isa
+++ b/arch/mips/isa/formats/fp.isa
@@ -29,47 +29,6 @@ output decoder {{
}
}};
-def template FloatingPointExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
- {
- //These are set to constants when the execute method
- //is generated
- bool useCc = ;
- bool checkPriv = ;
-
- //Attempt to execute the instruction
- try
- {
- checkPriv;
-
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
- }
- //If we have an exception for some reason,
- //deal with it
- catch(MipsException except)
- {
- //Deal with exception
- return No_Fault;
- }
-
- //Write the resulting state to the execution context
- %(op_wb)s;
- if(useCc)
- {
- xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
- xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
- xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
- xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
- xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
- xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
- xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
- xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
- }
- return No_Fault;
- }
-}};
// Primary format for integer operate instructions:
def format FloatOp(code, *flags) {{
diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa
index cf06741a1..a47844bee 100644
--- a/arch/mips/isa/formats/int.isa
+++ b/arch/mips/isa/formats/int.isa
@@ -7,6 +7,8 @@
//Outputs to decoder.hh
output header {{
+#include <iostream>
+ using namespace std;
/**
* Base class for integer operations.
*/
@@ -26,15 +28,24 @@ output header {{
class IntImmOp : public MipsStaticInst
{
protected:
- uint16_t imm;
+
+ int32_t imm;
/// Constructor
IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
{
+ //If Bit 15 is 1 then Sign Extend
+ int32_t temp = imm & 0x00008000;
+
+ if (temp > 0 && mnemonic != "lui") {
+ imm |= 0xFFFF0000;
+ }
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+
};
}};
@@ -43,15 +54,59 @@ output header {{
output decoder {{
std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
- return "Disassembly of integer instruction\n";
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ // just print the first dest... if there's a second one,
+ // it's generally implicit
+ if (_numDestRegs > 0) {
+ printReg(ss, _destRegIdx[0]);
+ }
+
+ ss << ",";
+
+ // just print the first two source regs... if there's
+ // a third one, it's a read-modify-write dest (Rc),
+ // e.g. for CMOVxx
+ if (_numSrcRegs > 0) {
+ printReg(ss, _srcRegIdx[0]);
+ }
+
+ if (_numSrcRegs > 1) {
+ ss << ",";
+ printReg(ss, _srcRegIdx[1]);
+ }
+
+ return ss.str();
}
std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
- return "Disassembly of integer immediate instruction\n";
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ if (_numDestRegs > 0) {
+ printReg(ss, _destRegIdx[0]);
+ }
+
+ ss << ",";
+
+ if (_numSrcRegs > 0) {
+ printReg(ss, _srcRegIdx[0]);
+ ss << ",";
+ }
+
+ if( mnemonic == "lui")
+ ccprintf(ss, "%08p ", imm);
+ else
+ ss << (int) imm;
+
+ return ss.str();
}
-}};
+}};
//Used by decoder.isa
def format IntOp(code, *opt_flags) {{
diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
index fcdb577c6..8a07e63d4 100644
--- a/arch/mips/isa/formats/mem.isa
+++ b/arch/mips/isa/formats/mem.isa
@@ -40,6 +40,7 @@ output header {{
const StaticInstPtr eaCompPtr;
/// Pointer to MemAcc object.
const StaticInstPtr memAccPtr;
+
/// Displacement for EA calculation (signed).
int32_t disp;
@@ -51,6 +52,12 @@ output header {{
memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
disp(OFFSET)
{
+ //If Bit 15 is 1 then Sign Extend
+ int32_t temp = disp & 0x00008000;
+
+ if (temp > 0) {
+ disp |= 0xFFFF0000;
+ }
}
std::string
@@ -70,7 +77,7 @@ output decoder {{
Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
- flags[IsFloating] ? 'f' : 'r', RS, JMPTARG, RT);
+ flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
}
}};
diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa
index 05c5ac10f..d35179005 100644
--- a/arch/mips/isa/formats/noop.isa
+++ b/arch/mips/isa/formats/noop.isa
@@ -59,7 +59,7 @@ output exec {{
Fault
Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
{
- return No_Fault;
+ return NoFault;
}
}};
@@ -68,9 +68,11 @@ output exec {{
def template OperateNopCheckDecode {{
{
MipsStaticInst *i = new %(class_name)s(machInst);
- if (RD == 0) {
- i = makeNop(i);
- }
+
+ //if (RD == 0) {
+ // i = makeNop(i);
+ //}
+
return i;
}
}};
diff --git a/arch/mips/isa/formats/trap.isa b/arch/mips/isa/formats/trap.isa
index 78f8d87b0..6884d4fa8 100644
--- a/arch/mips/isa/formats/trap.isa
+++ b/arch/mips/isa/formats/trap.isa
@@ -42,12 +42,11 @@ def template TrapExecute {{
}};
// Primary format for integer operate instructions:
-def format Trap(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+def format Trap(code, *flags) {{
+ code = 'bool cond;\n' + code;
+ iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecodeWithMnemonic.subst(iop)
- exec_output = TrapExecute.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
}};
diff --git a/arch/mips/isa/formats/unimp.isa b/arch/mips/isa/formats/unimp.isa
index a7a71c681..adbd5b5b1 100644
--- a/arch/mips/isa/formats/unimp.isa
+++ b/arch/mips/isa/formats/unimp.isa
@@ -111,7 +111,7 @@ output exec {{
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
- return Unimplemented_Opcode_Fault;
+ return UnimplementedOpcodeFault;
}
Fault
@@ -123,7 +123,7 @@ output exec {{
warned = true;
}
- return No_Fault;
+ return NoFault;
}
}};
diff --git a/arch/mips/isa/formats/unknown.isa b/arch/mips/isa/formats/unknown.isa
index 6eba5b4f9..4601b3684 100644
--- a/arch/mips/isa/formats/unknown.isa
+++ b/arch/mips/isa/formats/unknown.isa
@@ -42,7 +42,7 @@ output exec {{
{
panic("attempt to execute unknown instruction "
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
- return Unimplemented_Opcode_Fault;
+ return UnimplementedOpcodeFault;
}
}};
diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa
index c06877b35..db4bf204a 100644
--- a/arch/mips/isa/formats/util.isa
+++ b/arch/mips/isa/formats/util.isa
@@ -1,29 +1,6 @@
// -*- mode:c++ -*-
let {{
-def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
- # Declare basic control transfer w/o link (i.e. link reg is R31)
- nolink_code = 'NPC = %s;\n' % npc_expr
- nolink_iop = InstObjParams(name, Name, base_class,
- CodeBlock(nolink_code), flags)
- header_output = BasicDeclare.subst(nolink_iop)
- decoder_output = BasicConstructor.subst(nolink_iop)
- exec_output = BasicExecute.subst(nolink_iop)
-
- # Generate declaration of '*AndLink' version, append to decls
- link_code = 'Ra = NPC & ~3;\n' + nolink_code
- link_iop = InstObjParams(name, Name + 'AndLink', base_class,
- CodeBlock(link_code), flags)
- header_output += BasicDeclare.subst(link_iop)
- decoder_output += BasicConstructor.subst(link_iop)
- exec_output += BasicExecute.subst(link_iop)
-
- # need to use link_iop for the decode template since it is expecting
- # the shorter version of class_name (w/o "AndLink")
-
- return (header_output, decoder_output,
- JumpOrBranchDecode.subst(nolink_iop), exec_output)
-
def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
postacc_code = '', base_class = 'Memory',
decode_template = BasicDecode, exec_template_base = ''):
@@ -116,10 +93,56 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
output exec {{
+using namespace MipsISA;
+
+
/// CLEAR ALL CPU INST/EXE HAZARDS
inline void
clear_exe_inst_hazards()
{
//CODE HERE
}
+
+
+ /// Check "FP enabled" machine status bit. Called when executing any FP
+ /// instruction in full-system mode.
+ /// @retval Full-system mode: NoFault if FP is enabled, FenFault
+ /// if not. Non-full-system mode: always returns NoFault.
+#if FULL_SYSTEM
+ inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+ {
+ Fault fault = NoFault; // dummy... this ipr access should not fault
+ if (!Mips34k::ICSR_FPE(xc->readIpr(MipsISA::IPR_ICSR, fault))) {
+ fault = FloatEnableFault;
+ }
+ return fault;
+ }
+#else
+ inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+ {
+ return NoFault;
+ }
+#endif
+
+ double convert_and_round(float w, int x, int y, int z)
+ {
+ double temp = .34000;
+
+ return temp;
+ }
+
+ enum FPTypes{
+ FP_SINGLE,
+ FP_DOUBLE,
+ FP_LONG,
+ FP_PS_LO,
+ FP_PS_HI,
+ FP_WORD,
+ RND_NEAREST,
+ RND_ZERO,
+ RND_UP,
+ RND_DOWN
+ };
}};
+
+
diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index 65ef2245f..13870337b 100644
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -16,21 +16,18 @@ def operands {{
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
- 'R31': ('IntReg', 'uw','R31','IsInteger', 4),
+ 'r31': ('IntReg', 'uw','R31','IsInteger', 4),
+ 'R0': ('IntReg', 'uw','R0', 'IsInteger', 5),
'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
- 'Sa': ('IntReg', 'uw', 'SA', 'IsInteger', 4),
'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
+ 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
- 'NNPC': ('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
- #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
- #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
- # The next two are hacks for non-full-system call-pal emulation
- #'R0': ('IntReg', 'uq', '0', None, 1),
+ 'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
}};
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 13:19:45 +0000