diff options
Diffstat (limited to 'arch/mips/isa')
| -rw-r--r-- | arch/mips/isa/base.isa | 2 | ||||
| -rw-r--r-- | arch/mips/isa/decoder.isa | 2 | ||||
| -rw-r--r-- | arch/mips/isa/formats/basic.isa | 2 | ||||
| -rw-r--r-- | arch/mips/isa/formats/branch.isa | 24 | ||||
| -rw-r--r-- | arch/mips/isa/operands.isa | 7 |
5 files changed, 23 insertions, 14 deletions
diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa index 99fa302c0..db37cf49c 100644 --- a/arch/mips/isa/base.isa +++ b/arch/mips/isa/base.isa @@ -16,7 +16,7 @@ output header {{ // Constructor. MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) - : StaticInst<SPARCISA>(mnem, _machInst, __opClass) + : StaticInst<MIPSISA>(mnem, _machInst, __opClass) { } diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index 997badb25..f46024f15 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -168,7 +168,7 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: decode REGIMM_LO { format Trap { 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); - 0x1: tgeiu({{ cond = (Rs.uw < INTIMM); }}); + 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); diff --git a/arch/mips/isa/formats/basic.isa b/arch/mips/isa/formats/basic.isa index 24c397685..3b62aa5c3 100644 --- a/arch/mips/isa/formats/basic.isa +++ b/arch/mips/isa/formats/basic.isa @@ -40,7 +40,7 @@ def template BasicExecute {{ if(fault == No_Fault) { - %(op_wb)s; + %(op_wb)s; } return fault; } diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa index d9dd433e3..1f7a6f330 100644 --- a/arch/mips/isa/formats/branch.isa +++ b/arch/mips/isa/formats/branch.isa @@ -45,12 +45,12 @@ output header {{ { protected: /// target address (signed) Displacement . - int32_t targetOffset; + int32_t disp; /// Constructor. Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : PCDependentDisassembly(mnem, _machInst, __opClass), - targetOffset(OFFSET << 2) + disp(OFFSET << 2) { } @@ -67,12 +67,12 @@ output header {{ { protected: /// target address (signed) Displacement . - int32_t targetOffset; + int32_t disp; /// Constructor. Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : PCDependentDisassembly(mnem, _machInst, __opClass), - targetOffset(OFFSET << 2) + disp(OFFSET << 2) { } @@ -255,9 +255,12 @@ def format Branch(code,*flags) {{ #Add Link Code if Link instruction strlen = len(name) if name[strlen-2:] == 'al': - code += 'R31 = NPC + 8;\n' + code += 'R31 = NPC + 4;\n' - code += '\nif (cond) NPC = NPC + disp;\n'; + # condition code + code += 'if (cond) {' + code += ' NPC = NPC + disp;\n' + code += ' NNPC = NNPC + disp;\n } \n' iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), ('IsDirectControl', 'IsCondControl')) @@ -267,15 +270,20 @@ def format Branch(code,*flags) {{ exec_output = BasicExecute.subst(iop) }}; + def format BranchLikely(code,*flags) {{ code = 'bool cond;\n\t\t\t' + code #Add Link Code if Link instruction strlen = len(name) if name[strlen-3:] == 'all': - code += 'R31 = NPC + 8;\n' + code += 'R31 = NPC + 4;\n' + + #condition code + code += 'if (cond) {' + code += ' NPC = NPC + disp;\n' + code += ' NNPC = NNPC + disp;\n } \n' - code = '\t\t\tif (cond) NPC = NPC + disp;\n'; iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), ('IsDirectControl', 'IsCondControl','IsCondDelaySlot')) diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa index 19d21ac8d..77035f04c 100644 --- a/arch/mips/isa/operands.isa +++ b/arch/mips/isa/operands.isa @@ -16,6 +16,7 @@ def operands {{ 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1), 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2), 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3), + 'R31': ('IntReg', 'uw','R31','IsInteger', 4), 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3), 'Sa': ('IntReg', 'uw', 'SA', 'IsInteger', 4), @@ -24,12 +25,12 @@ def operands {{ 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2), 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3), - 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4) + 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), - #'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4), + 'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4), + 'NNPC': ('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4) #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), # The next two are hacks for non-full-system call-pal emulation #'R0': ('IntReg', 'uq', '0', None, 1), - #'R31': ('IntReg', 'uw', '31', None, 1) }}; |