diff options
Diffstat (limited to 'arch/mips')
34 files changed, 3238 insertions, 1883 deletions
diff --git a/arch/mips/SConscript b/arch/mips/SConscript index b8efa7ef9..ef1ef25d6 100644 --- a/arch/mips/SConscript +++ b/arch/mips/SConscript @@ -57,9 +57,9 @@ full_system_sources = Split(''' # Syscall emulation (non-full-system) sources syscall_emulation_sources = Split(''' - common_syscall_emul.cc - linux_process.cc - tru64_process.cc + linux/linux.cc + linux/process.cc + process.cc ''') # Set up complete list of sources based on configuration. diff --git a/arch/mips/faults.cc b/arch/mips/faults.cc index 142dfe0a4..a31856f07 100644 --- a/arch/mips/faults.cc +++ b/arch/mips/faults.cc @@ -27,54 +27,115 @@ */ #include "arch/mips/faults.hh" +#include "cpu/exec_context.hh" +#include "cpu/base.hh" +#include "base/trace.hh" + +namespace MipsISA +{ + +FaultName MachineCheckFault::_name = "Machine Check"; +FaultVect MachineCheckFault::_vect = 0x0401; +FaultStat MachineCheckFault::_count; + +FaultName AlignmentFault::_name = "Alignment"; +FaultVect AlignmentFault::_vect = 0x0301; +FaultStat AlignmentFault::_count; + +FaultName ResetFault::_name = "reset"; +FaultVect ResetFault::_vect = 0x0001; +FaultStat ResetFault::_count; + +FaultName ArithmeticFault::_name = "arith"; +FaultVect ArithmeticFault::_vect = 0x0501; +FaultStat ArithmeticFault::_count; + +FaultName InterruptFault::_name = "interrupt"; +FaultVect InterruptFault::_vect = 0x0101; +FaultStat InterruptFault::_count; + +FaultName NDtbMissFault::_name = "dtb_miss_single"; +FaultVect NDtbMissFault::_vect = 0x0201; +FaultStat NDtbMissFault::_count; + +FaultName PDtbMissFault::_name = "dtb_miss_double"; +FaultVect PDtbMissFault::_vect = 0x0281; +FaultStat PDtbMissFault::_count; + +FaultName DtbPageFault::_name = "dfault"; +FaultVect DtbPageFault::_vect = 0x0381; +FaultStat DtbPageFault::_count; + +FaultName DtbAcvFault::_name = "dfault"; +FaultVect DtbAcvFault::_vect = 0x0381; +FaultStat DtbAcvFault::_count; + +FaultName ItbMissFault::_name = "itbmiss"; +FaultVect ItbMissFault::_vect = 0x0181; +FaultStat ItbMissFault::_count; + +FaultName ItbPageFault::_name = "itbmiss"; +FaultVect ItbPageFault::_vect = 0x0181; +FaultStat ItbPageFault::_count; + +FaultName ItbAcvFault::_name = "iaccvio"; +FaultVect ItbAcvFault::_vect = 0x0081; +FaultStat ItbAcvFault::_count; + +FaultName UnimplementedOpcodeFault::_name = "opdec"; +FaultVect UnimplementedOpcodeFault::_vect = 0x0481; +FaultStat UnimplementedOpcodeFault::_count; + +FaultName FloatEnableFault::_name = "fen"; +FaultVect FloatEnableFault::_vect = 0x0581; +FaultStat FloatEnableFault::_count; + +FaultName PalFault::_name = "pal"; +FaultVect PalFault::_vect = 0x2001; +FaultStat PalFault::_count; + +FaultName IntegerOverflowFault::_name = "intover"; +FaultVect IntegerOverflowFault::_vect = 0x0501; +FaultStat IntegerOverflowFault::_count; + +FaultName UnimpFault::_name = "Unimplemented Simulator feature"; +FaultVect UnimpFault::_vect = 0x0001; +FaultStat UnimpFault::_count; + +#if FULL_SYSTEM + +void MipsFault::invoke(ExecContext * xc) +{ + FaultBase::invoke(xc); + countStat()++; + + // exception restart address + if (setRestartAddress() || !xc->inPalMode()) + xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC()); + + if (skipFaultingInstruction()) { + // traps... skip faulting instruction. + xc->setMiscReg(MipsISA::IPR_EXC_ADDR, + xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4); + } + + xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect()); + xc->setNextPC(xc->readPC() + sizeof(MachInst)); +} + +void ArithmeticFault::invoke(ExecContext * xc) +{ + FaultBase::invoke(xc); + panic("Arithmetic traps are unimplemented!"); +} + +void UnimpFault::invoke(ExecContext * xc) +{ + FaultBase::invoke(xc); + panic("Unimpfault: %s\n", panicStr.c_str()); +} + +#endif + +} // namespace MipsISA -ResetFaultType * const ResetFault = - new ResetFaultType("reset", 1, 0x0001); -ArithmeticFaultType * const ArithmeticFault = - new ArithmeticFaultType("arith", 3, 0x0501); -InterruptFaultType * const InterruptFault = - new InterruptFaultType("interrupt", 4, 0x0101); -NDtbMissFaultType * const NDtbMissFault = - new NDtbMissFaultType("dtb_miss_single", 5, 0x0201); -PDtbMissFaultType * const PDtbMissFault = - new PDtbMissFaultType("dtb_miss_double", 6, 0x0281); -DtbPageFaultType * const DtbPageFault = - new DtbPageFaultType("dfault", 8, 0x0381); -DtbAcvFaultType * const DtbAcvFault = - new DtbAcvFaultType("dfault", 9, 0x0381); -ItbMissFaultType * const ItbMissFault = - new ItbMissFaultType("itbmiss", 10, 0x0181); -ItbPageFaultType * const ItbPageFault = - new ItbPageFaultType("itbmiss", 11, 0x0181); -ItbAcvFaultType * const ItbAcvFault = - new ItbAcvFaultType("iaccvio", 12, 0x0081); -UnimplementedOpcodeFaultType * const UnimplementedOpcodeFault = - new UnimplementedOpcodeFaultType("opdec", 13, 0x0481); -FloatEnableFaultType * const FloatEnableFault = - new FloatEnableFaultType("fen", 14, 0x0581); -PalFaultType * const PalFault = - new PalFaultType("pal", 15, 0x2001); -IntegerOverflowFaultType * const IntegerOverflowFault = - new IntegerOverflowFaultType("intover", 16, 0x0501); - -Fault ** ListOfFaults[] = { - (Fault **)&NoFault, - (Fault **)&ResetFault, - (Fault **)&MachineCheckFault, - (Fault **)&ArithmeticFault, - (Fault **)&InterruptFault, - (Fault **)&NDtbMissFault, - (Fault **)&PDtbMissFault, - (Fault **)&AlignmentFault, - (Fault **)&DtbPageFault, - (Fault **)&DtbAcvFault, - (Fault **)&ItbMissFault, - (Fault **)&ItbPageFault, - (Fault **)&ItbAcvFault, - (Fault **)&UnimplementedOpcodeFault, - (Fault **)&FloatEnableFault, - (Fault **)&PalFault, - (Fault **)&IntegerOverflowFault, - }; - -int NumFaults = sizeof(ListOfFaults) / sizeof(Fault **); diff --git a/arch/mips/faults.hh b/arch/mips/faults.hh index c1cb956b0..b0d228090 100644 --- a/arch/mips/faults.hh +++ b/arch/mips/faults.hh @@ -30,131 +30,260 @@ #define __MIPS_FAULTS_HH__ #include "sim/faults.hh" -#include "arch/isa_traits.hh" //For the Addr type + +// The design of the "name" and "vect" functions is in sim/faults.hh + +namespace MipsISA +{ + +typedef const Addr FaultVect; class MipsFault : public FaultBase { + protected: + virtual bool skipFaultingInstruction() {return false;} + virtual bool setRestartAddress() {return true;} public: - MipsFault(char * newName, int newId, Addr newVect) - : FaultBase(newName, newId), vect(newVect) - {;} +#if FULL_SYSTEM + void invoke(ExecContext * xc); +#endif + virtual FaultVect vect() = 0; + virtual FaultStat & countStat() = 0; +}; + +class MachineCheckFault : public MipsFault +{ + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; + public: + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} + bool isMachineCheckFault() {return true;} +}; + +class AlignmentFault : public MipsFault +{ + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; + public: + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} + bool isAlignmentFault() {return true;} +}; + +static inline Fault genMachineCheckFault() +{ + return new MachineCheckFault; +} + +static inline Fault genAlignmentFault() +{ + return new AlignmentFault; +} - Addr vect; +class ResetFault : public MipsFault +{ + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; + public: + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} }; -extern class ResetFaultType : public MipsFault +class ArithmeticFault : public MipsFault { + protected: + bool skipFaultingInstruction() {return true;} + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - ResetFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const ResetFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +#if FULL_SYSTEM + void invoke(ExecContext * xc); +#endif +}; -extern class ArithmeticFaultType : public MipsFault +class InterruptFault : public MipsFault { + protected: + bool setRestartAddress() {return false;} + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - ArithmeticFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const ArithmeticFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; -extern class InterruptFaultType : public MipsFault +class NDtbMissFault : public MipsFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - InterruptFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const InterruptFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; -extern class NDtbMissFaultType : public MipsFault +class PDtbMissFault : public MipsFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - NDtbMissFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const NDtbMissFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; -extern class PDtbMissFaultType : public MipsFault +class DtbPageFault : public MipsFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - PDtbMissFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const PDtbMissFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; -extern class DtbPageFaultType : public MipsFault +class DtbAcvFault : public MipsFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - DtbPageFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const DtbPageFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; -extern class DtbAcvFaultType : public MipsFault +class ItbMissFault : public MipsFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - DtbAcvFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const DtbAcvFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; -extern class ItbMissFaultType : public MipsFault +class ItbPageFault : public MipsFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - ItbMissFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const ItbMissFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; -extern class ItbPageFaultType : public MipsFault +class ItbAcvFault : public MipsFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - ItbPageFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const ItbPageFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; -extern class ItbAcvFaultType : public MipsFault +class UnimplementedOpcodeFault : public MipsFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - ItbAcvFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const ItbAcvFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; -extern class UnimplementedOpcodeFaultType : public MipsFault +class FloatEnableFault : public MipsFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const UnimplementedOpcodeFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; -extern class FloatEnableFaultType : public MipsFault +class PalFault : public MipsFault { + protected: + bool skipFaultingInstruction() {return true;} + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - FloatEnableFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const FloatEnableFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; -extern class PalFaultType : public MipsFault +class IntegerOverflowFault : public MipsFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - PalFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const PalFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; -extern class IntegerOverflowFaultType : public MipsFault +class UnimpFault : public MipsFault { + private: + std::string panicStr; + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; public: - IntegerOverflowFaultType(char * newName, int newId, Addr newVect) - : MipsFault(newName, newId, newVect) - {;} -} * const IntegerOverflowFault; + UnimpFault(std::string _str) + : panicStr(_str) + { } + + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +#if FULL_SYSTEM + void invoke(ExecContext * xc); +#endif +}; -extern Fault ** ListOfFaults[]; -extern int NumFaults; +} // MipsISA namespace #endif // __FAULTS_HH__ diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa index 4125b5101..b2a31c018 100644 --- a/arch/mips/isa/base.isa +++ b/arch/mips/isa/base.isa @@ -8,10 +8,6 @@ //Outputs to decoder.hh output header {{ -#define R31 31 -#include "arch/mips/faults.hh" -#include "arch/mips/isa_traits.hh" - using namespace MipsISA; @@ -66,27 +62,23 @@ output decoder {{ ccprintf(ss, "%-10s ", mnemonic); - // just print the first two source regs... if there's - // a third one, it's a read-modify-write dest (Rc), - // e.g. for CMOVxx - if(_numSrcRegs > 0) - { + if(_numDestRegs > 0){ + printReg(ss, _destRegIdx[0]); + } + + if(_numSrcRegs > 0) { + ss << ","; printReg(ss, _srcRegIdx[0]); } - if(_numSrcRegs > 1) - { + if(_numSrcRegs > 1) { ss << ","; printReg(ss, _srcRegIdx[1]); } - // just print the first dest... if there's a second one, - // it's generally implicit - if(_numDestRegs > 0) - { - if(_numSrcRegs > 0) - ss << ","; - printReg(ss, _destRegIdx[0]); + + if(mnemonic == "sll" || mnemonic == "sra"){ + ccprintf(ss,", %d",SA); } return ss.str(); diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa index 58d487ad2..e1124a591 100644 --- a/arch/mips/isa/bitfields.isa +++ b/arch/mips/isa/bitfields.isa @@ -26,6 +26,7 @@ def bitfield RS <25:21>; def bitfield RS_MSB <25:25>; def bitfield RS_HI <25:24>; def bitfield RS_LO <23:21>; +def bitfield RS_SRL <25:22>; def bitfield RD <15:11>; @@ -38,7 +39,6 @@ def bitfield FT <20:16>; def bitfield FS <15:11>; def bitfield FD <10:6>; -def bitfield CC <20:18>; def bitfield ND <17:17>; def bitfield TF <16:16>; def bitfield MOVCI <16:16>; @@ -47,6 +47,10 @@ def bitfield SRL <21:21>; def bitfield SRLV < 6: 6>; def bitfield SA <10: 6>; +// Floating Point Condition Codes +def bitfield CC <10:8>; +def bitfield BRANCH_CC <20:18>; + // CP0 Register Select def bitfield SEL < 2: 0>; diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index 3f054f6a5..1454aba39 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -1,4 +1,4 @@ -// -*- mode:c++ -*- + // -*- mode:c++ -*- //////////////////////////////////////////////////////////////////// // @@ -20,36 +20,53 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode FUNCTION_LO { 0x1: decode MOVCI { format BasicOp { - 0: movf({{ if (xc->readMiscReg(FPCR,0) != CC) Rd = Rs}}); - 1: movt({{ if (xc->readMiscReg(FPCR,0) == CC) Rd = Rs}}); + 0: movf({{ if (getFPConditionCode(FCSR, CC) == 0) Rd = Rs}}); + 1: movt({{ if (getFPConditionCode(FCSR, CC) == 1) Rd = Rs}}); } } format BasicOp { //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields - //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." - - 0x0: decode RS { - 0x0: decode RT default BasicOp::sll({{ Rd = Rt.uw << SA; }}) { - 0x0: decode RD{ - 0x0: decode HINT { - 0x0:nop({{}}); //really sll r0,r0,0 - 0x1:ssnop({{}});//really sll r0,r0,1 - 0x3:ehb({{}}); //really sll r0,r0,3 - } - } + //are used to distinguish among the SLL, NOP, SSNOP and EHB functions. + 0x0: decode RS { + 0x0: decode RT { //fix Nop traditional vs. Nop converted disassembly later + 0x0: decode RD default Nop::nop(){ + 0x0: decode SA { + 0x1: ssnop({{ ; }}); //really sll r0,r0,1 + 0x3: ehb({{ ; }}); //really sll r0,r0,3 + } + } + + default: sll({{ Rd = Rt.uw << SA; }}); } + } - 0x2: decode SRL { - 0: srl({{ Rd = Rt.uw >> SA; }}); + 0x2: decode RS_SRL { + 0x0:decode SRL { + 0: srl({{ Rd = Rt.uw >> SA; }}); - //Hardcoded assuming 32-bit ISA, probably need parameter here - 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); + //Hardcoded assuming 32-bit ISA, probably need parameter here + 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); + } } - 0x3: sra({{ Rd = Rt.sw >> SA; }}); + 0x3: decode RS { + 0x0: sra({{ + uint32_t temp = Rt >> SA; + + if ( (Rt & 0x80000000) > 0 ) { + uint32_t mask = 0x80000000; + for(int i=0; i < SA; i++) { + temp |= mask; + mask = mask >> 1; + } + } + + Rd = temp; + }}); + } 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); @@ -60,7 +77,21 @@ decode OPCODE_HI default Unknown::unknown() { 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); } - 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); + 0x7: srav({{ + int shift_amt = Rs<4:0>; + + uint32_t temp = Rt >> shift_amt; + + if ( (Rt & 0x80000000) > 0 ) { + uint32_t mask = 0x80000000; + for(int i=0; i < shift_amt; i++) { + temp |= mask; + mask = mask >> 1; + } + } + + Rd = temp; + }}); } } @@ -76,9 +107,9 @@ decode OPCODE_HI default Unknown::unknown() { } 0x1: decode HINT { - 0: jalr({{ NNPC = Rs; }},IsCall,IsReturn); + 0: jalr({{ Rd = NNPC; NNPC = Rs; }},IsCall,IsReturn); - 1: jalr_hb({{ NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); + 1: jalr_hb({{ Rd = NNPC; NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); } } @@ -87,65 +118,69 @@ decode OPCODE_HI default Unknown::unknown() { 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); } - format WarnUnimpl { - 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative - 0x5: break(); - 0x7: sync(); + format BasicOp { + 0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative); + 0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative); + 0x7: sync({{ panic("Not implemented sync yet"); }},IsNonSpeculative); } } 0x2: decode FUNCTION_LO { format BasicOp { - 0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }}); - 0x1: mthi({{ xc->setMiscReg(Hi,Rs); }}); - 0x2: mflo({{ Rd = xc->readMiscReg(Lo); }}); - 0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }}); + 0x0: mfhi({{ Rd = HI; }}); + 0x1: mthi({{ HI = Rs; }}); + 0x2: mflo({{ Rd = LO; }}); + 0x3: mtlo({{ LO = Rs; }}); } } 0x3: decode FUNCTION_LO { format IntOp { 0x0: mult({{ - int64_t temp1 = Rs.sw * Rt.sw; - xc->setMiscReg(Hi,temp1<63:32>); - xc->setMiscReg(Lo,temp1<31:0>); + int64_t temp1 = Rs.sd * Rt.sd; + HI = temp1<63:32>; + LO = temp1<31:0>; }}); 0x1: multu({{ - int64_t temp1 = Rs.uw * Rt.uw; - xc->setMiscReg(Hi,temp1<63:32>); - xc->setMiscReg(Lo,temp1<31:0>); + uint64_t temp1 = Rs.ud * Rt.ud; + HI = temp1<63:32>; + LO = temp1<31:0>; }}); 0x2: div({{ - xc->setMiscReg(Hi,Rs.sw % Rt.sw); - xc->setMiscReg(Lo,Rs.sw / Rt.sw); + HI = Rs.sd % Rt.sd; + LO = Rs.sd / Rt.sd; }}); 0x3: divu({{ - xc->setMiscReg(Hi,Rs.uw % Rt.uw); - xc->setMiscReg(Lo,Rs.uw / Rt.uw); + HI = Rs.ud % Rt.ud; + LO = Rs.ud / Rt.ud; }}); } } - 0x4: decode FUNCTION_LO { - format IntOp { - 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}}); - 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); - 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); - 0x3: subu({{ Rd.sw = Rs.sw - Rt.uw;}}); - 0x4: and({{ Rd = Rs & Rt;}}); - 0x5: or({{ Rd = Rs | Rt;}}); - 0x6: xor({{ Rd = Rs ^ Rt;}}); - 0x7: nor({{ Rd = ~(Rs | Rt);}}); + 0x4: decode HINT { + 0x0: decode FUNCTION_LO { + format IntOp { + 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}}); + 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); + 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); + 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); + 0x4: and({{ Rd = Rs & Rt;}}); + 0x5: or({{ Rd = Rs | Rt;}}); + 0x6: xor({{ Rd = Rs ^ Rt;}}); + 0x7: nor({{ Rd = ~(Rs | Rt);}}); + } } } - 0x5: decode FUNCTION_LO { - format IntOp{ - 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); - 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); + 0x5: decode HINT { + 0x0: decode FUNCTION_LO { + format IntOp{ + 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); + 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); + } } } @@ -169,7 +204,6 @@ decode OPCODE_HI default Unknown::unknown() { } format BranchLikely { - //MIPS obsolete instructions 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); } @@ -193,7 +227,6 @@ decode OPCODE_HI default Unknown::unknown() { } format BranchLikely { - //Will be removed in future MIPS releases 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn); 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn); } @@ -215,8 +248,13 @@ decode OPCODE_HI default Unknown::unknown() { format Branch { 0x4: beq({{ cond = (Rs.sw == Rt.sw); }}); 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); - 0x6: blez({{ cond = (Rs.sw <= 0); }}); - 0x7: bgtz({{ cond = (Rs.sw > 0); }}); + 0x6: decode RT { + 0x0: blez({{ cond = (Rs.sw <= 0); }}); + } + + 0x7: decode RT { + 0x0: bgtz({{ cond = (Rs.sw > 0); }}); + } } } @@ -225,11 +263,14 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); - 0x3: sltiu({{ Rt.sw = ( Rs.sw < imm ) ? 1 : 0 }}); - 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); - 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); - 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); - 0x7: lui({{ Rt = INTIMM << 16}}); + 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); + 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); + 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); + 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); + + 0x7: decode RS { + 0x0: lui({{ Rt = imm << 16}}); + } } } @@ -258,6 +299,7 @@ decode OPCODE_HI default Unknown::unknown() { //sel field. In those instances, the sel field must be zero. //MT Code Needed Here + }}); 0xC: mttr({{ @@ -283,55 +325,37 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode SC { 0x0: dvpe({{ - int idx; - int sel; - getMiscRegIdx(MVPControl,idx,sel); - Rt.sw = xc->readMiscReg(idx,sel); - xc->setMiscReg(idx,sel); + Rt.sw = xc->readMiscReg(MVPControl); + xc->setMiscReg(MVPControl,0); }}); 0x1: evpe({{ - int idx; - int sel; - getMiscRegIdx(MVPControl,idx,sel); - Rt.sw = xc->readMiscReg(idx,sel); - xc->setMiscReg(idx,sel,1); + Rt.sw = xc->readMiscReg(MVPControl); + xc->setMiscReg(MVPControl,1); }}); } 0x1: decode SC { 0x0: dmt({{ - int idx; - int sel; - getMiscRegIdx(VPEControl,idx,sel); - Rt.sw = xc->readMiscReg(idx,sel); - xc->setMiscReg(idx,sel); + Rt.sw = xc->readMiscReg(VPEControl); + xc->setMiscReg(VPEControl,0); }}); 0x1: emt({{ - int idx; - int sel; - getMiscRegIdx(VPEControl,idx,sel); - Rt.sw = xc->readMiscReg(idx,sel); - xc->setMiscReg(idx,sel,1); + Rt.sw = xc->readMiscReg(VPEControl); + xc->setMiscReg(VPEControl,1); }}); } 0xC: decode SC { 0x0: di({{ - int idx; - int sel; - getMiscRegIdx(Status,idx,sel); - Rt.sw = xc->readMiscReg(idx,sel); - xc->setMiscReg(idx,sel); + Rt.sw = xc->readMiscReg(Status); + xc->setMiscReg(Status,0); }}); 0x1: ei({{ - int idx; - int sel; - getMiscRegIdx(Status,idx,sel); - Rt.sw = xc->readMiscReg(idx,sel); - xc->setMiscReg(idx,sel,1); + Rt.sw = xc->readMiscReg(Status); + xc->setMiscReg(Status,1); }}); } } @@ -370,27 +394,91 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode RS_HI { 0x0: decode RS_LO { format FloatOp { - 0x0: mfc1({{ /*Rt.uw = Fs.ud<31:0>;*/ }}); - 0x2: cfc1({{ /*Rt.uw = xc->readMiscReg(FPCR[Fs]);*/}}); - 0x3: mfhc1({{ /*Rt.uw = Fs.ud<63:32>*/;}}); - 0x4: mtc1({{ /*Fs = Rt.uw*/}}); - 0x6: ctc1({{ /*xc->setMiscReg(FPCR[Fs],Rt);*/}}); - 0x7: mthc1({{ /*Fs<63:32> = Rt.uw*/}}); + 0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }}); + 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); + 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); + 0x7: mthc1({{ + uint64_t fs_hi = Rt.uw; + uint64_t fs_lo = Fs.ud & 0x0000FFFF; + Fs.ud = fs_hi << 32 | fs_lo; + }}); + } + + format System { + 0x2: cfc1({{ + switch (FS) + { + case 0: + Rt = FIR; + break; + case 25: + Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23; + break; + case 26: + Rt = 0 | (FCSR & 0x0003F07C); + break; + case 28: + Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003); + break; + case 31: + Rt = FCSR; + break; + default: + panic("FP Control Value (%d) Not Available. Ignoring Access to" + "Floating Control Status Register",FS); + } + }}); + + 0x6: ctc1({{ + switch (FS) + { + case 25: + FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25 + | (FCSR & 0x01000000) // bit 24 + | (FCSR & 0x004FFFFF);// bit 22...0 + break; + + case 26: + FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18 + | Rt.uw<17:12> << 12 // bit 17...12 + | (FCSR & 0x00000F80) << 7// bit 11...7 + | Rt.uw<6:2> << 2 // bit 6...2 + | (FCSR & 0x00000002); // bit 1...0 + break; + + case 28: + FCSR = 0 | (FCSR & 0xFE000000) // move 31...25 + | Rt.uw<2:2> << 24 // bit 24 + | (FCSR & 0x00FFF000) << 23// bit 23...12 + | Rt.uw<11:7> << 7 // bit 24 + | (FCSR & 0x000007E) + | Rt.uw<1:0>;// bit 22...0 + break; + + case 31: + FCSR = Rt.uw; + break; + + default: + panic("FP Control Value (%d) Not Available. Ignoring Access to" + "Floating Control Status Register", FS); + } + }}); } } 0x1: decode ND { 0x0: decode TF { format Branch { - 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }}); - 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }}); + 0x0: bc1f({{ cond = (getFPConditionCode(FCSR,CC) == 0); }}); + 0x1: bc1t({{ cond = (getFPConditionCode(FCSR,CC) == 1); }}); } } 0x1: decode TF { format BranchLikely { - 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }}); - 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }}); + 0x0: bc1fl({{ cond = (getFPConditionCode(FCSR,CC) == 0); }}); + 0x1: bc1tl({{ cond = (getFPConditionCode(FCSR,CC) == 1); }}); } } } @@ -401,164 +489,422 @@ decode OPCODE_HI default Unknown::unknown() { //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S //(( single-word )) - 0x0: decode RS_HI { - 0x0: decode RS_LO { + 0x0: decode FUNCTION_HI { + 0x0: decode FUNCTION_LO { format FloatOp { - 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); - 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); - 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); - 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); - 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); - 0x5: abss({{ Fd.sf = fabs(Fs.sf);}}); - 0x6: movs({{ Fd.sf = Fs.sf;}}); - 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); + 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); + 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); + 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); + 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); + 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); + 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); + 0x6: mov_s({{ Fd.sf = Fs.sf;}}); + 0x7: neg_s({{ Fd.sf = -1 * Fs.sf;}}); } } - 0x1: decode RS_LO { - //only legal for 64 bit-FP + 0x1: decode FUNCTION_LO { format Float64Op { - 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); - 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); - 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); - 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); + 0x0: round_l_s({{ + Fd.ud = fpConvert(roundFP(Fs.sf,0), SINGLE_TO_LONG); + }}); + + 0x1: trunc_l_s({{ + Fd.ud = fpConvert(truncFP(Fs.sf), SINGLE_TO_LONG); + }}); + + 0x2: ceil_l_s({{ + Fd.ud = fpConvert(ceil(Fs.sf), SINGLE_TO_LONG); + }}); + + 0x3: floor_l_s({{ + Fd.ud = fpConvert(floor(Fs.sf), SINGLE_TO_LONG); + }}); } format FloatOp { - 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); - 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); - 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); - 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); + 0x4: round_w_s({{ + Fd.uw = fpConvert(roundFP(Fs.sf,0), SINGLE_TO_WORD); + }}); + + 0x5: trunc_w_s({{ + Fd.uw = fpConvert(truncFP(Fs.sf), SINGLE_TO_WORD); + }}); + + 0x6: ceil_w_s({{ + Fd.uw = fpConvert(ceil(Fs.sf), SINGLE_TO_WORD); + }}); + + 0x7: floor_w_s({{ + Fd.uw = fpConvert(floor(Fs.sf), SINGLE_TO_WORD); + }}); } } - 0x2: decode RS_LO { + 0x2: decode FUNCTION_LO { 0x1: decode MOVCF { format FloatOp { - 0x0: movfs({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); - 0x1: movts({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); + 0x0: movf_s({{if (getFPConditionCode(FCSR,CC) == 0) Fd = Fs;}}); + 0x1: movt_s({{if (getFPConditionCode(FCSR,CC) == 1) Fd = Fs;}}); } } - format BasicOp { - 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); - 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); + format FloatOp { + 0x2: movz_s({{ if (Rt == 0) Fd = Fs; }}); + 0x3: movn_s({{ if (Rt != 0) Fd = Fs; }}); + 0x5: recip_s({{ Fd = 1 / Fs; }}); + 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); } + } - format Float64Op { - 0x5: recips({{ Fd = 1 / Fs; }}); - 0x6: rsqrts({{ Fd = 1 / sqrt((double)Fs.ud);}}); + 0x4: decode FUNCTION_LO { + + format FloatConvertOp { + 0x1: cvt_d_s({{ + Fd.ud = fpConvert(Fs.sf, SINGLE_TO_DOUBLE); + }}); + + 0x4: cvt_w_s({{ + Fd.uw = fpConvert(Fs.sf, SINGLE_TO_WORD); + }}); + } + + format FloatConvertOp { + 0x5: cvt_l_s({{ + Fd.ud = fpConvert(Fs.sf, SINGLE_TO_LONG); + }}); + + 0x6: cvt_ps_st({{ + Fd.ud = (uint64_t)Fs.uw << 32 | (uint64_t)Ft.uw; + }}); } } - 0x4: decode RS_LO { + 0x6: decode FUNCTION_LO { + format FloatCompareOp { + 0x0: c_f_s({{ cond = 0; }}); - format FloatOp { - 0x1: cvt_d_s({{ int rnd_mode = xc->readMiscReg(FCSR); - Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); + 0x1: c_un_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 1; + else + cond = 0; }}); - 0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR); - Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); + 0x2: c_eq_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 0; + else + cond = (Fs.sf == Ft.sf); }}); - } - //only legal for 64 bit - format Float64Op { - 0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR); - Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); + 0x3: c_ueq_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 1; + else + cond = (Fs.sf == Ft.sf); + }}); + + 0x4: c_olt_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 0; + else + cond = (Fs.sf < Ft.sf); }}); - 0x6: cvt_ps_s({{ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/ }}); + 0x5: c_ult_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 1; + else + cond = (Fs.sf < Ft.sf); + }}); + + 0x6: c_ole_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 0; + else + cond = (Fs.sf <= Ft.sf); + }}); + + 0x7: c_ule_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 1; + else + cond = (Fs.sf <= Ft.sf); + }}); + } + } + + 0x7: decode FUNCTION_LO { + format FloatCompareWithXcptOp { + 0x0: c_sf_s({{ cond = 0; }}); + + 0x1: c_ngle_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 1; + else + cond = 0; + }}); + + 0x2: c_seq_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 0; + else + cond = (Fs.sf == Ft.sf); + }}); + + 0x3: c_ngl_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 1; + else + cond = (Fs.sf == Ft.sf); + }}); + + 0x4: c_lt_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 0; + else + cond = (Fs.sf < Ft.sf); + }}); + + 0x5: c_nge_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 1; + else + cond = (Fs.sf < Ft.sf); + }}); + + 0x6: c_le_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 0; + else + cond = (Fs.sf <= Ft.sf); + }}); + + 0x7: c_ngt_s({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond = 1; + else + cond = (Fs.sf <= Ft.sf); + }}); } } } //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D - 0x1: decode RS_HI { - 0x0: decode RS_LO { + 0x1: decode FUNCTION_HI { + 0x0: decode FUNCTION_LO { format FloatOp { - 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); - 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); - 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); - 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); - 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); - 0x5: absd({{ Fd.df = fabs(Fs.df);}}); - 0x6: movd({{ Fd.df = Fs.df;}}); - 0x7: negd({{ Fd.df = -1 * Fs.df;}}); + 0x0: add_d({{ Fd.df = Fs.df + Ft.df;}}); + 0x1: sub_d({{ Fd.df = Fs.df - Ft.df;}}); + 0x2: mul_d({{ Fd.df = Fs.df * Ft.df;}}); + 0x3: div_d({{ Fd.df = Fs.df / Ft.df;}}); + 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df);}}); + 0x5: abs_d({{ Fd.df = fabs(Fs.df);}}); + 0x6: mov_d({{ Fd.ud = Fs.ud;}}); + 0x7: neg_d({{ Fd.df = -1 * Fs.df;}}); } } - 0x1: decode RS_LO { - //only legal for 64 bit - format Float64Op { - 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); - 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); - 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); - 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); + 0x1: decode FUNCTION_LO { + format FloatOp { + 0x0: round_l_d({{ + Fd.ud = fpConvert(roundFP(Fs.df,0), DOUBLE_TO_LONG); + }}); + + 0x1: trunc_l_d({{ + Fd.ud = fpConvert(truncFP(Fs.df), DOUBLE_TO_LONG); + }}); + + 0x2: ceil_l_d({{ + Fd.ud = fpConvert(ceil(Fs.df), DOUBLE_TO_LONG); + }}); + + 0x3: floor_l_d({{ + Fd.ud = fpConvert(floor(Fs.df), DOUBLE_TO_LONG); + }}); } format FloatOp { - 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); - 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); - 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); - 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); + 0x4: round_w_d({{ + Fd.uw = fpConvert(roundFP(Fs.df,0), DOUBLE_TO_WORD); + }}); + + 0x5: trunc_w_d({{ + Fd.uw = fpConvert(truncFP(Fs.df), DOUBLE_TO_WORD); + }}); + + 0x6: ceil_w_d({{ + Fd.uw = fpConvert(ceil(Fs.df), DOUBLE_TO_WORD); + }}); + + 0x7: floor_w_d({{ + Fd.uw = fpConvert(floor(Fs.df), DOUBLE_TO_WORD); + }}); } } - 0x2: decode RS_LO { + 0x2: decode FUNCTION_LO { 0x1: decode MOVCF { format FloatOp { - 0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }}); - 0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }}); + 0x0: movf_d({{if (getFPConditionCode(FCSR,CC) == 0) Fd.df = Fs.df; }}); + 0x1: movt_d({{if (getFPConditionCode(FCSR,CC) == 1) Fd.df = Fs.df; }}); } } format BasicOp { - 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }}); - 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }}); + 0x2: movz_d({{ if (Rt == 0) Fd.df = Fs.df; }}); + 0x3: movn_d({{ if (Rt != 0) Fd.df = Fs.df; }}); } - format Float64Op { - 0x5: recipd({{ Fd.df = 1 / Fs.df}}); - 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); + format FloatOp { + 0x5: recip_d({{ Fd.df = 1 / Fs.df}}); + 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }}); } } - 0x4: decode RS_LO { + 0x4: decode FUNCTION_LO { format FloatOp { 0x0: cvt_s_d({{ - int rnd_mode = xc->readMiscReg(FCSR); - Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); + Fd.uw = fpConvert(Fs.df, DOUBLE_TO_SINGLE); }}); 0x4: cvt_w_d({{ - int rnd_mode = xc->readMiscReg(FCSR); - Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); + Fd.uw = fpConvert(Fs.df, DOUBLE_TO_WORD); }}); - } - //only legal for 64 bit - format Float64Op { 0x5: cvt_l_d({{ - int rnd_mode = xc->readMiscReg(FCSR); - Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); + Fd.ud = fpConvert(Fs.df, DOUBLE_TO_LONG); + }}); + } + } + + 0x6: decode FUNCTION_LO { + format FloatCompareOp { + 0x0: c_f_d({{ cond = 0; }}); + + 0x1: c_un_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 1; + else + cond = 0; + }}); + + 0x2: c_eq_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 0; + else + cond = (Fs.df == Ft.df); }}); + + 0x3: c_ueq_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 1; + else + cond = (Fs.df == Ft.df); + }}); + + 0x4: c_olt_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 0; + else + cond = (Fs.df < Ft.df); + }}); + + 0x5: c_ult_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 1; + else + cond = (Fs.df < Ft.df); + }}); + + 0x6: c_ole_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 0; + else + cond = (Fs.df <= Ft.df); + }}); + + 0x7: c_ule_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 1; + else + cond = (Fs.df <= Ft.df); + }}); + } + } + + 0x7: decode FUNCTION_LO { + format FloatCompareWithXcptOp { + 0x0: c_sf_d({{ cond = 0; }}); + + 0x1: c_ngle_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 1; + else + cond = 0; + }}); + + 0x2: c_seq_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 0; + else + cond = (Fs.df == Ft.df); + }}); + + 0x3: c_ngl_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 1; + else + cond = (Fs.df == Ft.df); + }}); + + 0x4: c_lt_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 0; + else + cond = (Fs.df < Ft.df); + }}); + + 0x5: c_nge_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 1; + else + cond = (Fs.df < Ft.df); + }}); + + 0x6: c_le_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 0; + else + cond = (Fs.df <= Ft.df); + }}); + + 0x7: c_ngt_d({{ + if (isnan(Fs.df) || isnan(Ft.df)) + cond = 1; + else + cond = (Fs.df <= Ft.df); + }}); } } } //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 0x4: decode FUNCTION { - format FloatOp { - 0x20: cvt_s({{ - int rnd_mode = xc->readMiscReg(FCSR); - Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); + format FloatConvertOp { + 0x20: cvt_s_w({{ + Fd.uw = fpConvert(Fs.sf, WORD_TO_SINGLE); + }}); + + 0x21: cvt_d_w({{ + Fd.ud = fpConvert(Fs.sf, WORD_TO_DOUBLE); }}); + } - 0x21: cvt_d({{ - int rnd_mode = xc->readMiscReg(FCSR); - Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); + format Float64ConvertOp { + 0x26: cvt_ps_pw({{ + Fd.ud = fpConvert(Fs.ud, WORD_TO_PS); }}); } } @@ -567,15 +913,17 @@ decode OPCODE_HI default Unknown::unknown() { //Note: "1. Format type L is legal only if 64-bit floating point operations //are enabled." 0x5: decode FUNCTION_HI { - format FloatOp { - 0x10: cvt_s_l({{ - int rnd_mode = xc->readMiscReg(FCSR); - Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); + format Float64ConvertOp { + 0x20: cvt_s_l({{ + Fd.uw = fpConvert(Fs.ud, LONG_TO_SINGLE); + }}); + + 0x21: cvt_d_l({{ + Fd.ud = fpConvert(Fs.ud, LONG_TO_DOUBLE); }}); - 0x11: cvt_d_l({{ - int rnd_mode = xc->readMiscReg(FCSR); - Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); + 0x26: cvt_ps_l({{ + Fd.ud = fpConvert(Fs.ud, LONG_TO_PS); }}); } } @@ -583,73 +931,275 @@ decode OPCODE_HI default Unknown::unknown() { //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 //Note: "1. Format type PS is legal only if 64-bit floating point operations //are enabled. " - 0x6: decode RS_HI { - 0x0: decode RS_LO { + 0x6: decode FUNCTION_HI { + 0x0: decode FUNCTION_LO { format Float64Op { - 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and - //Lower Halves Independently but we take simulator shortcut - Fd.df = Fs.df + Ft.df; + 0x0: add_ps({{ + Fd1.sf = Fs1.sf + Ft2.sf; + Fd2.sf = Fs2.sf + Ft2.sf; }}); - 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and - //Lower Halves Independently but we take simulator shortcut - Fd.df = Fs.df - Ft.df; + 0x1: sub_ps({{ + Fd1.sf = Fs1.sf - Ft2.sf; + Fd2.sf = Fs2.sf - Ft2.sf; }}); - 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and - //Lower Halves Independently but we take simulator shortcut - Fd.df = Fs.df * Ft.df; + 0x2: mul_ps({{ + Fd1.sf = Fs1.sf * Ft2.sf; + Fd2.sf = Fs2.sf * Ft2.sf; }}); - 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and - //Lower Halves Independently but we take simulator shortcut - Fd.df = fabs(Fs.df); + 0x5: abs_ps({{ + Fd1.sf = fabs(Fs1.sf); + Fd2.sf = fabs(Fs2.sf); }}); - 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and - //Lower Halves Independently but we take simulator shortcut - //Fd.df = Fs<31:0> | Ft<31:0>; + 0x6: mov_ps({{ + Fd1.sf = Fs1.sf; + Fd2.sf = Fs2.sf; }}); - 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and - //Lower Halves Independently but we take simulator shortcut - Fd.df = -1 * Fs.df; + 0x7: neg_ps({{ + Fd1.sf = -1 * Fs1.sf; + Fd2.sf = -1 * Fs2.sf; }}); } } - 0x2: decode RS_LO { + 0x2: decode FUNCTION_LO { 0x1: decode MOVCF { format Float64Op { - 0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}}); - 0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); + 0x0: movf_ps({{ + if (getFPConditionCode(FCSR, CC) == 0) + Fd1 = Fs1; + if (getFPConditionCode(FCSR, CC+1) == 0) + Fd2 = Fs2; + }}); + + 0x1: movt_ps({{ + if (getFPConditionCode(FCSR, CC) == 1) + Fd1 = Fs1; + if (getFPConditionCode(FCSR, CC+1) == 1) + Fd2 = Fs2; + }}); } } - format BasicOp { - 0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); - 0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }}); + format Float64Op { + 0x2: movz_ps({{ + if (getFPConditionCode(FCSR, CC) == 0) + Fd1 = Fs1; + if (getFPConditionCode(FCSR, CC) == 0) + Fd2 = Fs2; + }}); + + 0x3: movn_ps({{ + if (getFPConditionCode(FCSR, CC) == 1) + Fd1 = Fs1; + if (getFPConditionCode(FCSR, CC) == 1) + Fd2 = Fs2; + }}); } } - 0x4: decode RS_LO { + 0x4: decode FUNCTION_LO { 0x0: Float64Op::cvt_s_pu({{ - int rnd_mode = xc->readMiscReg(FCSR); - Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); + Fd.uw = fpConvert(Fs2.uw, PU_TO_SINGLE); }}); } - 0x5: decode RS_LO { + 0x5: decode FUNCTION_LO { format Float64Op { 0x0: cvt_s_pl({{ - int rnd_mode = xc->readMiscReg(FCSR); - Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); + Fd.uw = fpConvert(Fs1.uw, PL_TO_SINGLE); }}); - 0x4: pll({{ /*Fd.df = Fs<31:0> | Ft<31:0>*/}}); - 0x5: plu({{ /*Fd.df = Fs<31:0> | Ft<63:32>*/}}); - 0x6: pul({{ /*Fd.df = Fs<63:32> | Ft<31:0>*/}}); - 0x7: puu({{ /*Fd.df = Fs<63:32 | Ft<63:32>*/}}); + + 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | Ft1.uw; }}); + 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | Ft2.uw; }}); + 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | Ft1.uw; }}); + 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | Ft2.uw; }}); + } + } + + 0x6: decode FUNCTION_LO { + format FloatPSCompareOp { + 0x0: c_f_ps({{ cond1 = 0; cond2 = 0; }}); + + 0x1: c_un_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 1; + else + cond1 = 0; + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 1; + else + cond2 = 0; + + }}); + + 0x2: c_eq_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 0; + else + cond1 = (Fs1.sf == Ft1.sf); + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 0; + else + cond2 = (Fs2.sf == Ft2.sf); + }}); + + 0x3: c_ueq_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 1; + else + cond1 = (Fs1.sf == Ft1.sf); + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 1; + else + cond2 = (Fs2.sf == Ft2.sf); + }}); + + 0x4: c_olt_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 0; + else + cond1 = (Fs1.sf < Ft1.sf); + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 0; + else + cond2 = (Fs2.sf < Ft2.sf); + }}); + + 0x5: c_ult_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 1; + else + cond1 = (Fs.sf < Ft.sf); + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 1; + else + cond2 = (Fs2.sf < Ft2.sf); + }}); + + 0x6: c_ole_ps({{ + if (isnan(Fs.sf) || isnan(Ft.sf)) + cond1 = 0; + else + cond1 = (Fs.sf <= Ft.sf); + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 0; + else + cond2 = (Fs2.sf <= Ft2.sf); + }}); + + 0x7: c_ule_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 1; + else + cond1 = (Fs1.sf <= Ft1.sf); + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 1; + else + cond2 = (Fs2.sf <= Ft2.sf); + }}); + } + } + + 0x7: decode FUNCTION_LO { + format FloatPSCompareWithXcptOp { + 0x0: c_sf_ps({{ cond1 = 0; cond2 = 0; }}); + + 0x1: c_ngle_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 1; + else + cond1 = 0; + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 1; + else + cond2 = 0; + }}); + + 0x2: c_seq_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 0; + else + cond1 = (Fs1.sf == Ft1.sf); + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 0; + else + cond2 = (Fs2.sf == Ft2.sf); + }}); + + 0x3: c_ngl_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 1; + else + cond1 = (Fs1.sf == Ft1.sf); + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 1; + else + cond2 = (Fs2.sf == Ft2.sf); + }}); + + 0x4: c_lt_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 0; + else + cond1 = (Fs1.sf < Ft1.sf); + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 0; + else + cond2 = (Fs2.sf < Ft2.sf); + }}); + + 0x5: c_nge_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 1; + else + cond1 = (Fs1.sf < Ft1.sf); + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 1; + else + cond2 = (Fs2.sf < Ft2.sf); + }}); + + 0x6: c_le_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 0; + else + cond1 = (Fs1.sf <= Ft1.sf); + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 0; + else + cond2 = (Fs2.sf <= Ft2.sf); + }}); + + 0x7: c_ngt_ps({{ + if (isnan(Fs1.sf) || isnan(Ft1.sf)) + cond1 = 1; + else + cond1 = (Fs1.sf <= Ft1.sf); + + if (isnan(Fs2.sf) || isnan(Ft2.sf)) + cond2 = 1; + else + cond2 = (Fs2.sf <= Ft2.sf); + }}); } } } @@ -694,24 +1244,18 @@ decode OPCODE_HI default Unknown::unknown() { //operations are enabled." 0x3: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { - format LoadMemory2 { - 0x0: lwxc1({{ EA = Rs + Rt; }},{{ /*F_t<31:0> = Mem.sf; */}}); - 0x1: ldxc1({{ EA = Rs + Rt; }},{{ /*F_t<63:0> = Mem.df;*/ }}); - 0x5: luxc1({{ //Need to make EA<2:0> = 0 - EA = Rs + Rt; - }}, - {{ /*F_t<31:0> = Mem.df; */}}); + format LoadFloatMemory { + 0x0: lwxc1({{ Ft.uw = Mem.uw;}}, {{ EA = Rs + Rt; }}); + 0x1: ldxc1({{ Ft.ud = Mem.ud;}}, {{ EA = Rs + Rt; }}); + 0x5: luxc1({{ Ft.uw = Mem.ud;}}, {{ EA = Rs + Rt; }}); } } 0x1: decode FUNCTION_LO { - format StoreMemory2 { - 0x0: swxc1({{ EA = Rs + Rt; }},{{ /*Mem.sf = Ft<31:0>; */}}); - 0x1: sdxc1({{ EA = Rs + Rt; }},{{ /*Mem.df = Ft<63:0> */}}); - 0x5: suxc1({{ //Need to make EA<2:0> = 0 - EA = Rs + Rt; - }}, - {{ /*Mem.df = F_t<63:0>;*/}}); + format StoreFloatMemory { + 0x0: swxc1({{ Mem.uw = Ft.uw;}}, {{ EA = Rs + Rt; }}); + 0x1: sdxc1({{ Mem.ud = Ft.ud;}}, {{ EA = Rs + Rt; }}); + 0x5: suxc1({{ Mem.ud = Ft.ud;}}, {{ EA = Rs + Rt; }}); } 0x7: WarnUnimpl::prefx(); @@ -722,49 +1266,44 @@ decode OPCODE_HI default Unknown::unknown() { format BasicOp { 0x4: decode FUNCTION_LO { - 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); - 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); + 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); + 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 0x6: madd_ps({{ - //Must Check for Exception Here... Supposed to Operate on Upper and - //Lower Halves Independently but we take simulator shortcut - Fd.df = (Fs.df * Fs.df) + Fr.df; + Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; + Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df; }}); } 0x5: decode FUNCTION_LO { - 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); - 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); + 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }}); + 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }}); 0x6: msub_ps({{ - //Must Check for Exception Here... Supposed to Operate on Upper and - //Lower Halves Independently but we take simulator shortcut - Fd.df = (Fs.df * Fs.df) - Fr.df; + Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df; + Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df; }}); } 0x6: decode FUNCTION_LO { - 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); - 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); + 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); + 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }}); 0x6: nmadd_ps({{ - //Must Check for Exception Here... Supposed to Operate on Upper and - //Lower Halves Independently but we take simulator shortcut - Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; + Fd1.sf = -1 * ((Fs1.df * Ft1.df) + Fr1.df); + Fd2.sf = -1 * ((Fs2.df * Ft2.df) + Fr2.df); }}); } 0x7: decode FUNCTION_LO { - 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); - 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); + 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); + 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 0x6: nmsub_ps({{ - //Must Check for Exception Here... Supposed to Operate on Upper and - //Lower Halves Independently but we take simulator shortcut - Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; + Fd1.sf = -1 * ((Fs1.df * Ft1.df) - Fr1.df); + Fd2.sf = -1 * ((Fs2.df * Ft2.df) - Fr2.df); }}); } } } } - //MIPS obsolete instructions format BranchLikely { 0x4: beql({{ cond = (Rs.sw == 0); }}); 0x5: bnel({{ cond = (Rs.sw != 0); }}); @@ -781,59 +1320,63 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode FUNCTION_LO { format IntOp { 0x0: madd({{ - int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; + int64_t temp1 = (int64_t) HI << 32 | LO; temp1 = temp1 + (Rs.sw * Rt.sw); - xc->setMiscReg(Hi,temp1<63:32>); - xc->setMiscReg(Lo,temp1<31:0>); - }}); + HI = temp1<63:32>; + LO = temp1<31:0>; + }}); 0x1: maddu({{ - int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; + int64_t temp1 = (int64_t) HI << 32 | LO; temp1 = temp1 + (Rs.uw * Rt.uw); - xc->setMiscReg(Hi,temp1<63:32>); - xc->setMiscReg(Lo,temp1<31:0>); - }}); + HI = temp1<63:32>; + LO = temp1<31:0>; + }}); 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 0x4: msub({{ - int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; + int64_t temp1 = (int64_t) HI << 32 | LO; temp1 = temp1 - (Rs.sw * Rt.sw); - xc->setMiscReg(Hi,temp1<63:32>); - xc->setMiscReg(Lo,temp1<31:0>); - }}); + HI = temp1<63:32>; + LO = temp1<31:0>; + }}); 0x5: msubu({{ - int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; + int64_t temp1 = (int64_t) HI << 32 | LO; temp1 = temp1 - (Rs.uw * Rt.uw); - xc->setMiscReg(Hi,temp1<63:32>); - xc->setMiscReg(Lo,temp1<31:0>); - }}); + HI = temp1<63:32>; + LO = temp1<31:0>; + }}); } } 0x4: decode FUNCTION_LO { format BasicOp { 0x0: clz({{ - /*int cnt = 0; - int idx = 0; - while ( Rs.uw<idx> != 1) { - cnt++; - idx--; + int cnt = 0; + uint32_t mask = 0x80000000; + for (int i=0; i < 32; i++) { + if( (Rs & mask) == 0) { + cnt++; + } else { + break; + } } - - Rd.uw = cnt;*/ + Rd.uw = cnt; }}); 0x1: clo({{ - /*int cnt = 0; - int idx = 0; - while ( Rs.uw<idx> != 0) { - cnt++; - idx--; + int cnt = 0; + uint32_t mask = 0x80000000; + for (int i=0; i < 32; i++) { + if( (Rs & mask) != 0) { + cnt++; + } else { + break; + } } - - Rd.uw = cnt;*/ + Rd.uw = cnt; }}); } } @@ -847,14 +1390,14 @@ decode OPCODE_HI default Unknown::unknown() { 0x7: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { - format WarnUnimpl { + format FailUnimpl { 0x1: ext(); 0x4: ins(); } } 0x1: decode FUNCTION_LO { - format WarnUnimpl { + format FailUnimpl { 0x0: fork(); 0x1: yield(); } @@ -864,16 +1407,16 @@ decode OPCODE_HI default Unknown::unknown() { //Table A-10 MIPS32 BSHFL Encoding of sa Field 0x4: decode SA { - 0x02: WarnUnimpl::wsbh(); + 0x02: FailUnimpl::wsbh(); format BasicOp { - 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}}); - 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}}); + 0x10: seb({{ Rd.sw = Rt.sw<7:0>}}); + 0x18: seh({{ Rd.sw = Rt.sw<15:0>}}); } } 0x6: decode FUNCTION_LO { - 0x7: BasicOp::rdhwr({{ /*Rt = xc->hwRegs[RD];*/ }}); + 0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }} } } } @@ -882,23 +1425,238 @@ decode OPCODE_HI default Unknown::unknown() { format LoadMemory { 0x0: lb({{ Rt.sw = Mem.sb; }}); 0x1: lh({{ Rt.sw = Mem.sh; }}); - 0x2: lwl({{ Rt.sw = Mem.sw; }});//, WordAlign); - 0x3: lw({{ Rt.sw = Mem.sb; }}); + + 0x2: lwl({{ + uint32_t mem_word = Mem.uw; + uint32_t unalign_addr = Rs + disp; + uint32_t offset = unalign_addr & 0x00000003; +#if BYTE_ORDER == BIG_ENDIAN + switch(offset) + { + case 0: + Rt = mem_word; + break; + + case 1: + Rt &= 0x000F; + Rt |= (mem_word << 4); + break; + + case 2: + Rt &= 0x00FF; + Rt |= (mem_word << 8); + break; + + case 3: + Rt &= 0x0FFF; + Rt |= (mem_word << 12); + break; + + default: + panic("lwl: bad offset"); + } +#elif BYTE_ORDER == LITTLE_ENDIAN + switch(offset) + { + case 0: + Rt &= 0x0FFF; + Rt |= (mem_word << 12); + break; + + case 1: + Rt &= 0x00FF; + Rt |= (mem_word << 8); + break; + + case 2: + Rt &= 0x000F; + Rt |= (mem_word << 4); + break; + + case 3: + Rt = mem_word; + break; + + default: + panic("lwl: bad offset"); + } +#endif + }}, {{ EA = (Rs + disp) & ~3; }}); + + 0x3: lw({{ Rt.sw = Mem.sw; }}); 0x4: lbu({{ Rt.uw = Mem.ub; }}); 0x5: lhu({{ Rt.uw = Mem.uh; }}); - 0x6: lwr({{ Rt.uw = Mem.uw; }});//, WordAlign); + 0x6: lwr({{ + uint32_t mem_word = Mem.uw; + uint32_t unalign_addr = Rs + disp; + uint32_t offset = unalign_addr & 0x00000003; + +#if BYTE_ORDER == BIG_ENDIAN + switch(offset) + { + case 0: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; + case 1: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; + case 2: Rt &= 0xF000; Rt |= (mem_word >> 4); break; + case 3: Rt = mem_word; break; + default: panic("lwr: bad offset"); + } +#elif BYTE_ORDER == LITTLE_ENDIAN + switch(offset) + { + case 0: Rt = mem_word; break; + case 1: Rt &= 0xF000; Rt |= (mem_word >> 4); break; + case 2: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; + case 3: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; + default: panic("lwr: bad offset"); + } +#endif + }}, + {{ EA = (Rs + disp) & ~3; }}); } - - 0x7: FailUnimpl::reserved(); } 0x5: decode OPCODE_LO default FailUnimpl::reserved() { format StoreMemory { 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 0x1: sh({{ Mem.uh = Rt<15:0>; }}); - 0x2: swl({{ Mem.ub = Rt<31:0>; }});//,WordAlign); - 0x3: sw({{ Mem.ub = Rt<31:0>; }}); - 0x6: swr({{ Mem.ub = Rt<31:0>; }});//,WordAlign); + 0x2: swl({{ + uint32_t mem_word = 0; + uint32_t aligned_addr = (Rs + disp) & ~3; + uint32_t unalign_addr = Rs + disp; + uint32_t offset = unalign_addr & 0x00000003; + + DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x", + aligned_addr,unalign_addr,offset); + + fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); + +#if BYTE_ORDER == BIG_ENDIAN + switch(offset) + { + case 0: + Mem = Rt; + break; + + case 1: + mem_word &= 0xF000; + mem_word |= (Rt >> 4); + Mem = mem_word; + break; + + case 2: + mem_word &= 0xFF00; + mem_word |= (Rt >> 8); + Mem = mem_word; + break; + + case 3: + mem_word &= 0xFFF0; + mem_word |= (Rt >> 12); + Mem = mem_word; + break; + + default: + panic("swl: bad offset"); + } +#elif BYTE_ORDER == LITTLE_ENDIAN + switch(offset) + { + case 0: + mem_word &= 0xFFF0; + mem_word |= (Rt >> 12); + Mem = mem_word; + break; + + case 1: + mem_word &= 0xFF00; + mem_word |= (Rt >> 8); + Mem = mem_word; + break; + + case 2: + mem_word &= 0xF000; + mem_word |= (Rt >> 4); + Mem = mem_word; + break; + + case 3: + Mem = Rt; + break; + + default: + panic("swl: bad offset"); + } +#endif + }},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT); + + 0x3: sw({{ Mem.uw = Rt<31:0>; }}); + + 0x6: swr({{ + uint32_t mem_word = 0; + uint32_t aligned_addr = (Rs + disp) & ~3; + uint32_t unalign_addr = Rs + disp; + uint32_t offset = unalign_addr & 0x00000003; + + fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); + +#if BYTE_ORDER == BIG_ENDIAN + switch(offset) + { + case 0: + mem_word &= 0x0FFF; + mem_word |= (Rt << 12); + Mem = mem_word; + break; + + case 1: + mem_word &= 0x00FF; + mem_word |= (Rt << 8); + Mem = mem_word; + break; + + case 2: + mem_word &= 0x000F; + mem_word |= (Rt << 4); + Mem = mem_word; + break; + + case 3: + Mem = Rt; + break; + + default: + panic("swr: bad offset"); + } +#elif BYTE_ORDER == LITTLE_ENDIAN + switch(offset) + { + case 0: + Mem = Rt; + break; + + case 1: + mem_word &= 0x000F; + mem_word |= (Rt << 4); + Mem = mem_word; + break; + + case 2: + mem_word &= 0x00FF; + mem_word |= (Rt << 8); + Mem = mem_word; + break; + + case 3: + mem_word &= 0x0FFF; + mem_word |= (Rt << 12); + Mem = mem_word; + break; + + default: + panic("swr: bad offset"); + } +#endif + }},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT); } format WarnUnimpl { @@ -908,21 +1666,21 @@ decode OPCODE_HI default Unknown::unknown() { } 0x6: decode OPCODE_LO default FailUnimpl::reserved() { - 0x0: WarnUnimpl::ll(); + 0x0: LoadMemory::ll({{Rt.uw = Mem.uw}},mem_flags=LOCKED); - format LoadMemory { - 0x1: lwc1({{ /*F_t<31:0> = Mem.sf; */}}); - 0x5: ldc1({{ /*F_t<63:0> = Mem.df; */}}); + format LoadFloatMemory { + 0x1: lwc1({{ Ft.uw = Mem.uw; }}); + 0x5: ldc1({{ Ft.ud = Mem.ud; }}); } } 0x7: decode OPCODE_LO default FailUnimpl::reserved() { - 0x0: WarnUnimpl::sc(); + 0x0: StoreMemory::sc({{ Mem.uw = Rt.uw; Rt.uw = 1; }}); - format StoreMemory { - 0x1: swc1({{ //Mem.sf = Ft<31:0>; }}); - 0x5: sdc1({{ //Mem.df = Ft<63:0>; }}); + format StoreFloatMemory { + 0x1: swc1({{ Mem.uw = Ft.uw; }}); + 0x5: sdc1({{ Mem.ud = Ft.ud; }}); } } } diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa deleted file mode 100644 index f7a9e4ce2..000000000 --- a/arch/mips/isa/formats.isa +++ /dev/null @@ -1,35 +0,0 @@ -// -*- mode:c++ -*- - -//Templates from this format are used later -//Include the basic format -##include "m5/arch/mips/isa/formats/basic.isa" - -//Include the basic format -##include "m5/arch/mips/isa/formats/noop.isa" - -//Include utility formats/functions -##include "m5/arch/mips/isa/formats/util.isa" - -//Include the cop0 formats -##include "m5/arch/mips/isa/formats/cop0.isa" - -//Include the integer formats -##include "m5/arch/mips/isa/formats/int.isa" - -//Include the floatOp format -##include "m5/arch/mips/isa/formats/fp.isa" - -//Include the mem format -##include "m5/arch/mips/isa/formats/mem.isa" - -//Include the trap format -##include "m5/arch/mips/isa/formats/trap.isa" - -//Include the branch format -##include "m5/arch/mips/isa/formats/branch.isa" - -//Include the noop format -##include "m5/arch/mips/isa/formats/unimp.isa" - -//Include the noop format -##include "m5/arch/mips/isa/formats/unknown.isa" diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa index 0d2ad7855..8cfa37a20 100644 --- a/arch/mips/isa/formats/branch.isa +++ b/arch/mips/isa/formats/branch.isa @@ -179,7 +179,7 @@ output decoder {{ ss << ","; } - Addr target = pc + 8 + disp; + Addr target = pc + 4 + disp; std::string str; if (symtab && symtab->findSymbol(target, str)) @@ -187,6 +187,12 @@ output decoder {{ else ccprintf(ss, "0x%x", target); + string inst_name = mnemonic; + + if (inst_name.substr(inst_name.length()-2,inst_name.length()) == "al"){ + ccprintf(ss, " (r31=0x%x)",pc+8); + } + return ss.str(); } @@ -255,7 +261,7 @@ def format Branch(code,*flags) {{ #Add Link Code if Link instruction strlen = len(name) if name[strlen-2:] == 'al': - code += 'r31 = NNPC;\n' + code += 'R31 = NNPC;\n' #Condition code code = 'bool cond;\n' + code @@ -265,8 +271,6 @@ def format Branch(code,*flags) {{ code += ' NNPC = NNPC;\n' code += '} \n' - code += 'cout << hex << "NPC: " << NPC << " + " << disp << " = " << NNPC << endl;' - iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), ('IsDirectControl', 'IsCondControl')) @@ -281,7 +285,7 @@ def format BranchLikely(code,*flags) {{ #Add Link Code if Link instruction strlen = len(name) if name[strlen-3:] == 'all': - code += 'r31 = NNPC;\n' + code += 'R31 = NNPC;\n' #Condition code code = 'bool cond;\n' + code @@ -303,10 +307,8 @@ def format Jump(code,*flags) {{ #Add Link Code if Link instruction strlen = len(name) if strlen > 1 and name[1:] == 'al': - code = 'r31 = NNPC;\n' + code + code = 'R31 = NNPC;\n' + code - #code += 'if(NNPC == 0x80000638) { NNPC = r31; cout << "SKIPPING JUMP TO SIM_GET_MEM_CONF" << endl;}' - #code += 'target = NNPC;' iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\ ('IsIndirectControl', 'IsUncondControl')) diff --git a/arch/mips/isa/formats/formats.isa b/arch/mips/isa/formats/formats.isa new file mode 100644 index 000000000..7d493ffae --- /dev/null +++ b/arch/mips/isa/formats/formats.isa @@ -0,0 +1,35 @@ +// -*- mode:c++ -*- + +//Templates from this format are used later +//Include the basic format +##include "basic.isa" + +//Include the basic format +##include "noop.isa" + +//Include utility functions +##include "util.isa" + +//Include the cop0 formats +##include "cop0.isa" + +//Include the integer formats +##include "int.isa" + +//Include the floatOp format +##include "fp.isa" + +//Include the mem format +##include "mem.isa" + +//Include the trap format +##include "trap.isa" + +//Include the branch format +##include "branch.isa" + +//Include the noop format +##include "unimp.isa" + +//Include the noop format +##include "unknown.isa" diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa index 34b71acf7..9f2c24755 100644 --- a/arch/mips/isa/formats/fp.isa +++ b/arch/mips/isa/formats/fp.isa @@ -30,7 +30,7 @@ output decoder {{ }}; -// Primary format for integer operate instructions: +// Primary format for float operate instructions: def format FloatOp(code, *flags) {{ iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) header_output = BasicDeclare.subst(iop) @@ -39,7 +39,35 @@ def format FloatOp(code, *flags) {{ exec_output = BasicExecute.subst(iop) }}; -// Primary format for integer operate instructions: +def format FloatCompareOp(code, *flags) {{ + code = 'bool cond;\n' + code + code += 'FCSR = makeCCVector(FCSR, CC,cond);\n' + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; + +def format FloatCompareWithXcptOp(code, *flags) {{ + code = 'bool cond;\n' + code + code += 'FCSR = makeCCVector(FCSR, CC,cond);\n' + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; + +def format FloatConvertOp(code, *flags) {{ + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; + +// Primary format for float64 operate instructions: def format Float64Op(code, *flags) {{ iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) header_output = BasicDeclare.subst(iop) @@ -47,3 +75,35 @@ def format Float64Op(code, *flags) {{ decode_block = BasicDecode.subst(iop) exec_output = BasicExecute.subst(iop) }}; + +def format Float64ConvertOp(code, *flags) {{ + code = 'bool cond;\n' + code + code += 'FCSR = makeCCVector(FCSR, CC,cond);\n' + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; + +def format FloatPSCompareOp(code, *flags) {{ + code = 'bool cond1;\nbool cond2;\n' + code + code += 'FCSR = makeCCVector(FCSR, CC+1, cond1);\n' + code += 'FCSR = makeCCVector(FCSR, CC, cond2);\n' + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; + +def format FloatPSCompareWithXcptOp(code, *flags) {{ + code = 'bool cond1;\nbool cond2;\n' + code + code += 'FCSR = makeCCVector(FCSR, CC+1, cond1);\n' + code += 'FCSR = makeCCVector(FCSR, CC, cond2);\n' + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa index a47844bee..7d38b9ff5 100644 --- a/arch/mips/isa/formats/int.isa +++ b/arch/mips/isa/formats/int.isa @@ -29,17 +29,19 @@ output header {{ { protected: - int32_t imm; + int16_t imm; + int32_t sextImm; + uint32_t zextImm; /// Constructor IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM) + MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM), + sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM) { //If Bit 15 is 1 then Sign Extend - int32_t temp = imm & 0x00008000; - + int32_t temp = sextImm & 0x00008000; if (temp > 0 && mnemonic != "lui") { - imm |= 0xFFFF0000; + sextImm |= 0xFFFF0000; } } @@ -62,10 +64,9 @@ output decoder {{ // it's generally implicit if (_numDestRegs > 0) { printReg(ss, _destRegIdx[0]); + ss << ","; } - ss << ","; - // just print the first two source regs... if there's // a third one, it's a read-modify-write dest (Rc), // e.g. for CMOVxx @@ -99,9 +100,9 @@ output decoder {{ } if( mnemonic == "lui") - ccprintf(ss, "%08p ", imm); + ccprintf(ss, "%08p ", sextImm); else - ss << (int) imm; + ss << (int) sextImm; return ss.str(); } diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa index 8a07e63d4..e2afc7252 100644 --- a/arch/mips/isa/formats/mem.isa +++ b/arch/mips/isa/formats/mem.isa @@ -276,8 +276,7 @@ def template LoadCompleteAcc {{ Fault fault = NoFault; %(fp_enable_check)s; - %(op_src_decl)s; - %(op_dest_decl)s; + %(op_decl)s; memcpy(&Mem, data, sizeof(Mem)); @@ -375,8 +374,7 @@ def template StoreInitiateAcc {{ uint64_t write_result = 0; %(fp_enable_check)s; - %(op_src_decl)s; - %(op_dest_decl)s; + %(op_decl)s; %(op_rd)s; %(ea_code)s; @@ -449,21 +447,27 @@ def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, }}; //FP loads are offloaded to these formats for now ... -def format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }}, - mem_flags = [], inst_flags = []) {{ +def format LoadFloatMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, + mem_flags = [], inst_flags = []) {{ (header_output, decoder_output, decode_block, exec_output) = \ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - decode_template = LoadNopCheckDecode, + decode_template = BasicDecode, exec_template_base = 'Load') }}; -//FP stores are offloaded to these formats for now ... -def format StoreMemory2(ea_code = {{ EA = Rs + disp; }},memacc_code = {{ }}, - mem_flags = [], inst_flags = []) {{ +def format StoreFloatMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, + mem_flags = [], inst_flags = []) {{ (header_output, decoder_output, decode_block, exec_output) = \ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - decode_template = LoadNopCheckDecode, exec_template_base = 'Store') }}; + +def format UnalignedStore(memacc_code, postacc_code, + ea_code = {{ EA = Rb + disp; }}, + mem_flags = [], inst_flags = []) {{ + (header_output, decoder_output, decode_block, exec_output) = \ + LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, + postacc_code, exec_template_base = 'Store') +}}; diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa index d35179005..2aa4816e3 100644 --- a/arch/mips/isa/formats/noop.isa +++ b/arch/mips/isa/formats/noop.isa @@ -88,3 +88,7 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{ exec_output = BasicExecute.subst(iop) }}; +def format Nop() {{ + decode_block = 'return new Nop(\"sll r0,r0,0\",machInst);\n' +}}; + diff --git a/arch/mips/isa/formats/unimp.isa b/arch/mips/isa/formats/unimp.isa index adbd5b5b1..475a88752 100644 --- a/arch/mips/isa/formats/unimp.isa +++ b/arch/mips/isa/formats/unimp.isa @@ -110,8 +110,9 @@ output exec {{ Trace::InstRecord *traceData) const { panic("attempt to execute unimplemented instruction '%s' " - "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE); - return UnimplementedOpcodeFault; + "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE, + inst2string(machInst)); + return new UnimplementedOpcodeFault; } Fault diff --git a/arch/mips/isa/formats/unknown.isa b/arch/mips/isa/formats/unknown.isa index 4601b3684..ba83c007e 100644 --- a/arch/mips/isa/formats/unknown.isa +++ b/arch/mips/isa/formats/unknown.isa @@ -26,12 +26,34 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +output header {{ + std::string inst2string(MachInst machInst); +}}; output decoder {{ + +std::string inst2string(MachInst machInst) +{ + string str = ""; + uint32_t mask = 0x80000000; + + for(int i=0; i < 32; i++) { + if ((machInst & mask) == 0) { + str += "0"; + } else { + str += "1"; + } + + mask = mask >> 1; + } + + return str; +} + std::string Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return csprintf("%-10s (inst 0x%x, opcode 0x%x)", - "unknown", machInst, OPCODE); + return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)", + "unknown", machInst, OPCODE, inst2string(machInst)); } }}; @@ -41,8 +63,8 @@ output exec {{ Trace::InstRecord *traceData) const { panic("attempt to execute unknown instruction " - "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE); - return UnimplementedOpcodeFault; + "(inst 0x%08x, opcode 0x%x, binary: %s)", machInst, OPCODE, inst2string(machInst)); + return new UnimplementedOpcodeFault; } }}; diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa index db4bf204a..615160931 100644 --- a/arch/mips/isa/formats/util.isa +++ b/arch/mips/isa/formats/util.isa @@ -93,8 +93,7 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, output exec {{ -using namespace MipsISA; - + using namespace MipsISA; /// CLEAR ALL CPU INST/EXE HAZARDS inline void @@ -124,25 +123,7 @@ using namespace MipsISA; } #endif - double convert_and_round(float w, int x, int y, int z) - { - double temp = .34000; - - return temp; - } - enum FPTypes{ - FP_SINGLE, - FP_DOUBLE, - FP_LONG, - FP_PS_LO, - FP_PS_HI, - FP_WORD, - RND_NEAREST, - RND_ZERO, - RND_UP, - RND_DOWN - }; }}; diff --git a/arch/mips/isa/includes.isa b/arch/mips/isa/includes.isa index da919be00..9c370fbe3 100644 --- a/arch/mips/isa/includes.isa +++ b/arch/mips/isa/includes.isa @@ -9,21 +9,28 @@ output header {{ #include <iomanip> #include "cpu/static_inst.hh" -#include "mem/mem_req.hh" // some constructors use MemReq flags +#include "arch/mips/isa_traits.hh" }}; output decoder {{ +#include "arch/mips/isa_traits.hh" #include "base/cprintf.hh" #include "base/loader/symtab.hh" #include "cpu/exec_context.hh" // for Jump::branchTarget() +#include "arch/mips/faults.hh" +#include "arch/mips/isa_traits.hh" #include <math.h> #if defined(linux) #include <fenv.h> #endif + +using namespace MipsISA; }}; output exec {{ +#include "arch/mips/faults.hh" +#include "arch/mips/isa_traits.hh" #include <math.h> #if defined(linux) #include <fenv.h> @@ -35,5 +42,7 @@ output exec {{ #include "cpu/base.hh" #include "cpu/exetrace.hh" #include "sim/sim_exit.hh" + +using namespace MipsISA; }}; diff --git a/arch/mips/isa/main.isa b/arch/mips/isa/main.isa index 411e398b4..01d81323e 100644 --- a/arch/mips/isa/main.isa +++ b/arch/mips/isa/main.isa @@ -26,7 +26,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -##include "m5/arch/mips/isa/includes.isa" +##include "includes.isa" //////////////////////////////////////////////////////////////////// // @@ -37,16 +37,16 @@ namespace MipsISA; //Include the bitfield definitions -##include "m5/arch/mips/isa/bitfields.isa" +##include "bitfields.isa" //Include the operand_types and operand definitions -##include "m5/arch/mips/isa/operands.isa" +##include "operands.isa" //Include the base class for mips instructions, and some support code -##include "m5/arch/mips/isa/base.isa" +##include "base.isa" //Include the definitions for the instruction formats -##include "m5/arch/mips/isa/formats.isa" +##include "formats/formats.isa" //Include the decoder definition -##include "m5/arch/mips/isa/decoder.isa" +##include "decoder.isa" diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa index 13870337b..0f9c74b48 100644 --- a/arch/mips/isa/operands.isa +++ b/arch/mips/isa/operands.isa @@ -13,21 +13,49 @@ def operand_types {{ }}; def operands {{ + #General Purpose Integer Reg Operands 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1), 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2), 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3), - 'r31': ('IntReg', 'uw','R31','IsInteger', 4), - 'R0': ('IntReg', 'uw','R0', 'IsInteger', 5), + #Operands used for Link or Syscall Insts + 'R31': ('IntReg', 'uw','31','IsInteger', 4), + 'R2': ('IntReg', 'uw','2', 'IsInteger', 5), + + #Special Integer Reg operands + 'HI': ('IntReg', 'uw','32', 'IsInteger', 6), + 'LO': ('IntReg', 'uw','33', 'IsInteger', 7), + + #Immediate Value operand 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3), + #Floating Point Reg Operands 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1), 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2), 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3), 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3), - 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), + #Special Floating Point Control Reg Operands + 'FIR': ('FloatReg', 'uw', '32', 'IsFloating', 1), + 'FCCR': ('FloatReg', 'uw', '33', 'IsFloating', 2), + 'FEXR': ('FloatReg', 'uw', '34', 'IsFloating', 3), + 'FENR': ('FloatReg', 'uw', '35', 'IsFloating', 3), + 'FCSR': ('FloatReg', 'uw', '36', 'IsFloating', 3), + + #Operands For Paired Singles FP Operations + 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4), + 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4), + 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5), + 'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5), + 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6), + 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6), + 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7), + 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7), + + #Memory Operand + 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), + #Program Counter Operands 'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4), 'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4) }}; diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc index d01fa6bd4..216a6e2ec 100644 --- a/arch/mips/isa_traits.cc +++ b/arch/mips/isa_traits.cc @@ -30,296 +30,109 @@ #include "config/full_system.hh" #include "cpu/static_inst.hh" #include "sim/serialize.hh" +#include "base/bitfield.hh" using namespace MipsISA; +using namespace std; -//Function now Obsolete in current state. -//If anyting this should return the correct miscreg index -//but that is handled implicitly with enums anyway void -MipsISA::getMiscRegIdx(int reg_name,int &idx, int &sel) +MipsISA::copyRegs(ExecContext *src, ExecContext *dest) { - switch(reg_name) - { - case Index: idx = 0; sel = 0; break; //0-0 Index into the TLB array - case MVPControl: idx = 0; sel = 1; break; //0-1 Per-processor register containing global - case MVPConf0: idx = 0; sel = 2; break; //0-2 Per-processor register containing global - case MVPConf1: idx = 0; sel = 3; break; //0-3 Per-processor register containing global - case Random: idx = 1; sel = 3; break; //1-0 Randomly generated index into the TLB array - case VPEControl: idx = 1; sel = 1; break; //1-1 Per-VPE register containing relatively volatile - //thread configuration data - case VPEConf0: idx = 1; sel = 2; break; //1-2 Per-VPE multi-thread configuration - //information - case VPEConf1: idx = 1; sel = 3; break; //1-3 Per-VPE multi-thread configuration - //information - case YQMask: idx = 1; sel = 4; break; //Per-VPE register defining which YIELD - //qualifier bits may be used without generating - //an exception - case VPESchedule: idx = 1; sel = 5; break; - case VPEScheFBack: idx = 1; sel = 6; break; - case VPEOpt: idx = 1; sel = 7; break; - case EntryLo0: idx = 1; sel = 5; break; - case TCStatus: idx = 1; sel = 5; break; - case TCBind: idx = 1; sel = 5; break; - case TCRestart: idx = 1; sel = 5; break; - case TCHalt: idx = 1; sel = 5; break; - case TCContext: idx = 1; sel = 5; break; - case TCSchedule: idx = 1; sel = 5; break; - case TCScheFBack: panic("Accessing Unimplemented CP0 Register"); break; - case EntryLo1: panic("Accessing Unimplemented CP0 Register"); break; - case Context: panic("Accessing Unimplemented CP0 Register"); break; - case ContextConfig: panic("Accessing Unimplemented CP0 Register"); break; - //case PageMask: panic("Accessing Unimplemented CP0 Register"); break; - case PageGrain: panic("Accessing Unimplemented CP0 Register"); break; - case Wired: panic("Accessing Unimplemented CP0 Register"); break; - case SRSConf0: panic("Accessing Unimplemented CP0 Register"); break; - case SRSConf1: panic("Accessing Unimplemented CP0 Register"); break; - case SRSConf2: panic("Accessing Unimplemented CP0 Register"); break; - case SRSConf3: panic("Accessing Unimplemented CP0 Register"); break; - case SRSConf4: panic("Accessing Unimplemented CP0 Register"); break; - case BadVAddr: panic("Accessing Unimplemented CP0 Register"); break; - case Count: panic("Accessing Unimplemented CP0 Register"); break; - case EntryHi: panic("Accessing Unimplemented CP0 Register"); break; - case Compare: panic("Accessing Unimplemented CP0 Register"); break; - case Status: idx = 12; sel = 0; break; //12-0 Processor status and control - case IntCtl: idx = 12; sel = 1; break; //12-1 Interrupt system status and control - case SRSCtl: idx = 12; sel = 2; break; //12-2 Shadow register set status and control - case SRSMap: idx = 12; sel = 3; break; //12-3 Shadow set IPL mapping - case Cause: idx = 13; sel = 0; break; //13-0 Cause of last general exception - case EPC: idx = 14; sel = 0; break; //14-0 Program counter at last exception - case PrId: idx = 15; sel = 0; break; //15-0 Processor identification and revision - case EBase: idx = 15; sel = 1; break; //15-1 Exception vector base register - case Config: panic("Accessing Unimplemented CP0 Register"); break; - case Config1: panic("Accessing Unimplemented CP0 Register"); break; - case Config2: panic("Accessing Unimplemented CP0 Register"); break; - case Config3: panic("Accessing Unimplemented CP0 Register"); break; - case LLAddr: panic("Accessing Unimplemented CP0 Register"); break; - case WatchLo: panic("Accessing Unimplemented CP0 Register"); break; - case WatchHi: panic("Accessing Unimplemented CP0 Register"); break; - case Debug: panic("Accessing Unimplemented CP0 Register"); break; - case TraceControl1: panic("Accessing Unimplemented CP0 Register"); break; - case TraceControl2: panic("Accessing Unimplemented CP0 Register"); break; - case UserTraceData: panic("Accessing Unimplemented CP0 Register"); break; - case TraceBPC: panic("Accessing Unimplemented CP0 Register"); break; - case DEPC: panic("Accessing Unimplemented CP0 Register"); break; - case PerfCnt: panic("Accessing Unimplemented CP0 Register"); break; - case ErrCtl: panic("Accessing Unimplemented CP0 Register"); break; - case CacheErr0: panic("Accessing Unimplemented CP0 Register"); break; - case CacheErr1: panic("Accessing Unimplemented CP0 Register"); break; - case CacheErr2: panic("Accessing Unimplemented CP0 Register"); break; - case CacheErr3: panic("Accessing Unimplemented CP0 Register"); break; - case TagLo: panic("Accessing Unimplemented CP0 Register"); break; - case DataLo: panic("Accessing Unimplemented CP0 Register"); break; - case TagHi: panic("Accessing Unimplemented CP0 Register"); break; - case DataHi: panic("Accessing Unimplemented CP0 Register"); break; - case ErrorEPC: panic("Accessing Unimplemented CP0 Register"); break; + /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag); + uniq = xc->readMiscReg(MipsISA::Uniq_DepTag); + lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag); + lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag); - default: - panic("Accessing Unimplemented Misc. Register"); - } +#if FULL_SYSTEM + copyIprs(xc); + #endif*/ } -void RegFile::coldReset() +void +MipsISA::MiscRegFile::copyMiscRegs(ExecContext *xc) { - //CP0 Random Reg: - //Randomly generated index into the TLB array - miscRegs[Random] = 0x0000003f; - - //CP0 Wired Reg. - miscRegs[Wired] = 0x0000000; - - //CP0 HWRENA - miscRegs[HWRena] = 0x0000000; - - //CP0 Status Reg. - miscRegs[Status] = 0x0400004; - - //CP0 INTCNTL - miscRegs[IntCtl] = 0xfc00000; - - //CP0 SRSCNTL - miscRegs[SRSCtl] = 0x0c00000; - - //CP0 SRSMAP - miscRegs[SRSMap] = 0x0000000; - - //CP0 Cause - miscRegs[Cause] = 0x0000000; - - //CP0 Processor ID - miscRegs[PrId] = 0x0019300; - - //CP0 EBASE - miscRegs[EBase] = 0x8000000; - - //CP0 Config Reg. - miscRegs[Config] = 0x80040482; - - //CP0 Config 1 Reg. - miscRegs[Config1] = 0xfee3719e; - - //CP0 Config 2 Reg. - miscRegs[Config2] = 0x8000000; - - //CP0 Config 3 Reg. - miscRegs[Config3] = 0x0000020; - - //CP0 Config 7 Reg. - miscRegs[Config7] = 0x0000000; - - //CP0 Debug - miscRegs[Debug] = 0x0201800; - - //CP0 PERFCNTL1 - miscRegs[PerfCnt0] = 0x0000000; - - //CP0 PERFCNTL2 - miscRegs[PerfCnt1] = 0x0000000; + /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag); + uniq = xc->readMiscReg(MipsISA::Uniq_DepTag); + lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag); + lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag); + #endif*/ } -void RegFile::createCP0Regs() +uint64_t +MipsISA::fpConvert(double fp_val, ConvertType cvt_type) { -//Resize Coprocessor Register Banks to -// the number specified in MIPS32K VOL.III -// Chapter 8 - /* - //Cop-0 Regs. Bank 0: Index, - miscRegs[0].resize(4); - - //Cop-0 Regs. Bank 1: - miscRegs[1].resize(8); - - //Cop-0 Regs. Bank 2: - miscRegs[2].resize(8); - - //Cop-0 Regs. Bank 3: - miscRegs[3].resize(1); - - //Cop-0 Regs. Bank 4: - miscRegs[4].resize(2); - - //Cop-0 Regs. Bank 5: - miscRegs[5].resize(2); - - //Cop-0 Regs. Bank 6: - miscRegs[6].resize(6); - - //Cop-0 Regs. Bank 7: - miscRegs[7].resize(1); - - //Cop-0 Regs. Bank 8: - miscRegs[8].resize(1); - - //Cop-0 Regs. Bank 9: - miscRegs[9].resize(1); - - //Cop-0 Regs. Bank 10: - miscRegs[10].resize(1); - - //Cop-0 Regs. Bank 11: - miscRegs[11].resize(1); - - //Cop-0 Regs. Bank 12: - miscRegs[12].resize(4); - - //Cop-0 Regs. Bank 13: - miscRegs[13].resize(1); - - //Cop-0 Regs. Bank 14: - miscRegs[14].resize(1); - - //Cop-0 Regs. Bank 15: - miscRegs[15].resize(2); - - //Cop-0 Regs. Bank 16: - miscRegs[16].resize(4); - //Cop-0 Regs. Bank 17: - miscRegs[17].resize(1); - - //Cop-0 Regs. Bank 18: - miscRegs[18].resize(8); - - //Cop-0 Regs. Bank 19: - miscRegs[19].resize(8); - - //Cop-0 Regs. Bank 20: - miscRegs[20].resize(1); - - //Cop-0 Regs. Bank 21: - //miscRegs[21].resize(1); - //Reserved for future extensions - - //Cop-0 Regs. Bank 22: - //miscRegs[22].resize(4); - //Available for implementation dependent use - - //Cop-0 Regs. Bank 23: - miscRegs[23].resize(5); - - //Cop-0 Regs. Bank 24: - miscRegs[24].resize(1); - - //Cop-0 Regs. Bank 25: - miscRegs[25].resize(8); + switch (cvt_type) + { + case SINGLE_TO_DOUBLE: + double sdouble_val = fp_val; + void *sdouble_ptr = &sdouble_val; + uint64_t sdp_bits = *(uint64_t *) sdouble_ptr; + return sdp_bits; + + case SINGLE_TO_WORD: + int32_t sword_val = (int32_t) fp_val; + void *sword_ptr = &sword_val; + uint64_t sword_bits= *(uint32_t *) sword_ptr; + return sword_bits; + + case WORD_TO_SINGLE: + float wfloat_val = fp_val; + void *wfloat_ptr = &wfloat_val; + uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr; + return wfloat_bits; + + case WORD_TO_DOUBLE: + double wdouble_val = fp_val; + void *wdouble_ptr = &wdouble_val; + uint64_t wdp_bits = *(uint64_t *) wdouble_ptr; + return wdp_bits; - //Cop-0 Regs. Bank 26: - miscRegs[26].resize(1); + default: + panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type); + return 0; + } +} - //Cop-0 Regs. Bank 27: - miscRegs[27].resize(4); +double +MipsISA::roundFP(double val, int digits) +{ + double digit_offset = pow(10.0,digits); + val = val * digit_offset; + val = val + 0.5; + val = floor(val); + val = val / digit_offset; + return val; +} - //Cop-0 Regs. Bank 28: - miscRegs[28].resize(8); +double +MipsISA::truncFP(double val) +{ + int trunc_val = (int) val; + return (double) trunc_val; +} - //Cop-0 Regs. Bank 29: - miscRegs[29].resize(8); +bool +MipsISA::getFPConditionCode(uint32_t fcsr_reg, int cc) +{ + //uint32_t cc_bits = xc->readFloatReg(35); + return false;//regFile.floatRegfile.getConditionCode(cc); +} - //Cop-0 Regs. Bank 30: - miscRegs[30].resize(1); +uint32_t +MipsISA::makeCCVector(uint32_t fcsr, int num, bool val) +{ + int shift = (num == 0) ? 22 : num + 23; - //Cop-0 Regs. Bank 31: - miscRegs[31].resize(1);*/ + fcsr = fcsr | (val << shift); + return fcsr; } - -const Addr MipsISA::PageShift = 13; -const Addr MipsISA::PageBytes = ULL(1) << PageShift; -const Addr MipsISA::PageMask = ~(PageBytes - 1); -const Addr MipsISA::PageOffset = PageBytes - 1; - #if FULL_SYSTEM -//////////////////////////////////////////////////////////////////////// -// -// Translation stuff -// - -const Addr MipsISA::PteShift = 3; -const Addr MipsISA::NPtePageShift = PageShift - PteShift; -const Addr MipsISA::NPtePage = ULL(1) << NPtePageShift; -const Addr MipsISA::PteMask = NPtePage - 1; - -// User Virtual -const Addr MipsISA::USegBase = ULL(0x0); -const Addr MipsISA::USegEnd = ULL(0x000003ffffffffff); - -// Kernel Direct Mapped -const Addr MipsISA::K0SegBase = ULL(0xfffffc0000000000); -const Addr MipsISA::K0SegEnd = ULL(0xfffffdffffffffff); - -// Kernel Virtual -const Addr MipsISA::K1SegBase = ULL(0xfffffe0000000000); -const Addr MipsISA::K1SegEnd = ULL(0xffffffffffffffff); - -#endif - -// Mips UNOP (sll r0,r0,r0) -const MachInst MipsISA::NoopMachInst = 0x00000000; - static inline Addr TruncPage(Addr addr) { return addr & ~(MipsISA::PageBytes - 1); } @@ -327,12 +140,25 @@ TruncPage(Addr addr) static inline Addr RoundPage(Addr addr) { return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); } +#endif + +void +IntRegFile::serialize(std::ostream &os) +{ + SERIALIZE_ARRAY(regs, NumIntRegs); +} + +void +IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) +{ + UNSERIALIZE_ARRAY(regs, NumIntRegs); +} void RegFile::serialize(std::ostream &os) { - SERIALIZE_ARRAY(intRegFile, NumIntRegs); - SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs); + intRegFile.serialize(os); + //SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs); //SERIALIZE_SCALAR(miscRegs.fpcr); //SERIALIZE_SCALAR(miscRegs.uniq); //SERIALIZE_SCALAR(miscRegs.lock_flag); @@ -352,8 +178,8 @@ RegFile::serialize(std::ostream &os) void RegFile::unserialize(Checkpoint *cp, const std::string §ion) { - UNSERIALIZE_ARRAY(intRegFile, NumIntRegs); - UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs); + intRegFile.unserialize(cp, section); + //UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs); //UNSERIALIZE_SCALAR(miscRegs.fpcr); //UNSERIALIZE_SCALAR(miscRegs.uniq); //UNSERIALIZE_SCALAR(miscRegs.lock_flag); diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh index 1dfa0dc7a..148c405df 100644 --- a/arch/mips/isa_traits.hh +++ b/arch/mips/isa_traits.hh @@ -29,9 +29,14 @@ #ifndef __ARCH_MIPS_ISA_TRAITS_HH__ #define __ARCH_MIPS_ISA_TRAITS_HH__ -//#include "arch/mips/misc_regfile.hh" +#include "arch/mips/constants.hh" +#include "arch/mips/types.hh" +#include "arch/mips/regfile/regfile.hh" +#include "arch/mips/faults.hh" +#include "arch/mips/utility.hh" #include "base/misc.hh" #include "config/full_system.hh" +#include "sim/byteswap.hh" #include "sim/host.hh" #include "sim/faults.hh" @@ -40,9 +45,9 @@ class FastCPU; class FullCPU; class Checkpoint; +class ExecContext; namespace LittleEndianGuest {}; -using namespace LittleEndianGuest; #define TARGET_MIPS @@ -54,396 +59,107 @@ int DTB_ASN_ASN(uint64_t reg); int ITB_ASN_ASN(uint64_t reg); }; -namespace MipsISA -{ - typedef uint32_t MachInst; -// typedef uint64_t Addr; - typedef uint8_t RegIndex; - - enum { - MemoryEnd = 0xffffffffffffffffULL, - - NumIntRegs = 32, - NumFloatRegs = 32, - NumMiscRegs = 258, //account for hi,lo regs - - MaxRegsOfAnyType = 32, - // Static instruction parameters - MaxInstSrcRegs = 3, - MaxInstDestRegs = 2, - - // semantically meaningful register indices - ZeroReg = 0, // architecturally meaningful - // the rest of these depend on the ABI - StackPointerReg = 30, - GlobalPointerReg = 29, - ProcedureValueReg = 27, - ReturnAddressReg = 26, - ReturnValueReg = 0, - FramePointerReg = 15, - ArgumentReg0 = 16, - ArgumentReg1 = 17, - ArgumentReg2 = 18, - ArgumentReg3 = 19, - ArgumentReg4 = 20, - ArgumentReg5 = 21, - - LogVMPageSize = 13, // 8K bytes - VMPageSize = (1 << LogVMPageSize), - - BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned - - WordBytes = 4, - HalfwordBytes = 2, - ByteBytes = 1, - DepNA = 0, - }; - - // These enumerate all the registers for dependence tracking. - enum DependenceTags { - // 0..31 are the integer regs 0..31 - // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) - FP_Base_DepTag = 32, - Ctrl_Base_DepTag = 64, - Fpcr_DepTag = 64, // floating point control register - Uniq_DepTag = 65, - IPR_Base_DepTag = 66, - MiscReg_DepTag = 67 - }; - - typedef uint64_t IntReg; - typedef IntReg IntRegFile[NumIntRegs]; - - // floating point register file entry type - typedef union { - uint64_t q; - double d; - } FloatReg; - - typedef union { - uint64_t q[NumFloatRegs]; // integer qword view - double d[NumFloatRegs]; // double-precision floating point view - } FloatRegFile; - - // cop-0/cop-1 system control register file - typedef uint64_t MiscReg; -//typedef MiscReg MiscRegFile[NumMiscRegs]; - class MiscRegFile { - public: - MiscReg - protected: - uint64_t fpcr; // floating point condition codes - uint64_t uniq; // process-unique register - bool lock_flag; // lock flag for LL/SC - Addr lock_addr; // lock address for LL/SC - - MiscReg miscRegFile[NumMiscRegs]; - - public: - //These functions should be removed once the simplescalar cpu model - //has been replaced. - int getInstAsid(); - int getDataAsid(); - - MiscReg readReg(int misc_reg) - { return miscRegFile[misc_reg]; } - - MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc) - { return miscRegFile[misc_reg];} - - Fault setReg(int misc_reg, const MiscReg &val) - { miscRegFile[misc_reg] = val; return NoFault; } - - Fault setRegWithEffect(int misc_reg, const MiscReg &val, - ExecContext *xc) - { miscRegFile[misc_reg] = val; return NoFault; } - -#if FULL_SYSTEM - void clearIprs() { }; - - protected: - InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs - - private: - MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { } - - Fault setIpr(int idx, uint64_t val, ExecContext *xc) { } -#endif - friend class RegFile; - }; - - enum MiscRegTags { - //Coprocessor 0 Registers - //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 - //(Register Number-Register Select) Summary of Register - //------------------------------------------------------ - Index = 0, //0-0 Index into the TLB array - - MVPControl = 1, //0-1 Per-processor register containing global - //MIPS® MT configuration data - - MVPConf0 = 2, //0-2 Per-processor register containing global - //MIPS® MT configuration data - - MVPConf1 = 3, //0-3 Per-processor register containing global - //MIPS® MT configuration data - - Random = 8, //1-0 Randomly generated index into the TLB array - - VPEControl = 9, //1-1 Per-VPE register containing relatively volatile - //thread configuration data - - VPEConf0 = 10, //1-2 Per-VPE multi-thread configuration - //information - - - VPEConf1 = 11, //1-2 Per-VPE multi-thread configuration - //information - - YQMask = 12, //Per-VPE register defining which YIELD - //qualifier bits may be used without generating - //an exception - - VPESchedule = 13, - VPEScheFBack = 14, - VPEOpt = 15, - EntryLo0 = 16, // Bank 3: 16 - 23 - TCStatus = 17, - TCBind = 18, - TCRestart = 19, - TCHalt = 20, - TCContext = 21, - TCSchedule = 22, - TCScheFBack = 23, - - EntryLo1 = 24,// Bank 4: 24 - 31 - - Context = 32, // Bank 5: 32 - 39 - ContextConfig = 33, - - //PageMask = 40, //Bank 6: 40 - 47 - PageGrain = 41, - - Wired = 48, //Bank 7:48 - 55 - SRSConf0 = 49, - SRSConf1 = 50, - SRSConf2 = 51, - SRSConf3 = 52, - SRSConf4 = 53, - BadVAddr = 54, - - HWRena = 56,//Bank 8:56 - 63 - - Count = 64, //Bank 9:64 - 71 - - EntryHi = 72,//Bank 10:72 - 79 - - Compare = 80,//Bank 11:80 - 87 - - Status = 88,//Bank 12:88 - 96 //12-0 Processor status and control - IntCtl = 89, //12-1 Interrupt system status and control - SRSCtl = 90, //12-2 Shadow register set status and control - SRSMap = 91, //12-3 Shadow set IPL mapping - - Cause = 97,//97-104 //13-0 Cause of last general exception - - EPC = 105,//105-112 //14-0 Program counter at last exception - - PRId = 113//113-120, //15-0 Processor identification and revision - EBase = 114, //15-1 Exception vector base register - - Config = 121,//Bank 16: 121-128 - Config1 = 122, - Config2 = 123, - Config3 = 124, - Config6 = 127, - Config7 = 128, - - - LLAddr = 129,//Bank 17: 129-136 - - WatchLo0 = 137,//Bank 18: 137-144 - WatchLo1 = 138, - WatchLo2 = 139, - WatchLo3 = 140, - WatchLo4 = 141, - WatchLo5 = 142, - WatchLo6 = 143, - WatchLo7 = 144, +#if !FULL_SYSTEM +class SyscallReturn { + public: + template <class T> + SyscallReturn(T v, bool s) + { + retval = (uint32_t)v; + success = s; + } - WatchHi0 = 145,//Bank 19: 145-152 - WatchHi1 = 146, - WatchHi2 = 147, - WatchHi3 = 148, - WatchHi4 = 149, - WatchHi5 = 150, - WatchHi6 = 151, - WatchHi7 = 152, + template <class T> + SyscallReturn(T v) + { + success = (v >= 0); + retval = (uint32_t)v; + } - XCContext64 = 153,//Bank 20: 153-160 + ~SyscallReturn() {} - //Bank 21: 161-168 + SyscallReturn& operator=(const SyscallReturn& s) { + retval = s.retval; + success = s.success; + return *this; + } - //Bank 22: 169-176 - - Debug = 177, //Bank 23: 177-184 - TraceControl1 = 178, - TraceControl2 = 179, - UserTraceData = 180, - TraceBPC = 181, - - DEPC = 185,//Bank 24: 185-192 - - PerfCnt0 = 193,//Bank 25: 193 - 200 - PerfCnt1 = 194, - PerfCnt2 = 195, - PerfCnt3 = 196, - PerfCnt4 = 197, - PerfCnt5 = 198, - PerfCnt6 = 199, - PerfCnt7 = 200, - - ErrCtl = 201, //Bank 26: 201 - 208 - - CacheErr0 = 209, //Bank 27: 209 - 216 - CacheErr1 = 210, - CacheErr2 = 211, - CacheErr3 = 212, - - TagLo0 = 217,//Bank 28: 217 - 224 - DataLo1 = 218, - TagLo2 = 219, - DataLo3 = 220, - TagLo4 = 221, - DataLo5 = 222, - TagLo6 = 223, - DataLo7 = 234, - - TagHi0 = 233,//Bank 29: 233 - 240 - DataHi1 = 234, - TagHi2 = 235, - DataHi3 = 236, - TagHi4 = 237, - DataHi5 = 238, - TagHi6 = 239, - DataHi7 = 240, + bool successful() { return success; } + uint64_t value() { return retval; } - ErrorEPC = 249,//Bank 30: 241 - 248 + private: + uint64_t retval; + bool success; +}; +#endif - DESAVE = 257,//Bank 31: 249-256 +namespace MipsISA +{ + using namespace LittleEndianGuest; + + static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) + { + if (return_value.successful()) { + // no error + regs->setIntReg(SyscallSuccessReg, 0); + regs->setIntReg(ReturnValueReg1, return_value.value()); + } else { + // got an error, return details + regs->setIntReg(SyscallSuccessReg, (IntReg) -1); + regs->setIntReg(ReturnValueReg1, -return_value.value()); + } + } - //More Misc. Regs - Hi, - Lo, - FCSR, - FPCR, - - //Alpha Regs, but here now, for - //compiling sake - UNIQ, - LockAddr, - LockFlag - }; - -extern const Addr PageShift; -extern const Addr PageBytes; -extern const Addr PageMask; -extern const Addr PageOffset; + StaticInstPtr decodeInst(ExtMachInst); + static inline ExtMachInst + makeExtMI(MachInst inst, const uint64_t &pc) { #if FULL_SYSTEM - - typedef uint64_t InternalProcReg; - -#include "arch/mips/isa_fullsys_traits.hh" - + ExtMachInst ext_inst = inst; + if (pc && 0x1) + return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); + else + return ext_inst; #else - enum { - NumInternalProcRegs = 0 - }; + return ExtMachInst(inst); #endif + } - enum { - TotalNumRegs = - NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs - }; - - enum { - TotalDataRegs = NumIntRegs + NumFloatRegs - }; - - typedef union { - IntReg intreg; - FloatReg fpreg; - MiscReg ctrlreg; - } AnyReg; - - struct RegFile { - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegs; // control register file - - - Addr pc; // program counter - Addr npc; // next-cycle program counter - Addr nnpc; // next-next-cycle program counter - // used to implement branch delay slot - // not real register - - MiscReg hi; // MIPS HI Register - MiscReg lo; // MIPS LO Register - - -#if FULL_SYSTEM - IntReg palregs[NumIntRegs]; // PAL shadow registers - InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs - int intrflag; // interrupt flag - bool pal_shadow; // using pal_shadow registers - inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } - inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } -#endif // FULL_SYSTEM - - //void initCP0Regs(); - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - - void createCP0Regs(); - void coldReset(); - }; - - StaticInstPtr decodeInst(MachInst); + /** + * Function to insure ISA semantics about 0 registers. + * @param xc The execution context. + */ + template <class XC> + void zeroRegisters(XC *xc); - // return a no-op instruction... used for instruction fetch faults - extern const MachInst NoopMachInst; + const Addr MaxAddr = (Addr)-1; - enum annotes { - ANNOTE_NONE = 0, - // An impossible number for instruction annotations - ITOUCH_ANNOTE = 0xffffffff, - }; + void copyRegs(ExecContext *src, ExecContext *dest); - void getMiscRegIdx(int reg_name,int &idx, int &sel); + uint64_t fpConvert(double fp_val, ConvertType cvt_type); + double roundFP(double val, int digits); + double truncFP(double val); + bool getFPConditionCode(uint32_t fcsr_reg, int cc); + uint32_t makeCCVector(uint32_t fcsr, int num, bool val); + // Machine operations - static inline bool isCallerSaveIntegerRegister(unsigned int reg) { - panic("register classification not implemented"); - return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); - } + void saveMachineReg(AnyReg &savereg, const RegFile ®_file, + int regnum); - static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { - panic("register classification not implemented"); - return (reg >= 9 && reg <= 15); - } + void restoreMachineReg(RegFile ®s, const AnyReg ®, + int regnum); - static inline bool isCallerSaveFloatRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } +#if 0 + static void serializeSpecialRegs(const Serializable::Proxy &proxy, + const RegFile ®s); - static inline bool isCalleeSaveFloatRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } + static void unserializeSpecialRegs(const IniFile *db, + const std::string &category, + ConfigNode *node, + RegFile ®s); +#endif static inline Addr alignAddress(const Addr &addr, unsigned int nbytes) { @@ -470,77 +186,14 @@ extern const Addr PageOffset; return 0; } - // Machine operations - - void saveMachineReg(AnyReg &savereg, const RegFile ®_file, - int regnum); - - void restoreMachineReg(RegFile ®s, const AnyReg ®, - int regnum); - -#if 0 - static void serializeSpecialRegs(const Serializable::Proxy &proxy, - const RegFile ®s); - - static void unserializeSpecialRegs(const IniFile *db, - const std::string &category, - ConfigNode *node, - RegFile ®s); -#endif - - /** - * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. - */ - template <class XC> - void zeroRegisters(XC *xc); - - const Addr MaxAddr = (Addr)-1; }; -#if !FULL_SYSTEM -class SyscallReturn { - public: - template <class T> - SyscallReturn(T v, bool s) - { - retval = (uint64_t)v; - success = s; - } - - template <class T> - SyscallReturn(T v) - { - success = (v >= 0); - retval = (uint64_t)v; - } - - ~SyscallReturn() {} - - SyscallReturn& operator=(const SyscallReturn& s) { - retval = s.retval; - success = s.success; - return *this; - } - - bool successful() { return success; } - uint64_t value() { return retval; } - - - private: - uint64_t retval; - bool success; -}; - -#endif - - #if FULL_SYSTEM -//typedef TheISA::InternalProcReg InternalProcReg; -//const int NumInternalProcRegs = TheISA::NumInternalProcRegs; -//const int NumInterruptLevels = TheISA::NumInterruptLevels; #include "arch/mips/mips34k.hh" + #endif +using namespace MipsISA; + #endif // __ARCH_MIPS_ISA_TRAITS_HH__ diff --git a/arch/mips/linux/linux.cc b/arch/mips/linux/linux.cc new file mode 100644 index 000000000..ebff886dd --- /dev/null +++ b/arch/mips/linux/linux.cc @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/mips/linux/linux.hh" + +// open(2) flags translation table +OpenFlagTransTable MipsLinux::openFlagTable[] = { +#ifdef _MSC_VER + { MipsLinux::TGT_O_RDONLY, _O_RDONLY }, + { MipsLinux::TGT_O_WRONLY, _O_WRONLY }, + { MipsLinux::TGT_O_RDWR, _O_RDWR }, + { MipsLinux::TGT_O_APPEND, _O_APPEND }, + { MipsLinux::TGT_O_CREAT, _O_CREAT }, + { MipsLinux::TGT_O_TRUNC, _O_TRUNC }, + { MipsLinux::TGT_O_EXCL, _O_EXCL }, +#ifdef _O_NONBLOCK + { MipsLinux::TGT_O_NONBLOCK, _O_NONBLOCK }, +#endif +#ifdef _O_NOCTTY + { MipsLinux::TGT_O_NOCTTY, _O_NOCTTY }, +#endif +#ifdef _O_SYNC + { MipsLinux::TGT_O_SYNC, _O_SYNC }, +#endif +#else /* !_MSC_VER */ + { MipsLinux::TGT_O_RDONLY, O_RDONLY }, + { MipsLinux::TGT_O_WRONLY, O_WRONLY }, + { MipsLinux::TGT_O_RDWR, O_RDWR }, + { MipsLinux::TGT_O_APPEND, O_APPEND }, + { MipsLinux::TGT_O_CREAT, O_CREAT }, + { MipsLinux::TGT_O_TRUNC, O_TRUNC }, + { MipsLinux::TGT_O_EXCL, O_EXCL }, + { MipsLinux::TGT_O_NONBLOCK, O_NONBLOCK }, + { MipsLinux::TGT_O_NOCTTY, O_NOCTTY }, +#ifdef O_SYNC + { MipsLinux::TGT_O_SYNC, O_SYNC }, +#endif +#endif /* _MSC_VER */ +}; + +const int MipsLinux::NUM_OPEN_FLAGS = + (sizeof(MipsLinux::openFlagTable)/sizeof(MipsLinux::openFlagTable[0])); + + + diff --git a/arch/mips/linux/linux.hh b/arch/mips/linux/linux.hh new file mode 100644 index 000000000..fd08e8c87 --- /dev/null +++ b/arch/mips/linux/linux.hh @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MIPS_MIPS_LINUX_HH +#define __MIPS_MIPS_LINUX_HH + +#include "kern/linux/linux.hh" + +class MipsLinux : public Linux +{ + public: + + /// This table maps the target open() flags to the corresponding + /// host open() flags. + static OpenFlagTransTable openFlagTable[]; + + /// Number of entries in openFlagTable[]. + static const int NUM_OPEN_FLAGS; + + //@{ + /// open(2) flag values. + static const int TGT_O_RDONLY = 0x00000000; //!< O_RDONLY + static const int TGT_O_WRONLY = 0x00000001; //!< O_WRONLY + static const int TGT_O_RDWR = 0x00000002; //!< O_RDWR + static const int TGT_O_NONBLOCK = 0x00000080; //!< O_NONBLOCK + static const int TGT_O_APPEND = 0x00000008; //!< O_APPEND + static const int TGT_O_CREAT = 0x00000100; //!< O_CREAT + static const int TGT_O_TRUNC = 0x00000200; //!< O_TRUNC + static const int TGT_O_EXCL = 0x00000400; //!< O_EXCL + static const int TGT_O_NOCTTY = 0x00000800; //!< O_NOCTTY + static const int TGT_O_SYNC = 0x00000010; //!< O_SYNC + static const int TGT_O_DRD = 0x00010000; //!< O_DRD + static const int TGT_O_DIRECTIO = 0x00020000; //!< O_DIRECTIO + static const int TGT_O_CACHE = 0x00002000; //!< O_CACHE + static const int TGT_O_DSYNC = 0x00008000; //!< O_DSYNC + static const int TGT_O_RSYNC = 0x00040000; //!< O_RSYNC + //@} + + /// For mmap(). + static const unsigned TGT_MAP_ANONYMOUS = 0x800; + + //@{ + /// For getsysinfo(). + static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name as string + static const unsigned GSI_CPU_INFO = 59; //!< CPU information + static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type + static const unsigned GSI_MAX_CPU = 30; //!< max # cpu's on this machine + static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system + static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB + static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz + //@} + + //@{ + /// For getrusage(). + static const int TGT_RUSAGE_SELF = 0; + static const int TGT_RUSAGE_CHILDREN = -1; + static const int TGT_RUSAGE_BOTH = -2; + //@} + + //@{ + /// For setsysinfo(). + static const unsigned SSI_IEEE_FP_CONTROL = 14; //!< ieee_set_fp_control() + //@} + + //@{ + /// ioctl() command codes. + static const unsigned TIOCGETP = 0x7408; + static const unsigned TIOCSETP = 0x7409; + static const unsigned TIOCSETN = 0x740a; + static const unsigned TIOCSETC = 0x7411; + static const unsigned TIOCGETC = 0x7412; + static const unsigned FIONREAD = 0x467f; + static const unsigned TIOCISATTY = 0x5480; + static const unsigned TIOCGETS = 0x7413; + static const unsigned TIOCGETA = 0x7417; + //@} + + /// For table(). + static const int TBL_SYSINFO = 12; + + /// Resource enumeration for getrlimit(). + enum rlimit_resources { + TGT_RLIMIT_CPU = 0, + TGT_RLIMIT_FSIZE = 1, + TGT_RLIMIT_DATA = 2, + TGT_RLIMIT_STACK = 3, + TGT_RLIMIT_CORE = 4, + TGT_RLIMIT_NOFILE = 5, + TGT_RLIMIT_AS = 6, + TGT_RLIMIT_RSS = 7, + TGT_RLIMIT_VMEM = 7, + TGT_RLIMIT_NPROC = 8, + TGT_RLIMIT_MEMLOCK = 9, + TGT_RLIMIT_LOCKS = 10 + }; + +}; + +#endif diff --git a/arch/mips/linux/process.cc b/arch/mips/linux/process.cc new file mode 100644 index 000000000..ffc5da2e1 --- /dev/null +++ b/arch/mips/linux/process.cc @@ -0,0 +1,429 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/mips/linux/linux.hh" +#include "arch/mips/linux/process.hh" +#include "arch/mips/isa_traits.hh" + +#include "base/trace.hh" +#include "cpu/exec_context.hh" +#include "kern/linux/linux.hh" + +#include "sim/process.hh" +#include "sim/syscall_emul.hh" + +using namespace std; +using namespace MipsISA; + +/// Target uname() handler. +static SyscallReturn +unameFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0)); + + strcpy(name->sysname, "Linux"); + strcpy(name->nodename, "m5.eecs.umich.edu"); + strcpy(name->release, "2.4.20"); + strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); + strcpy(name->machine, "mips"); + + name.copyOut(xc->getMemPort()); + return 0; +} + +/// Target sys_getsysyinfo() handler. Even though this call is +/// borrowed from Tru64, the subcases that get used appear to be +/// different in practice from those used by Tru64 processes. +static SyscallReturn +sys_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + unsigned op = xc->getSyscallArg(0); + // unsigned nbytes = xc->getSyscallArg(2); + + switch (op) { + + case 45: { // GSI_IEEE_FP_CONTROL + TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + // I don't think this exactly matches the HW FPCR + *fpcr = 0; + fpcr.copyOut(xc->getMemPort()); + return 0; + } + + default: + cerr << "sys_getsysinfo: unknown op " << op << endl; + abort(); + break; + } + + return 1; +} + +/// Target sys_setsysinfo() handler. +static SyscallReturn +sys_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + unsigned op = xc->getSyscallArg(0); + // unsigned nbytes = xc->getSyscallArg(2); + + switch (op) { + + case 14: { // SSI_IEEE_FP_CONTROL + TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + // I don't think this exactly matches the HW FPCR + fpcr.copyIn(xc->getMemPort()); + DPRINTFR(SyscallVerbose, "sys_setsysinfo(SSI_IEEE_FP_CONTROL): " + " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr)); + return 0; + } + + default: + cerr << "sys_setsysinfo: unknown op " << op << endl; + abort(); + break; + } + + return 1; +} + + +SyscallDesc MipsLinuxProcess::syscallDescs[] = { + /* 0 */ SyscallDesc("syscall", unimplementedFunc), + /* 1 */ SyscallDesc("exit", exitFunc), + /* 2 */ SyscallDesc("fork", unimplementedFunc), + /* 3 */ SyscallDesc("read", readFunc), + /* 4 */ SyscallDesc("write", writeFunc), + /* 5 */ SyscallDesc("open", openFunc<MipsLinux>), + /* 6 */ SyscallDesc("close", closeFunc), + /* 7 */ SyscallDesc("waitpid", unimplementedFunc), + /* 8 */ SyscallDesc("creat", unimplementedFunc), + /* 9 */ SyscallDesc("link", unimplementedFunc), + /* 10 */ SyscallDesc("unlink", unlinkFunc), + /* 11 */ SyscallDesc("execve", unimplementedFunc), + /* 12 */ SyscallDesc("chdir", unimplementedFunc), + /* 13 */ SyscallDesc("time", unimplementedFunc), + /* 14 */ SyscallDesc("mknod", unimplementedFunc), + /* 15 */ SyscallDesc("chmod", chmodFunc<MipsLinux>), + /* 16 */ SyscallDesc("lchown", chownFunc), + /* 17 */ SyscallDesc("break", obreakFunc), /*obreak*/ + /* 18 */ SyscallDesc("unused#18", unimplementedFunc), + /* 19 */ SyscallDesc("lseek", lseekFunc), + /* 20 */ SyscallDesc("getpid", getpidFunc), + /* 21 */ SyscallDesc("mount", unimplementedFunc), + /* 22 */ SyscallDesc("umount", unimplementedFunc), + /* 23 */ SyscallDesc("setuid", setuidFunc), + /* 24 */ SyscallDesc("getuid", getuidFunc), + /* 25 */ SyscallDesc("stime", unimplementedFunc), + /* 26 */ SyscallDesc("ptrace", unimplementedFunc), + /* 27 */ SyscallDesc("alarm", unimplementedFunc), + /* 28 */ SyscallDesc("unused#28", unimplementedFunc), + /* 29 */ SyscallDesc("pause", unimplementedFunc), + /* 30 */ SyscallDesc("utime", unimplementedFunc), + /* 31 */ SyscallDesc("stty", unimplementedFunc), + /* 32 */ SyscallDesc("gtty", unimplementedFunc), + /* 33 */ SyscallDesc("access", unimplementedFunc), + /* 34 */ SyscallDesc("nice", unimplementedFunc), + /* 35 */ SyscallDesc("ftime", unimplementedFunc), + /* 36 */ SyscallDesc("sync", unimplementedFunc), + /* 37 */ SyscallDesc("kill", ignoreFunc), + /* 38 */ SyscallDesc("rename", unimplementedFunc), + /* 39 */ SyscallDesc("mkdir", unimplementedFunc), + /* 40 */ SyscallDesc("rmdir", unimplementedFunc), + /* 41 */ SyscallDesc("dup", unimplementedFunc), + /* 42 */ SyscallDesc("pipe", unimplementedFunc), + /* 43 */ SyscallDesc("times", unimplementedFunc), + /* 44 */ SyscallDesc("prof", unimplementedFunc), + /* 45 */ SyscallDesc("brk", obreakFunc),/*openFunc<MipsLinux>*/ + /* 46 */ SyscallDesc("setgid", unimplementedFunc), + /* 47 */ SyscallDesc("getgid", getgidFunc), + /* 48 */ SyscallDesc("signal", ignoreFunc), + /* 49 */ SyscallDesc("geteuid", geteuidFunc), + /* 50 */ SyscallDesc("getegid", getegidFunc), + /* 51 */ SyscallDesc("acct", unimplementedFunc), + /* 52 */ SyscallDesc("umount2", unimplementedFunc), + /* 53 */ SyscallDesc("lock", unimplementedFunc), + /* 54 */ SyscallDesc("ioctl", ioctlFunc<MipsLinux>), + /* 55 */ SyscallDesc("fcntl", unimplementedFunc), + /* 56 */ SyscallDesc("mpx", unimplementedFunc), + /* 57 */ SyscallDesc("setpgid", unimplementedFunc), + /* 58 */ SyscallDesc("ulimit", unimplementedFunc), + /* 59 */ SyscallDesc("unused#59", unimplementedFunc), + /* 60 */ SyscallDesc("umask", unimplementedFunc), + /* 61 */ SyscallDesc("chroot", unimplementedFunc), + /* 62 */ SyscallDesc("ustat", unimplementedFunc), + /* 63 */ SyscallDesc("dup2", unimplementedFunc), + /* 64 */ SyscallDesc("getppid", getpagesizeFunc), + /* 65 */ SyscallDesc("getpgrp", unimplementedFunc), + /* 66 */ SyscallDesc("setsid", unimplementedFunc), + /* 67 */ SyscallDesc("sigaction",unimplementedFunc), + /* 68 */ SyscallDesc("sgetmask", unimplementedFunc), + /* 69 */ SyscallDesc("ssetmask", unimplementedFunc), + /* 70 */ SyscallDesc("setreuid", unimplementedFunc), + /* 71 */ SyscallDesc("setregid", unimplementedFunc), + /* 72 */ SyscallDesc("sigsuspend", unimplementedFunc), + /* 73 */ SyscallDesc("sigpending", unimplementedFunc), + /* 74 */ SyscallDesc("sethostname", ignoreFunc), + /* 75 */ SyscallDesc("setrlimit", unimplementedFunc), + /* 76 */ SyscallDesc("getrlimit", unimplementedFunc), + /* 77 */ SyscallDesc("getrusage", unimplementedFunc), + /* 78 */ SyscallDesc("gettimeofday", unimplementedFunc), + /* 79 */ SyscallDesc("settimeofday", unimplementedFunc), + /* 80 */ SyscallDesc("getgroups", unimplementedFunc), + /* 81 */ SyscallDesc("setgroups", unimplementedFunc), + /* 82 */ SyscallDesc("reserved#82", unimplementedFunc), + /* 83 */ SyscallDesc("symlink", unimplementedFunc), + /* 84 */ SyscallDesc("unused#84", unimplementedFunc), + /* 85 */ SyscallDesc("readlink", unimplementedFunc), + /* 86 */ SyscallDesc("uselib", unimplementedFunc), + /* 87 */ SyscallDesc("swapon", gethostnameFunc), + /* 88 */ SyscallDesc("reboot", unimplementedFunc), + /* 89 */ SyscallDesc("readdir", unimplementedFunc), + /* 90 */ SyscallDesc("mmap", mmapFunc<MipsLinux>), + /* 91 */ SyscallDesc("munmap",munmapFunc), + /* 92 */ SyscallDesc("truncate", fcntlFunc), + /* 93 */ SyscallDesc("ftruncate", unimplementedFunc), + /* 94 */ SyscallDesc("fchmod", unimplementedFunc), + /* 95 */ SyscallDesc("fchown", unimplementedFunc), + /* 96 */ SyscallDesc("getpriority", unimplementedFunc), + /* 97 */ SyscallDesc("setpriority", unimplementedFunc), + /* 98 */ SyscallDesc("profil", unimplementedFunc), + /* 99 */ SyscallDesc("statfs", unimplementedFunc), + /* 100 */ SyscallDesc("fstatfs", unimplementedFunc), + /* 101 */ SyscallDesc("ioperm", unimplementedFunc), + /* 102 */ SyscallDesc("socketcall", unimplementedFunc), + /* 103 */ SyscallDesc("syslog", unimplementedFunc), + /* 104 */ SyscallDesc("setitimer", unimplementedFunc), + /* 105 */ SyscallDesc("getitimer", unimplementedFunc), + /* 106 */ SyscallDesc("stat", statFunc<MipsLinux>), + /* 107 */ SyscallDesc("lstat", unimplementedFunc), + /* 108 */ SyscallDesc("fstat", fstatFunc<MipsLinux>), + /* 109 */ SyscallDesc("unused#109", unimplementedFunc), + /* 110 */ SyscallDesc("iopl", unimplementedFunc), + /* 111 */ SyscallDesc("vhangup", unimplementedFunc), + /* 112 */ SyscallDesc("idle", ignoreFunc), + /* 113 */ SyscallDesc("vm86", unimplementedFunc), + /* 114 */ SyscallDesc("wait4", unimplementedFunc), + /* 115 */ SyscallDesc("swapoff", unimplementedFunc), + /* 116 */ SyscallDesc("sysinfo", unimplementedFunc), + /* 117 */ SyscallDesc("ipc", unimplementedFunc), + /* 118 */ SyscallDesc("fsync", unimplementedFunc), + /* 119 */ SyscallDesc("sigreturn", unimplementedFunc), + /* 120 */ SyscallDesc("clone", unimplementedFunc), + /* 121 */ SyscallDesc("setdomainname", unimplementedFunc), + /* 122 */ SyscallDesc("uname", unameFunc), + /* 123 */ SyscallDesc("modify_ldt", unimplementedFunc), + /* 124 */ SyscallDesc("adjtimex", unimplementedFunc), + /* 125 */ SyscallDesc("mprotect", ignoreFunc), + /* 126 */ SyscallDesc("sigprocmask", unimplementedFunc), + /* 127 */ SyscallDesc("create_module", unimplementedFunc), + /* 128 */ SyscallDesc("init_module", unimplementedFunc), + /* 129 */ SyscallDesc("delete_module", unimplementedFunc), + /* 130 */ SyscallDesc("get_kernel_syms", unimplementedFunc), + /* 131 */ SyscallDesc("quotactl", unimplementedFunc), + /* 132 */ SyscallDesc("getpgid", unimplementedFunc), + /* 133 */ SyscallDesc("fchdir", unimplementedFunc), + /* 134 */ SyscallDesc("bdflush", unimplementedFunc), + /* 135 */ SyscallDesc("sysfs", unimplementedFunc), + /* 136 */ SyscallDesc("personality", unimplementedFunc), + /* 137 */ SyscallDesc("afs_syscall", unimplementedFunc), + /* 138 */ SyscallDesc("setfsuid", unimplementedFunc), + /* 139 */ SyscallDesc("setfsgid", unimplementedFunc), + /* 140 */ SyscallDesc("llseek", unimplementedFunc), + /* 141 */ SyscallDesc("getdents", unimplementedFunc), + /* 142 */ SyscallDesc("newselect", unimplementedFunc), + /* 143 */ SyscallDesc("flock", unimplementedFunc), + /* 144 */ SyscallDesc("msync", unimplementedFunc),/*getrlimitFunc<MipsLinux>*/ + /* 145 */ SyscallDesc("readv", unimplementedFunc), + /* 146 */ SyscallDesc("writev", writevFunc<MipsLinux>), + /* 147 */ SyscallDesc("cacheflush", unimplementedFunc), + /* 148 */ SyscallDesc("cachectl", unimplementedFunc), + /* 149 */ SyscallDesc("sysmips", unimplementedFunc), + /* 150 */ SyscallDesc("unused#150", unimplementedFunc), + /* 151 */ SyscallDesc("getsid", unimplementedFunc), + /* 152 */ SyscallDesc("fdatasync", unimplementedFunc), + /* 153 */ SyscallDesc("sysctl", unimplementedFunc), + /* 154 */ SyscallDesc("mlock", unimplementedFunc), + /* 155 */ SyscallDesc("munlock", unimplementedFunc), + /* 156 */ SyscallDesc("mlockall", unimplementedFunc), + /* 157 */ SyscallDesc("munlockall", unimplementedFunc), + /* 158 */ SyscallDesc("sched_setparam", unimplementedFunc), + /* 159 */ SyscallDesc("sched_getparam", unimplementedFunc), + /* 160 */ SyscallDesc("sched_setscheduler", unimplementedFunc), + /* 161 */ SyscallDesc("sched_getscheduler", unimplementedFunc), + /* 162 */ SyscallDesc("sched_yield", unimplementedFunc), + /* 163 */ SyscallDesc("sched_get_prioritymax", unimplementedFunc), + /* 164 */ SyscallDesc("sched_get_priority_min", unimplementedFunc), + /* 165 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc), + /* 166 */ SyscallDesc("nanosleep", unimplementedFunc), + /* 167 */ SyscallDesc("mremap", unimplementedFunc), + /* 168 */ SyscallDesc("accept", unimplementedFunc), + /* 169 */ SyscallDesc("bind", unimplementedFunc), + /* 170 */ SyscallDesc("connect", unimplementedFunc), + /* 171 */ SyscallDesc("getpeername", unimplementedFunc), + /* 172 */ SyscallDesc("getsockname", unimplementedFunc), + /* 173 */ SyscallDesc("getsockopt", unimplementedFunc), + /* 174 */ SyscallDesc("listen", unimplementedFunc), + /* 175 */ SyscallDesc("recv", unimplementedFunc), + /* 176 */ SyscallDesc("recvmsg", unimplementedFunc), + /* 177 */ SyscallDesc("send", unimplementedFunc), + /* 178 */ SyscallDesc("sendmsg", ignoreFunc), + /* 179 */ SyscallDesc("sendto", unimplementedFunc), + /* 180 */ SyscallDesc("setsockopt", unimplementedFunc), + /* 181 */ SyscallDesc("shutdown", unimplementedFunc), + /* 182 */ SyscallDesc("unknown #182", unimplementedFunc), + /* 183 */ SyscallDesc("socket", ignoreFunc), + /* 184 */ SyscallDesc("socketpair", unimplementedFunc), + /* 185 */ SyscallDesc("setresuid", unimplementedFunc), + /* 186 */ SyscallDesc("getresuid", unimplementedFunc), + /* 187 */ SyscallDesc("query_module", unimplementedFunc), + /* 188 */ SyscallDesc("poll", unimplementedFunc), + /* 189 */ SyscallDesc("nfsservctl", unimplementedFunc), + /* 190 */ SyscallDesc("setresgid", unimplementedFunc), + /* 191 */ SyscallDesc("getresgid", unimplementedFunc), + /* 192 */ SyscallDesc("prctl", unimplementedFunc), + /* 193 */ SyscallDesc("rt_sigreturn", unimplementedFunc), + /* 194 */ SyscallDesc("rt_sigaction", ignoreFunc), + /* 195 */ SyscallDesc("rt_sigprocmask", ignoreFunc), + /* 196 */ SyscallDesc("rt_sigpending", unimplementedFunc), + /* 197 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc), + /* 198 */ SyscallDesc("rt_sigqueueinfo", ignoreFunc), + /* 199 */ SyscallDesc("rt_sigsuspend", unimplementedFunc), + /* 200 */ SyscallDesc("pread64", unimplementedFunc), + /* 201 */ SyscallDesc("pwrite64", unimplementedFunc), + /* 202 */ SyscallDesc("chown", unimplementedFunc), + /* 203 */ SyscallDesc("getcwd", unimplementedFunc), + /* 204 */ SyscallDesc("capget", unimplementedFunc), + /* 205 */ SyscallDesc("capset", unimplementedFunc), + /* 206 */ SyscallDesc("sigalstack", unimplementedFunc), + /* 207 */ SyscallDesc("sendfile", unimplementedFunc), + /* 208 */ SyscallDesc("getpmsg", unimplementedFunc), + /* 209 */ SyscallDesc("putpmsg", unimplementedFunc), + /* 210 */ SyscallDesc("mmap2", unimplementedFunc), + /* 211 */ SyscallDesc("truncate64", unimplementedFunc), + /* 212 */ SyscallDesc("ftruncate64", unimplementedFunc), + /* 213 */ SyscallDesc("stat64", unimplementedFunc), + /* 214 */ SyscallDesc("lstat64", lstat64Func<MipsLinux>), + /* 215 */ SyscallDesc("fstat64", fstat64Func<MipsLinux>), + /* 216 */ SyscallDesc("pivot_root", unimplementedFunc), + /* 217 */ SyscallDesc("mincore", unimplementedFunc), + /* 218 */ SyscallDesc("madvise", unimplementedFunc), + /* 219 */ SyscallDesc("getdents64", unimplementedFunc), + /* 220 */ SyscallDesc("fcntl64", fcntlFunc), + /* 221 */ SyscallDesc("reserved#221", unimplementedFunc), + /* 222 */ SyscallDesc("gettid", unimplementedFunc), + /* 223 */ SyscallDesc("readahead", unimplementedFunc), + /* 224 */ SyscallDesc("setxattr", unimplementedFunc), + /* 225 */ SyscallDesc("lsetxattr", unimplementedFunc), + /* 226 */ SyscallDesc("fsetxattr", unimplementedFunc), + /* 227 */ SyscallDesc("getxattr", unimplementedFunc), + /* 228 */ SyscallDesc("lgetxattr", unimplementedFunc), + /* 229 */ SyscallDesc("fgetxattr", unimplementedFunc), + /* 230 */ SyscallDesc("listxattr", unimplementedFunc), + /* 231 */ SyscallDesc("llistxattr", unimplementedFunc), + /* 232 */ SyscallDesc("flistxattr", unimplementedFunc), + /* 233 */ SyscallDesc("removexattr", unimplementedFunc), + /* 234 */ SyscallDesc("lremovexattr", unimplementedFunc), + /* 235 */ SyscallDesc("fremovexattr", ignoreFunc), + /* 236 */ SyscallDesc("tkill", unimplementedFunc), + /* 237 */ SyscallDesc("sendfile64", unimplementedFunc), + /* 238 */ SyscallDesc("futex", unimplementedFunc), + /* 239 */ SyscallDesc("sched_setaffinity", unimplementedFunc), + /* 240 */ SyscallDesc("sched_getaffinity", unimplementedFunc), + /* 241 */ SyscallDesc("io_setup", unimplementedFunc), + /* 242 */ SyscallDesc("io_destroy", unimplementedFunc), + /* 243 */ SyscallDesc("io_getevents", unimplementedFunc), + /* 244 */ SyscallDesc("io_submit", unimplementedFunc), + /* 245 */ SyscallDesc("io_cancel", unimplementedFunc), + /* 246 */ SyscallDesc("exit_group", exitFunc), + /* 247 */ SyscallDesc("lookup_dcookie", unimplementedFunc), + /* 248 */ SyscallDesc("epoll_create", unimplementedFunc), + /* 249 */ SyscallDesc("epoll_ctl", unimplementedFunc), + /* 250 */ SyscallDesc("epoll_wait", unimplementedFunc), + /* 251 */ SyscallDesc("remap_file_pages", unimplementedFunc), + /* 252 */ SyscallDesc("set_tid_address", unimplementedFunc), + /* 253 */ SyscallDesc("restart_syscall", unimplementedFunc), + /* 254 */ SyscallDesc("fadvise64", unimplementedFunc), + /* 255 */ SyscallDesc("statfs64", unimplementedFunc), + /* 256 */ SyscallDesc("fstafs64", unimplementedFunc), + /* 257 */ SyscallDesc("timer_create", sys_getsysinfoFunc), + /* 258 */ SyscallDesc("timer_settime", sys_setsysinfoFunc), + /* 259 */ SyscallDesc("timer_gettime", unimplementedFunc), + /* 260 */ SyscallDesc("timer_getoverrun", unimplementedFunc), + /* 261 */ SyscallDesc("timer_delete", unimplementedFunc), + /* 262 */ SyscallDesc("clock_settime", unimplementedFunc), + /* 263 */ SyscallDesc("clock_gettime", unimplementedFunc), + /* 264 */ SyscallDesc("clock_getres", unimplementedFunc), + /* 265 */ SyscallDesc("clock_nanosleep", unimplementedFunc), + /* 266 */ SyscallDesc("tgkill", unimplementedFunc), + /* 267 */ SyscallDesc("utimes", unimplementedFunc), + /* 268 */ SyscallDesc("mbind", unimplementedFunc), + /* 269 */ SyscallDesc("get_mempolicy", unimplementedFunc), + /* 270 */ SyscallDesc("set_mempolicy", unimplementedFunc), + /* 271 */ SyscallDesc("mq_open", unimplementedFunc), + /* 272 */ SyscallDesc("mq_unlink", unimplementedFunc), + /* 273 */ SyscallDesc("mq_timedsend", unimplementedFunc), + /* 274 */ SyscallDesc("mq_timedreceive", unimplementedFunc), + /* 275 */ SyscallDesc("mq_notify", unimplementedFunc), + /* 276 */ SyscallDesc("mq_getsetattr", unimplementedFunc), + /* 277 */ SyscallDesc("vserver", unimplementedFunc), + /* 278 */ SyscallDesc("waitid", unimplementedFunc), + /* 279 */ SyscallDesc("unknown #279", unimplementedFunc), + /* 280 */ SyscallDesc("add_key", unimplementedFunc), + /* 281 */ SyscallDesc("request_key", unimplementedFunc), + /* 282 */ SyscallDesc("keyctl", unimplementedFunc), +}; + +MipsLinuxProcess::MipsLinuxProcess(const std::string &name, + ObjectFile *objFile, + System *system, + int stdin_fd, + int stdout_fd, + int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp) + : MipsLiveProcess(name, objFile, system, stdin_fd, stdout_fd, stderr_fd, + argv, envp), + Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) +{ + //init_regs->intRegFile[0] = 0; +} + +SyscallDesc* +MipsLinuxProcess::getDesc(int callnum) +{ + //MIPS32 syscalls are in the range of 4000 - 4999 + int m5_sys_idx = callnum - 4000; + + if (m5_sys_idx < 0 || m5_sys_idx > Num_Syscall_Descs) + return NULL; + + return &syscallDescs[m5_sys_idx]; +} diff --git a/arch/mips/linux_process.hh b/arch/mips/linux/process.hh index 5408a6c44..68da3227b 100644 --- a/arch/mips/linux_process.hh +++ b/arch/mips/linux/process.hh @@ -29,16 +29,17 @@ #ifndef __MIPS_LINUX_PROCESS_HH__ #define __MIPS_LINUX_PROCESS_HH__ -#include "sim/process.hh" +#include "arch/mips/process.hh" /// A process with emulated Mips/Linux syscalls. -class MipsLinuxProcess : public LiveProcess +class MipsLinuxProcess : public MipsLiveProcess { public: /// Constructor. MipsLinuxProcess(const std::string &name, ObjectFile *objFile, + System *system, int stdin_fd, int stdout_fd, int stderr_fd, std::vector<std::string> &argv, std::vector<std::string> &envp); diff --git a/arch/mips/linux_process.cc b/arch/mips/linux_process.cc deleted file mode 100644 index 1d4f62350..000000000 --- a/arch/mips/linux_process.cc +++ /dev/null @@ -1,588 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "arch/mips/common_syscall_emul.hh" -#include "arch/mips/linux_process.hh" -#include "arch/mips/isa_traits.hh" - -#include "base/trace.hh" -#include "cpu/exec_context.hh" -#include "kern/linux/linux.hh" -#include "mem/functional/functional.hh" - -#include "sim/process.hh" -#include "sim/syscall_emul.hh" - -using namespace std; -using namespace MipsISA; - -/// Target uname() handler. -static SyscallReturn -unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) -{ - TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0)); - - strcpy(name->sysname, "Linux"); - strcpy(name->nodename, "m5.eecs.umich.edu"); - strcpy(name->release, "2.4.20"); - strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); - strcpy(name->machine, "mips"); - - name.copyOut(xc->mem); - return 0; -} - -/// Target osf_getsysyinfo() handler. Even though this call is -/// borrowed from Tru64, the subcases that get used appear to be -/// different in practice from those used by Tru64 processes. -static SyscallReturn -osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) -{ - unsigned op = xc->getSyscallArg(0); - // unsigned nbytes = xc->getSyscallArg(2); - - switch (op) { - - case 45: { // GSI_IEEE_FP_CONTROL - TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); - // I don't think this exactly matches the HW FPCR - *fpcr = 0; - fpcr.copyOut(xc->mem); - return 0; - } - - default: - cerr << "osf_getsysinfo: unknown op " << op << endl; - abort(); - break; - } - - return 1; -} - -/// Target osf_setsysinfo() handler. -static SyscallReturn -osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) -{ - unsigned op = xc->getSyscallArg(0); - // unsigned nbytes = xc->getSyscallArg(2); - - switch (op) { - - case 14: { // SSI_IEEE_FP_CONTROL - TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); - // I don't think this exactly matches the HW FPCR - fpcr.copyIn(xc->mem); - DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): " - " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr)); - return 0; - } - - default: - cerr << "osf_setsysinfo: unknown op " << op << endl; - abort(); - break; - } - - return 1; -} - - -SyscallDesc MipsLinuxProcess::syscallDescs[] = { - /* 0 */ SyscallDesc("osf_syscall", unimplementedFunc), - /* 1 */ SyscallDesc("exit", exitFunc), - /* 2 */ SyscallDesc("fork", unimplementedFunc), - /* 3 */ SyscallDesc("read", readFunc), - /* 4 */ SyscallDesc("write", writeFunc), - /* 5 */ SyscallDesc("osf_old_open", unimplementedFunc), - /* 6 */ SyscallDesc("close", closeFunc), - /* 7 */ SyscallDesc("osf_wait4", unimplementedFunc), - /* 8 */ SyscallDesc("osf_old_creat", unimplementedFunc), - /* 9 */ SyscallDesc("link", unimplementedFunc), - /* 10 */ SyscallDesc("unlink", unlinkFunc), - /* 11 */ SyscallDesc("osf_execve", unimplementedFunc), - /* 12 */ SyscallDesc("chdir", unimplementedFunc), - /* 13 */ SyscallDesc("fchdir", unimplementedFunc), - /* 14 */ SyscallDesc("mknod", unimplementedFunc), - /* 15 */ SyscallDesc("chmod", chmodFunc<Linux>), - /* 16 */ SyscallDesc("chown", chownFunc), - /* 17 */ SyscallDesc("brk", obreakFunc), - /* 18 */ SyscallDesc("osf_getfsstat", unimplementedFunc), - /* 19 */ SyscallDesc("lseek", lseekFunc), - /* 20 */ SyscallDesc("getxpid", getpidFunc), - /* 21 */ SyscallDesc("osf_mount", unimplementedFunc), - /* 22 */ SyscallDesc("umount", unimplementedFunc), - /* 23 */ SyscallDesc("setuid", setuidFunc), - /* 24 */ SyscallDesc("getxuid", getuidFunc), - /* 25 */ SyscallDesc("exec_with_loader", unimplementedFunc), - /* 26 */ SyscallDesc("osf_ptrace", unimplementedFunc), - /* 27 */ SyscallDesc("osf_nrecvmsg", unimplementedFunc), - /* 28 */ SyscallDesc("osf_nsendmsg", unimplementedFunc), - /* 29 */ SyscallDesc("osf_nrecvfrom", unimplementedFunc), - /* 30 */ SyscallDesc("osf_naccept", unimplementedFunc), - /* 31 */ SyscallDesc("osf_ngetpeername", unimplementedFunc), - /* 32 */ SyscallDesc("osf_ngetsockname", unimplementedFunc), - /* 33 */ SyscallDesc("access", unimplementedFunc), - /* 34 */ SyscallDesc("osf_chflags", unimplementedFunc), - /* 35 */ SyscallDesc("osf_fchflags", unimplementedFunc), - /* 36 */ SyscallDesc("sync", unimplementedFunc), - /* 37 */ SyscallDesc("kill", unimplementedFunc), - /* 38 */ SyscallDesc("osf_old_stat", unimplementedFunc), - /* 39 */ SyscallDesc("setpgid", unimplementedFunc), - /* 40 */ SyscallDesc("osf_old_lstat", unimplementedFunc), - /* 41 */ SyscallDesc("dup", unimplementedFunc), - /* 42 */ SyscallDesc("pipe", unimplementedFunc), - /* 43 */ SyscallDesc("osf_set_program_attributes", unimplementedFunc), - /* 44 */ SyscallDesc("osf_profil", unimplementedFunc), - /* 45 */ SyscallDesc("open", openFunc<Linux>), - /* 46 */ SyscallDesc("osf_old_sigaction", unimplementedFunc), - /* 47 */ SyscallDesc("getxgid", getgidFunc), - /* 48 */ SyscallDesc("osf_sigprocmask", ignoreFunc), - /* 49 */ SyscallDesc("osf_getlogin", unimplementedFunc), - /* 50 */ SyscallDesc("osf_setlogin", unimplementedFunc), - /* 51 */ SyscallDesc("acct", unimplementedFunc), - /* 52 */ SyscallDesc("sigpending", unimplementedFunc), - /* 53 */ SyscallDesc("osf_classcntl", unimplementedFunc), - /* 54 */ SyscallDesc("ioctl", ioctlFunc<Linux>), - /* 55 */ SyscallDesc("osf_reboot", unimplementedFunc), - /* 56 */ SyscallDesc("osf_revoke", unimplementedFunc), - /* 57 */ SyscallDesc("symlink", unimplementedFunc), - /* 58 */ SyscallDesc("readlink", unimplementedFunc), - /* 59 */ SyscallDesc("execve", unimplementedFunc), - /* 60 */ SyscallDesc("umask", unimplementedFunc), - /* 61 */ SyscallDesc("chroot", unimplementedFunc), - /* 62 */ SyscallDesc("osf_old_fstat", unimplementedFunc), - /* 63 */ SyscallDesc("getpgrp", unimplementedFunc), - /* 64 */ SyscallDesc("getpagesize", getpagesizeFunc), - /* 65 */ SyscallDesc("osf_mremap", unimplementedFunc), - /* 66 */ SyscallDesc("vfork", unimplementedFunc), - /* 67 */ SyscallDesc("stat", statFunc<Linux>), - /* 68 */ SyscallDesc("lstat", lstatFunc<Linux>), - /* 69 */ SyscallDesc("osf_sbrk", unimplementedFunc), - /* 70 */ SyscallDesc("osf_sstk", unimplementedFunc), - /* 71 */ SyscallDesc("mmap", mmapFunc<Linux>), - /* 72 */ SyscallDesc("osf_old_vadvise", unimplementedFunc), - /* 73 */ SyscallDesc("munmap", munmapFunc), - /* 74 */ SyscallDesc("mprotect", ignoreFunc), - /* 75 */ SyscallDesc("madvise", unimplementedFunc), - /* 76 */ SyscallDesc("vhangup", unimplementedFunc), - /* 77 */ SyscallDesc("osf_kmodcall", unimplementedFunc), - /* 78 */ SyscallDesc("osf_mincore", unimplementedFunc), - /* 79 */ SyscallDesc("getgroups", unimplementedFunc), - /* 80 */ SyscallDesc("setgroups", unimplementedFunc), - /* 81 */ SyscallDesc("osf_old_getpgrp", unimplementedFunc), - /* 82 */ SyscallDesc("setpgrp", unimplementedFunc), - /* 83 */ SyscallDesc("osf_setitimer", unimplementedFunc), - /* 84 */ SyscallDesc("osf_old_wait", unimplementedFunc), - /* 85 */ SyscallDesc("osf_table", unimplementedFunc), - /* 86 */ SyscallDesc("osf_getitimer", unimplementedFunc), - /* 87 */ SyscallDesc("gethostname", gethostnameFunc), - /* 88 */ SyscallDesc("sethostname", unimplementedFunc), - /* 89 */ SyscallDesc("getdtablesize", unimplementedFunc), - /* 90 */ SyscallDesc("dup2", unimplementedFunc), - /* 91 */ SyscallDesc("fstat", fstatFunc<Linux>), - /* 92 */ SyscallDesc("fcntl", fcntlFunc), - /* 93 */ SyscallDesc("osf_select", unimplementedFunc), - /* 94 */ SyscallDesc("poll", unimplementedFunc), - /* 95 */ SyscallDesc("fsync", unimplementedFunc), - /* 96 */ SyscallDesc("setpriority", unimplementedFunc), - /* 97 */ SyscallDesc("socket", unimplementedFunc), - /* 98 */ SyscallDesc("connect", unimplementedFunc), - /* 99 */ SyscallDesc("accept", unimplementedFunc), - /* 100 */ SyscallDesc("getpriority", unimplementedFunc), - /* 101 */ SyscallDesc("send", unimplementedFunc), - /* 102 */ SyscallDesc("recv", unimplementedFunc), - /* 103 */ SyscallDesc("sigreturn", unimplementedFunc), - /* 104 */ SyscallDesc("bind", unimplementedFunc), - /* 105 */ SyscallDesc("setsockopt", unimplementedFunc), - /* 106 */ SyscallDesc("listen", unimplementedFunc), - /* 107 */ SyscallDesc("osf_plock", unimplementedFunc), - /* 108 */ SyscallDesc("osf_old_sigvec", unimplementedFunc), - /* 109 */ SyscallDesc("osf_old_sigblock", unimplementedFunc), - /* 110 */ SyscallDesc("osf_old_sigsetmask", unimplementedFunc), - /* 111 */ SyscallDesc("sigsuspend", unimplementedFunc), - /* 112 */ SyscallDesc("osf_sigstack", ignoreFunc), - /* 113 */ SyscallDesc("recvmsg", unimplementedFunc), - /* 114 */ SyscallDesc("sendmsg", unimplementedFunc), - /* 115 */ SyscallDesc("osf_old_vtrace", unimplementedFunc), - /* 116 */ SyscallDesc("osf_gettimeofday", unimplementedFunc), - /* 117 */ SyscallDesc("osf_getrusage", unimplementedFunc), - /* 118 */ SyscallDesc("getsockopt", unimplementedFunc), - /* 119 */ SyscallDesc("numa_syscalls", unimplementedFunc), - /* 120 */ SyscallDesc("readv", unimplementedFunc), - /* 121 */ SyscallDesc("writev", writevFunc<Linux>), - /* 122 */ SyscallDesc("osf_settimeofday", unimplementedFunc), - /* 123 */ SyscallDesc("fchown", fchownFunc), - /* 124 */ SyscallDesc("fchmod", fchmodFunc<Linux>), - /* 125 */ SyscallDesc("recvfrom", unimplementedFunc), - /* 126 */ SyscallDesc("setreuid", unimplementedFunc), - /* 127 */ SyscallDesc("setregid", unimplementedFunc), - /* 128 */ SyscallDesc("rename", renameFunc), - /* 129 */ SyscallDesc("truncate", unimplementedFunc), - /* 130 */ SyscallDesc("ftruncate", unimplementedFunc), - /* 131 */ SyscallDesc("flock", unimplementedFunc), - /* 132 */ SyscallDesc("setgid", unimplementedFunc), - /* 133 */ SyscallDesc("sendto", unimplementedFunc), - /* 134 */ SyscallDesc("shutdown", unimplementedFunc), - /* 135 */ SyscallDesc("socketpair", unimplementedFunc), - /* 136 */ SyscallDesc("mkdir", unimplementedFunc), - /* 137 */ SyscallDesc("rmdir", unimplementedFunc), - /* 138 */ SyscallDesc("osf_utimes", unimplementedFunc), - /* 139 */ SyscallDesc("osf_old_sigreturn", unimplementedFunc), - /* 140 */ SyscallDesc("osf_adjtime", unimplementedFunc), - /* 141 */ SyscallDesc("getpeername", unimplementedFunc), - /* 142 */ SyscallDesc("osf_gethostid", unimplementedFunc), - /* 143 */ SyscallDesc("osf_sethostid", unimplementedFunc), - /* 144 */ SyscallDesc("getrlimit", getrlimitFunc<Linux>), - /* 145 */ SyscallDesc("setrlimit", ignoreFunc), - /* 146 */ SyscallDesc("osf_old_killpg", unimplementedFunc), - /* 147 */ SyscallDesc("setsid", unimplementedFunc), - /* 148 */ SyscallDesc("quotactl", unimplementedFunc), - /* 149 */ SyscallDesc("osf_oldquota", unimplementedFunc), - /* 150 */ SyscallDesc("getsockname", unimplementedFunc), - /* 151 */ SyscallDesc("osf_pread", unimplementedFunc), - /* 152 */ SyscallDesc("osf_pwrite", unimplementedFunc), - /* 153 */ SyscallDesc("osf_pid_block", unimplementedFunc), - /* 154 */ SyscallDesc("osf_pid_unblock", unimplementedFunc), - /* 155 */ SyscallDesc("osf_signal_urti", unimplementedFunc), - /* 156 */ SyscallDesc("sigaction", ignoreFunc), - /* 157 */ SyscallDesc("osf_sigwaitprim", unimplementedFunc), - /* 158 */ SyscallDesc("osf_nfssvc", unimplementedFunc), - /* 159 */ SyscallDesc("osf_getdirentries", unimplementedFunc), - /* 160 */ SyscallDesc("osf_statfs", unimplementedFunc), - /* 161 */ SyscallDesc("osf_fstatfs", unimplementedFunc), - /* 162 */ SyscallDesc("unknown #162", unimplementedFunc), - /* 163 */ SyscallDesc("osf_async_daemon", unimplementedFunc), - /* 164 */ SyscallDesc("osf_getfh", unimplementedFunc), - /* 165 */ SyscallDesc("osf_getdomainname", unimplementedFunc), - /* 166 */ SyscallDesc("setdomainname", unimplementedFunc), - /* 167 */ SyscallDesc("unknown #167", unimplementedFunc), - /* 168 */ SyscallDesc("unknown #168", unimplementedFunc), - /* 169 */ SyscallDesc("osf_exportfs", unimplementedFunc), - /* 170 */ SyscallDesc("unknown #170", unimplementedFunc), - /* 171 */ SyscallDesc("unknown #171", unimplementedFunc), - /* 172 */ SyscallDesc("unknown #172", unimplementedFunc), - /* 173 */ SyscallDesc("unknown #173", unimplementedFunc), - /* 174 */ SyscallDesc("unknown #174", unimplementedFunc), - /* 175 */ SyscallDesc("unknown #175", unimplementedFunc), - /* 176 */ SyscallDesc("unknown #176", unimplementedFunc), - /* 177 */ SyscallDesc("unknown #177", unimplementedFunc), - /* 178 */ SyscallDesc("unknown #178", unimplementedFunc), - /* 179 */ SyscallDesc("unknown #179", unimplementedFunc), - /* 180 */ SyscallDesc("unknown #180", unimplementedFunc), - /* 181 */ SyscallDesc("osf_alt_plock", unimplementedFunc), - /* 182 */ SyscallDesc("unknown #182", unimplementedFunc), - /* 183 */ SyscallDesc("unknown #183", unimplementedFunc), - /* 184 */ SyscallDesc("osf_getmnt", unimplementedFunc), - /* 185 */ SyscallDesc("unknown #185", unimplementedFunc), - /* 186 */ SyscallDesc("unknown #186", unimplementedFunc), - /* 187 */ SyscallDesc("osf_alt_sigpending", unimplementedFunc), - /* 188 */ SyscallDesc("osf_alt_setsid", unimplementedFunc), - /* 189 */ SyscallDesc("unknown #189", unimplementedFunc), - /* 190 */ SyscallDesc("unknown #190", unimplementedFunc), - /* 191 */ SyscallDesc("unknown #191", unimplementedFunc), - /* 192 */ SyscallDesc("unknown #192", unimplementedFunc), - /* 193 */ SyscallDesc("unknown #193", unimplementedFunc), - /* 194 */ SyscallDesc("unknown #194", unimplementedFunc), - /* 195 */ SyscallDesc("unknown #195", unimplementedFunc), - /* 196 */ SyscallDesc("unknown #196", unimplementedFunc), - /* 197 */ SyscallDesc("unknown #197", unimplementedFunc), - /* 198 */ SyscallDesc("unknown #198", unimplementedFunc), - /* 199 */ SyscallDesc("osf_swapon", unimplementedFunc), - /* 200 */ SyscallDesc("msgctl", unimplementedFunc), - /* 201 */ SyscallDesc("msgget", unimplementedFunc), - /* 202 */ SyscallDesc("msgrcv", unimplementedFunc), - /* 203 */ SyscallDesc("msgsnd", unimplementedFunc), - /* 204 */ SyscallDesc("semctl", unimplementedFunc), - /* 205 */ SyscallDesc("semget", unimplementedFunc), - /* 206 */ SyscallDesc("semop", unimplementedFunc), - /* 207 */ SyscallDesc("osf_utsname", unimplementedFunc), - /* 208 */ SyscallDesc("lchown", unimplementedFunc), - /* 209 */ SyscallDesc("osf_shmat", unimplementedFunc), - /* 210 */ SyscallDesc("shmctl", unimplementedFunc), - /* 211 */ SyscallDesc("shmdt", unimplementedFunc), - /* 212 */ SyscallDesc("shmget", unimplementedFunc), - /* 213 */ SyscallDesc("osf_mvalid", unimplementedFunc), - /* 214 */ SyscallDesc("osf_getaddressconf", unimplementedFunc), - /* 215 */ SyscallDesc("osf_msleep", unimplementedFunc), - /* 216 */ SyscallDesc("osf_mwakeup", unimplementedFunc), - /* 217 */ SyscallDesc("msync", unimplementedFunc), - /* 218 */ SyscallDesc("osf_signal", unimplementedFunc), - /* 219 */ SyscallDesc("osf_utc_gettime", unimplementedFunc), - /* 220 */ SyscallDesc("osf_utc_adjtime", unimplementedFunc), - /* 221 */ SyscallDesc("unknown #221", unimplementedFunc), - /* 222 */ SyscallDesc("osf_security", unimplementedFunc), - /* 223 */ SyscallDesc("osf_kloadcall", unimplementedFunc), - /* 224 */ SyscallDesc("unknown #224", unimplementedFunc), - /* 225 */ SyscallDesc("unknown #225", unimplementedFunc), - /* 226 */ SyscallDesc("unknown #226", unimplementedFunc), - /* 227 */ SyscallDesc("unknown #227", unimplementedFunc), - /* 228 */ SyscallDesc("unknown #228", unimplementedFunc), - /* 229 */ SyscallDesc("unknown #229", unimplementedFunc), - /* 230 */ SyscallDesc("unknown #230", unimplementedFunc), - /* 231 */ SyscallDesc("unknown #231", unimplementedFunc), - /* 232 */ SyscallDesc("unknown #232", unimplementedFunc), - /* 233 */ SyscallDesc("getpgid", unimplementedFunc), - /* 234 */ SyscallDesc("getsid", unimplementedFunc), - /* 235 */ SyscallDesc("sigaltstack", ignoreFunc), - /* 236 */ SyscallDesc("osf_waitid", unimplementedFunc), - /* 237 */ SyscallDesc("osf_priocntlset", unimplementedFunc), - /* 238 */ SyscallDesc("osf_sigsendset", unimplementedFunc), - /* 239 */ SyscallDesc("osf_set_speculative", unimplementedFunc), - /* 240 */ SyscallDesc("osf_msfs_syscall", unimplementedFunc), - /* 241 */ SyscallDesc("osf_sysinfo", unimplementedFunc), - /* 242 */ SyscallDesc("osf_uadmin", unimplementedFunc), - /* 243 */ SyscallDesc("osf_fuser", unimplementedFunc), - /* 244 */ SyscallDesc("osf_proplist_syscall", unimplementedFunc), - /* 245 */ SyscallDesc("osf_ntp_adjtime", unimplementedFunc), - /* 246 */ SyscallDesc("osf_ntp_gettime", unimplementedFunc), - /* 247 */ SyscallDesc("osf_pathconf", unimplementedFunc), - /* 248 */ SyscallDesc("osf_fpathconf", unimplementedFunc), - /* 249 */ SyscallDesc("unknown #249", unimplementedFunc), - /* 250 */ SyscallDesc("osf_uswitch", unimplementedFunc), - /* 251 */ SyscallDesc("osf_usleep_thread", unimplementedFunc), - /* 252 */ SyscallDesc("osf_audcntl", unimplementedFunc), - /* 253 */ SyscallDesc("osf_audgen", unimplementedFunc), - /* 254 */ SyscallDesc("sysfs", unimplementedFunc), - /* 255 */ SyscallDesc("osf_subsys_info", unimplementedFunc), - /* 256 */ SyscallDesc("osf_getsysinfo", osf_getsysinfoFunc), - /* 257 */ SyscallDesc("osf_setsysinfo", osf_setsysinfoFunc), - /* 258 */ SyscallDesc("osf_afs_syscall", unimplementedFunc), - /* 259 */ SyscallDesc("osf_swapctl", unimplementedFunc), - /* 260 */ SyscallDesc("osf_memcntl", unimplementedFunc), - /* 261 */ SyscallDesc("osf_fdatasync", unimplementedFunc), - /* 262 */ SyscallDesc("unknown #262", unimplementedFunc), - /* 263 */ SyscallDesc("unknown #263", unimplementedFunc), - /* 264 */ SyscallDesc("unknown #264", unimplementedFunc), - /* 265 */ SyscallDesc("unknown #265", unimplementedFunc), - /* 266 */ SyscallDesc("unknown #266", unimplementedFunc), - /* 267 */ SyscallDesc("unknown #267", unimplementedFunc), - /* 268 */ SyscallDesc("unknown #268", unimplementedFunc), - /* 269 */ SyscallDesc("unknown #269", unimplementedFunc), - /* 270 */ SyscallDesc("unknown #270", unimplementedFunc), - /* 271 */ SyscallDesc("unknown #271", unimplementedFunc), - /* 272 */ SyscallDesc("unknown #272", unimplementedFunc), - /* 273 */ SyscallDesc("unknown #273", unimplementedFunc), - /* 274 */ SyscallDesc("unknown #274", unimplementedFunc), - /* 275 */ SyscallDesc("unknown #275", unimplementedFunc), - /* 276 */ SyscallDesc("unknown #276", unimplementedFunc), - /* 277 */ SyscallDesc("unknown #277", unimplementedFunc), - /* 278 */ SyscallDesc("unknown #278", unimplementedFunc), - /* 279 */ SyscallDesc("unknown #279", unimplementedFunc), - /* 280 */ SyscallDesc("unknown #280", unimplementedFunc), - /* 281 */ SyscallDesc("unknown #281", unimplementedFunc), - /* 282 */ SyscallDesc("unknown #282", unimplementedFunc), - /* 283 */ SyscallDesc("unknown #283", unimplementedFunc), - /* 284 */ SyscallDesc("unknown #284", unimplementedFunc), - /* 285 */ SyscallDesc("unknown #285", unimplementedFunc), - /* 286 */ SyscallDesc("unknown #286", unimplementedFunc), - /* 287 */ SyscallDesc("unknown #287", unimplementedFunc), - /* 288 */ SyscallDesc("unknown #288", unimplementedFunc), - /* 289 */ SyscallDesc("unknown #289", unimplementedFunc), - /* 290 */ SyscallDesc("unknown #290", unimplementedFunc), - /* 291 */ SyscallDesc("unknown #291", unimplementedFunc), - /* 292 */ SyscallDesc("unknown #292", unimplementedFunc), - /* 293 */ SyscallDesc("unknown #293", unimplementedFunc), - /* 294 */ SyscallDesc("unknown #294", unimplementedFunc), - /* 295 */ SyscallDesc("unknown #295", unimplementedFunc), - /* 296 */ SyscallDesc("unknown #296", unimplementedFunc), - /* 297 */ SyscallDesc("unknown #297", unimplementedFunc), - /* 298 */ SyscallDesc("unknown #298", unimplementedFunc), - /* 299 */ SyscallDesc("unknown #299", unimplementedFunc), -/* - * Linux-specific system calls begin at 300 - */ - /* 300 */ SyscallDesc("bdflush", unimplementedFunc), - /* 301 */ SyscallDesc("sethae", unimplementedFunc), - /* 302 */ SyscallDesc("mount", unimplementedFunc), - /* 303 */ SyscallDesc("old_adjtimex", unimplementedFunc), - /* 304 */ SyscallDesc("swapoff", unimplementedFunc), - /* 305 */ SyscallDesc("getdents", unimplementedFunc), - /* 306 */ SyscallDesc("create_module", unimplementedFunc), - /* 307 */ SyscallDesc("init_module", unimplementedFunc), - /* 308 */ SyscallDesc("delete_module", unimplementedFunc), - /* 309 */ SyscallDesc("get_kernel_syms", unimplementedFunc), - /* 310 */ SyscallDesc("syslog", unimplementedFunc), - /* 311 */ SyscallDesc("reboot", unimplementedFunc), - /* 312 */ SyscallDesc("clone", unimplementedFunc), - /* 313 */ SyscallDesc("uselib", unimplementedFunc), - /* 314 */ SyscallDesc("mlock", unimplementedFunc), - /* 315 */ SyscallDesc("munlock", unimplementedFunc), - /* 316 */ SyscallDesc("mlockall", unimplementedFunc), - /* 317 */ SyscallDesc("munlockall", unimplementedFunc), - /* 318 */ SyscallDesc("sysinfo", unimplementedFunc), - /* 319 */ SyscallDesc("_sysctl", unimplementedFunc), - /* 320 */ SyscallDesc("was sys_idle", unimplementedFunc), - /* 321 */ SyscallDesc("oldumount", unimplementedFunc), - /* 322 */ SyscallDesc("swapon", unimplementedFunc), - /* 323 */ SyscallDesc("times", ignoreFunc), - /* 324 */ SyscallDesc("personality", unimplementedFunc), - /* 325 */ SyscallDesc("setfsuid", unimplementedFunc), - /* 326 */ SyscallDesc("setfsgid", unimplementedFunc), - /* 327 */ SyscallDesc("ustat", unimplementedFunc), - /* 328 */ SyscallDesc("statfs", unimplementedFunc), - /* 329 */ SyscallDesc("fstatfs", unimplementedFunc), - /* 330 */ SyscallDesc("sched_setparam", unimplementedFunc), - /* 331 */ SyscallDesc("sched_getparam", unimplementedFunc), - /* 332 */ SyscallDesc("sched_setscheduler", unimplementedFunc), - /* 333 */ SyscallDesc("sched_getscheduler", unimplementedFunc), - /* 334 */ SyscallDesc("sched_yield", unimplementedFunc), - /* 335 */ SyscallDesc("sched_get_priority_max", unimplementedFunc), - /* 336 */ SyscallDesc("sched_get_priority_min", unimplementedFunc), - /* 337 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc), - /* 338 */ SyscallDesc("afs_syscall", unimplementedFunc), - /* 339 */ SyscallDesc("uname", unameFunc), - /* 340 */ SyscallDesc("nanosleep", unimplementedFunc), - /* 341 */ SyscallDesc("mremap", unimplementedFunc), - /* 342 */ SyscallDesc("nfsservctl", unimplementedFunc), - /* 343 */ SyscallDesc("setresuid", unimplementedFunc), - /* 344 */ SyscallDesc("getresuid", unimplementedFunc), - /* 345 */ SyscallDesc("pciconfig_read", unimplementedFunc), - /* 346 */ SyscallDesc("pciconfig_write", unimplementedFunc), - /* 347 */ SyscallDesc("query_module", unimplementedFunc), - /* 348 */ SyscallDesc("prctl", unimplementedFunc), - /* 349 */ SyscallDesc("pread", unimplementedFunc), - /* 350 */ SyscallDesc("pwrite", unimplementedFunc), - /* 351 */ SyscallDesc("rt_sigreturn", unimplementedFunc), - /* 352 */ SyscallDesc("rt_sigaction", ignoreFunc), - /* 353 */ SyscallDesc("rt_sigprocmask", unimplementedFunc), - /* 354 */ SyscallDesc("rt_sigpending", unimplementedFunc), - /* 355 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc), - /* 356 */ SyscallDesc("rt_sigqueueinfo", unimplementedFunc), - /* 357 */ SyscallDesc("rt_sigsuspend", unimplementedFunc), - /* 358 */ SyscallDesc("select", unimplementedFunc), - /* 359 */ SyscallDesc("gettimeofday", gettimeofdayFunc<Linux>), - /* 360 */ SyscallDesc("settimeofday", unimplementedFunc), - /* 361 */ SyscallDesc("getitimer", unimplementedFunc), - /* 362 */ SyscallDesc("setitimer", unimplementedFunc), - /* 363 */ SyscallDesc("utimes", utimesFunc<Linux>), - /* 364 */ SyscallDesc("getrusage", getrusageFunc<Linux>), - /* 365 */ SyscallDesc("wait4", unimplementedFunc), - /* 366 */ SyscallDesc("adjtimex", unimplementedFunc), - /* 367 */ SyscallDesc("getcwd", unimplementedFunc), - /* 368 */ SyscallDesc("capget", unimplementedFunc), - /* 369 */ SyscallDesc("capset", unimplementedFunc), - /* 370 */ SyscallDesc("sendfile", unimplementedFunc), - /* 371 */ SyscallDesc("setresgid", unimplementedFunc), - /* 372 */ SyscallDesc("getresgid", unimplementedFunc), - /* 373 */ SyscallDesc("dipc", unimplementedFunc), - /* 374 */ SyscallDesc("pivot_root", unimplementedFunc), - /* 375 */ SyscallDesc("mincore", unimplementedFunc), - /* 376 */ SyscallDesc("pciconfig_iobase", unimplementedFunc), - /* 377 */ SyscallDesc("getdents64", unimplementedFunc), - /* 378 */ SyscallDesc("gettid", unimplementedFunc), - /* 379 */ SyscallDesc("readahead", unimplementedFunc), - /* 380 */ SyscallDesc("security", unimplementedFunc), - /* 381 */ SyscallDesc("tkill", unimplementedFunc), - /* 382 */ SyscallDesc("setxattr", unimplementedFunc), - /* 383 */ SyscallDesc("lsetxattr", unimplementedFunc), - /* 384 */ SyscallDesc("fsetxattr", unimplementedFunc), - /* 385 */ SyscallDesc("getxattr", unimplementedFunc), - /* 386 */ SyscallDesc("lgetxattr", unimplementedFunc), - /* 387 */ SyscallDesc("fgetxattr", unimplementedFunc), - /* 388 */ SyscallDesc("listxattr", unimplementedFunc), - /* 389 */ SyscallDesc("llistxattr", unimplementedFunc), - /* 390 */ SyscallDesc("flistxattr", unimplementedFunc), - /* 391 */ SyscallDesc("removexattr", unimplementedFunc), - /* 392 */ SyscallDesc("lremovexattr", unimplementedFunc), - /* 393 */ SyscallDesc("fremovexattr", unimplementedFunc), - /* 394 */ SyscallDesc("futex", unimplementedFunc), - /* 395 */ SyscallDesc("sched_setaffinity", unimplementedFunc), - /* 396 */ SyscallDesc("sched_getaffinity", unimplementedFunc), - /* 397 */ SyscallDesc("tuxcall", unimplementedFunc), - /* 398 */ SyscallDesc("io_setup", unimplementedFunc), - /* 399 */ SyscallDesc("io_destroy", unimplementedFunc), - /* 400 */ SyscallDesc("io_getevents", unimplementedFunc), - /* 401 */ SyscallDesc("io_submit", unimplementedFunc), - /* 402 */ SyscallDesc("io_cancel", unimplementedFunc), - /* 403 */ SyscallDesc("unknown #403", unimplementedFunc), - /* 404 */ SyscallDesc("unknown #404", unimplementedFunc), - /* 405 */ SyscallDesc("exit_group", exitFunc), // exit all threads... - /* 406 */ SyscallDesc("lookup_dcookie", unimplementedFunc), - /* 407 */ SyscallDesc("sys_epoll_create", unimplementedFunc), - /* 408 */ SyscallDesc("sys_epoll_ctl", unimplementedFunc), - /* 409 */ SyscallDesc("sys_epoll_wait", unimplementedFunc), - /* 410 */ SyscallDesc("remap_file_pages", unimplementedFunc), - /* 411 */ SyscallDesc("set_tid_address", unimplementedFunc), - /* 412 */ SyscallDesc("restart_syscall", unimplementedFunc), - /* 413 */ SyscallDesc("fadvise64", unimplementedFunc), - /* 414 */ SyscallDesc("timer_create", unimplementedFunc), - /* 415 */ SyscallDesc("timer_settime", unimplementedFunc), - /* 416 */ SyscallDesc("timer_gettime", unimplementedFunc), - /* 417 */ SyscallDesc("timer_getoverrun", unimplementedFunc), - /* 418 */ SyscallDesc("timer_delete", unimplementedFunc), - /* 419 */ SyscallDesc("clock_settime", unimplementedFunc), - /* 420 */ SyscallDesc("clock_gettime", unimplementedFunc), - /* 421 */ SyscallDesc("clock_getres", unimplementedFunc), - /* 422 */ SyscallDesc("clock_nanosleep", unimplementedFunc), - /* 423 */ SyscallDesc("semtimedop", unimplementedFunc), - /* 424 */ SyscallDesc("tgkill", unimplementedFunc), - /* 425 */ SyscallDesc("stat64", unimplementedFunc), - /* 426 */ SyscallDesc("lstat64", lstat64Func<Linux>), - /* 427 */ SyscallDesc("fstat64", fstat64Func<Linux>), - /* 428 */ SyscallDesc("vserver", unimplementedFunc), - /* 429 */ SyscallDesc("mbind", unimplementedFunc), - /* 430 */ SyscallDesc("get_mempolicy", unimplementedFunc), - /* 431 */ SyscallDesc("set_mempolicy", unimplementedFunc), - /* 432 */ SyscallDesc("mq_open", unimplementedFunc), - /* 433 */ SyscallDesc("mq_unlink", unimplementedFunc), - /* 434 */ SyscallDesc("mq_timedsend", unimplementedFunc), - /* 435 */ SyscallDesc("mq_timedreceive", unimplementedFunc), - /* 436 */ SyscallDesc("mq_notify", unimplementedFunc), - /* 437 */ SyscallDesc("mq_getsetattr", unimplementedFunc), - /* 438 */ SyscallDesc("waitid", unimplementedFunc), - /* 439 */ SyscallDesc("add_key", unimplementedFunc), - /* 440 */ SyscallDesc("request_key", unimplementedFunc), - /* 441 */ SyscallDesc("keyctl", unimplementedFunc) -}; - -MipsLinuxProcess::MipsLinuxProcess(const std::string &name, - ObjectFile *objFile, - int stdin_fd, - int stdout_fd, - int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp) - : LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp), - Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) -{ - init_regs->intRegFile[0] = 0; -} - - - -SyscallDesc* -MipsLinuxProcess::getDesc(int callnum) -{ - if (callnum < 0 || callnum > Num_Syscall_Descs) - return NULL; - return &syscallDescs[callnum]; -} diff --git a/arch/mips/process.cc b/arch/mips/process.cc index 6de44fe9f..7831551be 100644 --- a/arch/mips/process.cc +++ b/arch/mips/process.cc @@ -26,22 +26,37 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include "arch/mips/isa_traits.hh" #include "arch/mips/process.hh" +#include "arch/mips/linux/process.hh" +#include "base/loader/object_file.hh" +#include "base/misc.hh" +#include "cpu/exec_context.hh" +#include "sim/builder.hh" +#include "sim/system.hh" + +using namespace std; +using namespace MipsISA; -namespace MipsISA -{ -LiveProcess * -createProcess(const string &nm, ObjectFile * objFile, - int stdin_fd, int stdout_fd, int stderr_fd, - vector<string> &argv, vector<string> &envp) +MipsLiveProcess * +MipsLiveProcess::create(const std::string &nm, System *system, int stdin_fd, + int stdout_fd, int stderr_fd, std::string executable, + std::vector<std::string> &argv, std::vector<std::string> &envp) { - LiveProcess * process = NULL; - if (objFile->getArch() != ObjectFile::MIPS) + MipsLiveProcess *process = NULL; + + ObjectFile *objFile = createObjectFile(executable); + if (objFile == NULL) { + fatal("Can't load object file %s", executable); + } + + + if (objFile->getArch() != ObjectFile::Mips) fatal("Object file does not match architecture."); switch (objFile->getOpSys()) { case ObjectFile::Linux: - process = new MipsLinuxProcess(nm, objFile, + process = new MipsLinuxProcess(nm, objFile, system, stdin_fd, stdout_fd, stderr_fd, argv, envp); break; @@ -49,8 +64,98 @@ createProcess(const string &nm, ObjectFile * objFile, default: fatal("Unknown/unsupported operating system."); } + + if (process == NULL) + fatal("Unknown error creating process object."); return process; } -} // namespace MipsISA +MipsLiveProcess::MipsLiveProcess(const std::string &nm, ObjectFile *objFile, + System *_system, int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, std::vector<std::string> &envp) + : LiveProcess(nm, objFile, _system, stdin_fd, stdout_fd, stderr_fd, + argv, envp) +{ + + // XXX all the below need to be updated for SPARC - Ali + brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); + brk_point = roundUp(brk_point, VMPageSize); + + // Set up stack. On Alpha, stack goes below text section. This + // code should get moved to some architecture-specific spot. + stack_base = objFile->textBase() - (409600+4096); + + // Set up region for mmaps. Tru64 seems to start just above 0 and + // grow up from there. + mmap_start = mmap_end = 0x10000; + + // Set pointer for next thread stack. Reserve 8M for main stack. + next_thread_stack_base = stack_base - (8 * 1024 * 1024); + +} + +void +MipsLiveProcess::startup() +{ + argsInit(MachineBytes, VMPageSize); +} + + + + +BEGIN_DECLARE_SIM_OBJECT_PARAMS(MipsLiveProcess) + + VectorParam<string> cmd; + Param<string> executable; + Param<string> input; + Param<string> output; + VectorParam<string> env; + SimObjectParam<System *> system; + +END_DECLARE_SIM_OBJECT_PARAMS(MipsLiveProcess) + + +BEGIN_INIT_SIM_OBJECT_PARAMS(MipsLiveProcess) + + INIT_PARAM(cmd, "command line (executable plus arguments)"), + INIT_PARAM(executable, "executable (overrides cmd[0] if set)"), + INIT_PARAM(input, "filename for stdin (dflt: use sim stdin)"), + INIT_PARAM(output, "filename for stdout/stderr (dflt: use sim stdout)"), + INIT_PARAM(env, "environment settings"), + INIT_PARAM(system, "system") + +END_INIT_SIM_OBJECT_PARAMS(MipsLiveProcess) + + +CREATE_SIM_OBJECT(MipsLiveProcess) +{ + string in = input; + string out = output; + + // initialize file descriptors to default: same as simulator + int stdin_fd, stdout_fd, stderr_fd; + + if (in == "stdin" || in == "cin") + stdin_fd = STDIN_FILENO; + else + stdin_fd = Process::openInputFile(input); + + if (out == "stdout" || out == "cout") + stdout_fd = STDOUT_FILENO; + else if (out == "stderr" || out == "cerr") + stdout_fd = STDERR_FILENO; + else + stdout_fd = Process::openOutputFile(out); + + stderr_fd = (stdout_fd != STDOUT_FILENO) ? stdout_fd : STDERR_FILENO; + + return MipsLiveProcess::create(getInstanceName(), system, + stdin_fd, stdout_fd, stderr_fd, + (string)executable == "" ? cmd[0] : executable, + cmd, env); +} + + +REGISTER_SIM_OBJECT("MipsLiveProcess", MipsLiveProcess) + diff --git a/arch/mips/process.hh b/arch/mips/process.hh index ab4323107..2a13dc955 100644 --- a/arch/mips/process.hh +++ b/arch/mips/process.hh @@ -29,17 +29,36 @@ #ifndef __MIPS_PROCESS_HH__ #define __MIPS_PROCESS_HH__ -#include "arch/mips/linux_process.hh" -#include "base/loader/object_file.hh" +#include <string> +#include <vector> +#include "sim/process.hh" -namespace MipsISA +class LiveProcess; +class ObjectFile; +class System; + +class MipsLiveProcess : public LiveProcess { + protected: + MipsLiveProcess(const std::string &nm, ObjectFile *objFile, + System *_system, int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp); + + void startup(); + + public: + // this function is used to create the LiveProcess object, since + // we can't tell which subclass of LiveProcess to use until we + // open and look at the object file. + static MipsLiveProcess *create(const std::string &nm, + System *_system, + int stdin_fd, int stdout_fd, int stderr_fd, + std::string executable, + std::vector<std::string> &argv, + std::vector<std::string> &envp); -LiveProcess * -createProcess(const string &nm, ObjectFile * objFile, - int stdin_fd, int stdout_fd, int stderr_fd, - vector<string> &argv, vector<string> &envp); +}; -} // namespace MipsISA #endif // __MIPS_PROCESS_HH__ diff --git a/arch/mips/regfile/float_regfile.hh b/arch/mips/regfile/float_regfile.hh new file mode 100644 index 000000000..15c6f97f4 --- /dev/null +++ b/arch/mips/regfile/float_regfile.hh @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_MIPS_FLOAT_REGFILE_HH__ +#define __ARCH_MIPS_FLOAT_REGFILE_HH__ + +#include "arch/mips/types.hh" +#include "arch/mips/constants.hh" +#include "base/misc.hh" +#include "config/full_system.hh" +#include "sim/byteswap.hh" +#include "sim/faults.hh" +#include "sim/host.hh" + +class Checkpoint; +class ExecContext; +class Regfile; + +namespace MipsISA +{ + class FloatRegFile + { + protected: + FloatReg32 regs[NumFloatRegs]; + + public: + + void clear() + { + bzero(regs, sizeof(regs)); + } + + double readReg(int floatReg, int width) + { + switch(width) + { + case SingleWidth: + void *float_ptr = ®s[floatReg]; + return *(float *) float_ptr; + + case DoubleWidth: + uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg]; + void *double_ptr = &double_val; + return *(double *) double_ptr; + + default: + panic("Attempted to read a %d bit floating point register!", width); + } + } + + FloatRegBits readRegBits(int floatReg, int width) + { + if (floatReg < NumFloatArchRegs - 1) { + switch(width) + { + case SingleWidth: + return regs[floatReg]; + + case DoubleWidth: + return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg]; + + default: + panic("Attempted to read a %d bit floating point register!", width); + } + } else { + if (width > SingleWidth) + assert("Control Regs are only 32 bits wide"); + + return regs[floatReg]; + } + } + + Fault setReg(int floatReg, const FloatReg &val, int width) + { + + switch(width) + { + case SingleWidth: + float temp = val; + void *float_ptr = &temp; + regs[floatReg] = *(FloatReg32 *) float_ptr; + break; + + case DoubleWidth: + const void *double_ptr = &val; + FloatReg64 temp_double = *(FloatReg64 *) double_ptr; + regs[floatReg + 1] = temp_double >> 32; + regs[floatReg] = temp_double; + break; + + default: + panic("Attempted to read a %d bit floating point register!", width); + } + + return NoFault; + } + + Fault setRegBits(int floatReg, const FloatRegBits &val, int width) + { + using namespace std; + + switch(width) + { + case SingleWidth: + regs[floatReg] = val; + break; + + case DoubleWidth: + regs[floatReg + 1] = val >> 32; + regs[floatReg] = val; + break; + + default: + panic("Attempted to read a %d bit floating point register!", width); + } + return NoFault; + } + + void serialize(std::ostream &os); + + void unserialize(Checkpoint *cp, const std::string §ion); + }; + + enum MiscFloatRegNums { + FIR = NumFloatArchRegs, + FCCR, + FEXR, + FENR, + FCSR + }; + +} // namespace MipsISA + +#endif diff --git a/arch/mips/regfile/int_regfile.hh b/arch/mips/regfile/int_regfile.hh new file mode 100644 index 000000000..3cd87734d --- /dev/null +++ b/arch/mips/regfile/int_regfile.hh @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_MIPS_INT_REGFILE_HH__ +#define __ARCH_MIPS_INT_REGFILE_HH__ + +#include "arch/mips/types.hh" +#include "arch/mips/constants.hh" +#include "base/misc.hh" +#include "sim/faults.hh" + +class Checkpoint; +class ExecContext; +class Regfile; + +namespace MipsISA +{ + class IntRegFile + { + protected: + IntReg regs[NumIntRegs]; + + public: + IntReg readReg(int intReg) + { + return regs[intReg]; + } + + Fault setReg(int intReg, const IntReg &val) + { + regs[intReg] = val; + return NoFault; + } + + void serialize(std::ostream &os); + + void unserialize(Checkpoint *cp, const std::string §ion); + + }; + + enum MiscIntRegNums { + HI = NumIntArchRegs, + LO + }; + +} // namespace MipsISA + +#endif diff --git a/arch/mips/regfile/misc_regfile.hh b/arch/mips/regfile/misc_regfile.hh new file mode 100644 index 000000000..9f054e5f7 --- /dev/null +++ b/arch/mips/regfile/misc_regfile.hh @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_MIPS_MISC_REGFILE_HH__ +#define __ARCH_MIPS_MISC_REGFILE_HH__ + +#include "arch/mips/types.hh" +#include "arch/mips/constants.hh" +#include "sim/faults.hh" + +class Checkpoint; +class ExecContext; +class Regfile; + +namespace MipsISA +{ + class MiscRegFile { + + protected: + uint64_t fpcr; // floating point condition codes + uint64_t uniq; // process-unique register + bool lock_flag; // lock flag for LL/SC + Addr lock_addr; // lock address for LL/SC + + MiscReg miscRegFile[NumMiscRegs]; + + public: + //These functions should be removed once the simplescalar cpu model + //has been replaced. + int getInstAsid(); + int getDataAsid(); + + void copyMiscRegs(ExecContext *xc); + + MiscReg readReg(int misc_reg) + { + return miscRegFile[misc_reg]; + } + + MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc) + { + return miscRegFile[misc_reg]; + } + + Fault setReg(int misc_reg, const MiscReg &val) + { + miscRegFile[misc_reg] = val; return NoFault; + } + + Fault setRegWithEffect(int misc_reg, const MiscReg &val, + ExecContext *xc) + { + miscRegFile[misc_reg] = val; return NoFault; + } + +#if FULL_SYSTEM + void clearIprs() { } + + protected: + InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs + + private: + MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { } + + Fault setIpr(int idx, uint64_t val, ExecContext *xc) { } +#endif + friend class RegFile; + }; +} // namespace MipsISA + +#endif diff --git a/arch/mips/regfile/regfile.hh b/arch/mips/regfile/regfile.hh new file mode 100644 index 000000000..e77571b33 --- /dev/null +++ b/arch/mips/regfile/regfile.hh @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_MIPS_REGFILE_HH__ +#define __ARCH_MIPS_REGFILE_HH__ + +#include "arch/mips/types.hh" +#include "arch/mips/constants.hh" +#include "arch/mips/regfile/int_regfile.hh" +#include "arch/mips/regfile/float_regfile.hh" +#include "arch/mips/regfile/misc_regfile.hh" +#include "sim/faults.hh" + +class Checkpoint; +class ExecContext; + +namespace MipsISA +{ + class RegFile { + protected: + IntRegFile intRegFile; // (signed) integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegFile; // control register file + + public: + + void clear() + { + bzero(&intRegFile, sizeof(intRegFile)); + bzero(&floatRegFile, sizeof(floatRegFile)); + bzero(&miscRegFile, sizeof(miscRegFile)); + } + + MiscReg readMiscReg(int miscReg) + { + return miscRegFile.readReg(miscReg); + } + + MiscReg readMiscRegWithEffect(int miscReg, + Fault &fault, ExecContext *xc) + { + fault = NoFault; + return miscRegFile.readRegWithEffect(miscReg, fault, xc); + } + + Fault setMiscReg(int miscReg, const MiscReg &val) + { + return miscRegFile.setReg(miscReg, val); + } + + Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, + ExecContext * xc) + { + return miscRegFile.setRegWithEffect(miscReg, val, xc); + } + + FloatReg readFloatReg(int floatReg) + { + return floatRegFile.readReg(floatReg,SingleWidth); + } + + FloatReg readFloatReg(int floatReg, int width) + { + return floatRegFile.readReg(floatReg,width); + } + + FloatRegBits readFloatRegBits(int floatReg) + { + return floatRegFile.readRegBits(floatReg,SingleWidth); + } + + FloatRegBits readFloatRegBits(int floatReg, int width) + { + return floatRegFile.readRegBits(floatReg,width); + } + + Fault setFloatReg(int floatReg, const FloatReg &val) + { + return floatRegFile.setReg(floatReg, val, SingleWidth); + } + + Fault setFloatReg(int floatReg, const FloatReg &val, int width) + { + return floatRegFile.setReg(floatReg, val, width); + } + + Fault setFloatRegBits(int floatReg, const FloatRegBits &val) + { + return floatRegFile.setRegBits(floatReg, val, SingleWidth); + } + + Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width) + { + return floatRegFile.setRegBits(floatReg, val, width); + } + + IntReg readIntReg(int intReg) + { + return intRegFile.readReg(intReg); + } + + Fault setIntReg(int intReg, const IntReg &val) + { + return intRegFile.setReg(intReg, val); + } + protected: + + Addr pc; // program counter + Addr npc; // next-cycle program counter + Addr nnpc; // next-next-cycle program counter + // used to implement branch delay slot + // not real register + public: + Addr readPC() + { + return pc; + } + + void setPC(Addr val) + { + pc = val; + } + + Addr readNextPC() + { + return npc; + } + + void setNextPC(Addr val) + { + npc = val; + } + + Addr readNextNPC() + { + return nnpc; + } + + void setNextNPC(Addr val) + { + nnpc = val; + } + + +#if FULL_SYSTEM + IntReg palregs[NumIntRegs]; // PAL shadow registers + InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs + int intrflag; // interrupt flag + bool pal_shadow; // using pal_shadow registers + inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } + inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } +#endif // FULL_SYSTEM + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); + + typedef int ContextParam; + typedef int ContextVal; + + void changeContext(ContextParam param, ContextVal val) + { + } + }; + + void copyRegs(ExecContext *src, ExecContext *dest); + + void copyMiscRegs(ExecContext *src, ExecContext *dest); + +#if FULL_SYSTEM + void copyIprs(ExecContext *src, ExecContext *dest); +#endif +} // namespace MipsISA + +#endif diff --git a/arch/mips/types.hh b/arch/mips/types.hh new file mode 100644 index 000000000..4d5fb3456 --- /dev/null +++ b/arch/mips/types.hh @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_MIPS_TYPES_HH__ +#define __ARCH_MIPS_TYPES_HH__ + +#include "sim/host.hh" + +namespace MipsISA +{ + typedef uint32_t MachInst; + typedef uint64_t ExtMachInst; + typedef uint8_t RegIndex; + + typedef uint32_t IntReg; + + // floating point register file entry type + typedef double FloatReg; + typedef uint32_t FloatReg32; + typedef uint64_t FloatReg64; + typedef uint64_t FloatRegBits; + + // cop-0/cop-1 system control register + typedef uint64_t MiscReg; + typedef uint64_t InternalProcReg; + + typedef union { + IntReg intreg; + FloatReg fpreg; + MiscReg ctrlreg; + } AnyReg; + + //used in FP convert & round function + enum ConvertType{ + SINGLE_TO_DOUBLE, + SINGLE_TO_WORD, + SINGLE_TO_LONG, + + DOUBLE_TO_SINGLE, + DOUBLE_TO_WORD, + DOUBLE_TO_LONG, + + LONG_TO_SINGLE, + LONG_TO_DOUBLE, + LONG_TO_WORD, + LONG_TO_PS, + + WORD_TO_SINGLE, + WORD_TO_DOUBLE, + WORD_TO_LONG, + WORD_TO_PS, + + PL_TO_SINGLE, + PU_TO_SINGLE + }; + + //used in FP convert & round function + enum RoundMode{ + RND_ZERO, + RND_DOWN, + RND_UP, + RND_NEAREST + }; + +} // namespace MipsISA + +#endif diff --git a/arch/mips/utility.hh b/arch/mips/utility.hh new file mode 100644 index 000000000..b213a9f24 --- /dev/null +++ b/arch/mips/utility.hh @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_MIPS_UTILITY_HH__ +#define __ARCH_MIPS_UTILITY_HH__ + +#include "arch/mips/types.hh" +#include "arch/mips/constants.hh" +#include "base/misc.hh" +#include "sim/host.hh" + +namespace MipsISA { + +}; + +#endif |