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-rw-r--r--arch/mips/isa/bitfields.isa51
-rw-r--r--arch/mips/isa/decoder.isa754
-rw-r--r--arch/mips/isa/formats.isa22
-rw-r--r--arch/mips/isa/formats/basic.isa65
-rw-r--r--arch/mips/isa/formats/branch.isa66
-rw-r--r--arch/mips/isa/formats/fp.isa110
-rw-r--r--arch/mips/isa/formats/int.isa70
-rw-r--r--arch/mips/isa/formats/mem.isa78
-rw-r--r--arch/mips/isa/formats/noop.isa47
-rw-r--r--arch/mips/isa/formats/tlbop.isa53
-rw-r--r--arch/mips/isa/formats/trap.isa53
-rw-r--r--arch/mips/isa/includes.isa40
-rw-r--r--arch/mips/isa/main.isa52
-rw-r--r--arch/mips/isa/operands.isa36
-rw-r--r--arch/mips/isa_traits.cc58
-rw-r--r--arch/mips/isa_traits.hh532
16 files changed, 2087 insertions, 0 deletions
diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa
new file mode 100644
index 000000000..94a8a6467
--- /dev/null
+++ b/arch/mips/isa/bitfields.isa
@@ -0,0 +1,51 @@
+////////////////////////////////////////////////////////////////////
+//
+// Bitfield definitions.
+//
+
+def bitfield OPCODE_HI <31:29>;
+def bitfield OPCODE_LO <28:26>;
+
+def bitfield FUNCTION_HI < 5: 3>;
+def bitfield FUNCTION_LO < 2: 0>;
+
+// Integer operate format
+def bitfield RT <20:16>;
+def bitfield RT_HI <20:19>;
+def bitfield RT_LO <18:16>;
+
+def bitfield RS <25:21>;
+def bitfield RS_HI <25:24>;
+def bitfield RS_LO <23:21>;
+
+def bitfield RD <15:11>;
+
+def bitfield INTIMM <15: 0>; // integer immediate (literal)
+
+// Floating-point operate format
+def bitfield FMT <25:21>;
+def bitfield FT <20:16>;
+def bitfield FS <15:11>;
+def bitfield FD <10:6>;
+
+def bitfield MOVCI <16:16>;
+def bitfield MOVCF <16:16>;
+def bitfield SRL <21:21>;
+def bitfield SRLV < 6: 6>;
+def bitfield SA <10: 6>;
+
+// Interrupts
+def bitfield SC < 5: 5>;
+
+// Branch format
+def bitfield OFFSET <15: 0>; // displacement
+
+// Memory-format jumps
+def bitfield JMPTARG <25: 0>;
+def bitfield JMPHINT <10: 6>;
+
+def bitfield SYSCALLCODE <25: 6>;
+def bitfield TRAPCODE <15:13>;
+
+// M5 instructions
+def bitfield M5FUNC <7:0>;
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
new file mode 100644
index 000000000..acd00e70d
--- /dev/null
+++ b/arch/mips/isa/decoder.isa
@@ -0,0 +1,754 @@
+////////////////////////////////////////////////////////////////////
+//
+// The actual MIPS32 ISA decoder
+// -----------------------------
+// The following instructions are specified in the MIPS32 ISA
+// Specification. Decoding closely follows the style specified
+// in the MIPS32 ISAthe specification document starting with Table
+// A-2 (document available @ www.mips.com)
+//
+//@todo: Distinguish "unknown/future" use insts from "reserved"
+// ones
+decode OPCODE_HI default FailUnimpl::unknown() {
+
+ // Derived From ... Table A-2 MIPS32 ISA Manual
+ 0x0: decode OPCODE_LO default FailUnimpl::reserved(){
+
+ 0x0: decode FUNCTION_HI {
+ 0x0: decode FUNCTION_LO {
+ 0x1: decode MOVCI {
+ format BasicOp {
+ 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}});
+ 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}});
+ }
+ }
+
+ format BasicOp {
+
+ //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
+ //are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
+
+ 0x0: sll({{ Rd = Rt.uw << SA; }});
+
+ 0x2: decode SRL {
+ 0: srl({{ Rd = Rt.uw >> SA; }});
+
+ //Hardcoded assuming 32-bit ISA, probably need parameter here
+ 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
+ }
+
+ 0x3: sra({{ Rd = Rt.sw >> SA; }});
+
+ 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
+
+ 0x6: decode SRLV {
+ 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
+
+ //Hardcoded assuming 32-bit ISA, probably need parameter here
+ 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
+ }
+
+ 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
+ }
+ }
+
+ 0x1: decode FUNCTION_LO {
+
+ //Table A-3 Note: "Specific encodings of the hint field are used
+ //to distinguish JR from JR.HB and JALR from JALR.HB"
+ format Jump {
+ 0x0: jr(IsReturn);
+ 0x1: jalr(IsCall,IsReturn);
+ }
+
+ format BasicOp {
+ 0x2: movz({{ if (Rt == 0) Rd = Rs; }});
+ 0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+ }
+
+ format Trap {
+ 0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
+ 0x5: break({{ }});
+ 0x7: sync({{ }});
+ }
+ }
+
+ 0x2: decode FUNCTION_LO {
+ format BasicOp {
+ 0x0: mfhi({{ Rd = xc->miscRegs.hi; }});
+ 0x1: mthi({{ xc->miscRegs.hi = Rs; }});
+ 0x2: mflo({{ Rd = xc->miscRegs.lo; }});
+ 0x3: mtlo({{ xc->miscRegs.lo = Rs; }});
+ }
+ };
+
+ 0x3: decode FUNCTION_LO {
+ format IntOp {
+ 0x0: mult({{
+ INT64 temp1 = Rs.sw * Rt.sw;
+ xc->miscRegs.hi->temp1<63:32>;
+ xc->miscRegs.lo->temp1<31:0>
+ }});
+
+ 0x1: multu({{
+ INT64 temp1 = Rs.uw * Rt.uw;
+ xc->miscRegs.hi->temp1<63:32>;
+ xc->miscRegs.lo->temp1<31:0>
+ Rd.sw = Rs.uw * Rt.uw;
+ }});
+
+ 0x2: div({{
+ xc->miscRegs.hi = Rs.sw % Rt.sw;
+ xc->miscRegs.lo = Rs.sw / Rt.sw;
+ }});
+
+ 0x3: divu({{
+ xc->miscRegs.hi = Rs.uw % Rt.uw;
+ xc->miscRegs.lo = Rs.uw / Rt.uw;
+ }});
+ }
+ };
+
+ 0x4: decode FUNCTION_LO {
+ format IntOp {
+ 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}});
+ 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}});
+ 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}});
+ 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}});
+ 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}});
+ 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}});
+ 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}});
+ 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}});
+ }
+ }
+
+ 0x5: decode FUNCTION_LO {
+ format IntOp{
+ 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
+ 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
+ }
+ };
+
+ 0x6: decode FUNCTION_LO {
+ format Trap {
+ 0x0: tge({{ }});
+ 0x1: tgeu({{ }});
+ 0x2: tlt({{ }});
+ 0x3: tltu({{ }});
+ 0x4: teq({{ }});
+ 0x6: tne({{ }});
+ }
+ }
+ }
+
+ 0x1: decode REGIMM_HI {
+ 0x0: decode REGIMM_LO {
+ format Branch {
+ 0x0: bltz({{ cond = (Rs.sq < 0); }});
+ 0x1: bgez({{ cond = (Rs.sq >= 0); }});
+
+ //MIPS obsolete instructions
+ 0x2: bltzl({{ cond = (Rs.sq < 0); }});
+ 0x3: bgezl({{ cond = (Rs.sq >= 0); }});
+ }
+ }
+
+ 0x1: decode REGIMM_LO {
+ format Trap {
+ 0x0: tgei({{ }});
+ 0x1: tgeiu({{ }});
+ 0x2: tlti({{ }});
+ 0x3: tltiu({{ }});
+ 0x4: teqi({{ }});
+ 0x6: tnei({{ }});
+ }
+ }
+
+ 0x2: decode REGIMM_LO {
+ format Branch {
+ 0x0: bltzal({{ cond = (Rs.sq < 0); }});
+ 0x1: bgezal({{ cond = (Rs.sq >= 0); }});
+
+ //MIPS obsolete instructions
+ 0x2: bltzall({{ cond = (Rs.sq < 0); }});
+ 0x3: bgezall({{ cond = (Rs.sq >= 0); }});
+ }
+ }
+
+ 0x3: decode REGIMM_LO {
+ format Trap {
+ 0x7: synci({{ }});
+ }
+ }
+ }
+
+ format Jump {
+ 0x2: j();
+ 0x3: jal(IsCall);
+ }
+
+ format Branch {
+ 0x4: beq({{ cond = (Rs.sq == 0); }});
+ 0x5: bne({{ cond = (Rs.sq != 0); }});
+ 0x6: blez({{ cond = (Rs.sq <= 0); }});
+ 0x7: bgtz({{ cond = (Rs.sq > 0); }});
+ }
+ };
+
+ 0x1: decode OPCODE_LO default FailUnimpl::reserved(){
+ format IntOp {
+ 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }});
+ 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}});
+ 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }});
+ 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }});
+ 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
+ 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
+ 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
+ 0x7: lui({{ Rt = INTIMM << 16}});
+ };
+ };
+
+ 0x2: decode OPCODE_LO default FailUnimpl::reserved(){
+
+ //Table A-11 MIPS32 COP0 Encoding of rs Field
+ 0x0: decode RS_MSB {
+ 0x0: decode RS {
+
+ format BasicOp {
+ 0x0: mfc0({{
+ //The contents of the coprocessor 0 register specified by the
+ //combination of rd and sel are loaded into general register
+ //rt. Note that not all coprocessor 0 registers support the
+ //sel field. In those instances, the sel field must be zero.
+
+ if (SEL > 0)
+ panic("Can't Handle Cop0 with register select yet\n");
+
+ uint64_t reg_num = Rd.uw;
+
+ Rt = xc->miscRegs.cop0[reg_num];
+ }});
+
+ 0xC: mtc0({{
+ //The contents of the coprocessor 0 register specified by the
+ //combination of rd and sel are loaded into general register
+ //rt. Note that not all coprocessor 0 registers support the
+ //sel field. In those instances, the sel field must be zero.
+
+ if (SEL > 0)
+ panic("Can't Handle Cop0 with register select yet\n");
+
+ uint64_t reg_num = Rd.uw;
+
+ xc->miscRegs.cop0[reg_num] = Rt;
+ }});
+
+ 0xA: rdpgpr({{
+ //Accessing Previous Shadow Set Register Number
+ uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
+ uint64_t reg_num = Rt.uw;
+
+ Rd = xc->shadowIntRegFile[prev][reg_num];
+ }});
+ }
+
+ 0xB: decode SC {
+ format BasicOp {
+ 0x0: di({{
+ //Accessing Coprocessor 0 "Status" Register
+ Rt.sw = xc->miscRegs.cop0[12];
+ xc->miscRegs.cop0[12][INTERRUPT_ENABLE] = 0;
+ }});
+
+ 0x1: ei({{
+ //Accessing Coprocessor 0 "Status" Register
+ Rt.sw = xc->miscRegs.cop0[12];
+ xc->miscRegs.cop0[12][INTERRUPT_ENABLE] = 1;
+ }});
+ }
+ }
+
+ 0xE: BasicOp::wrpgpr({{
+ //Accessing Previous Shadow Set Register Number
+ uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
+ uint64_t reg_num = Rd.uw;
+
+ xc->shadowIntRegFile[prev][reg_num] = Rt;
+ }});
+ }
+
+ //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
+ 0x1: decode FUNCTION {
+ format Trap {
+ 0x01: tlbr({{ }});
+ 0x02: tlbwi({{ }});
+ 0x06: tlbwr({{ }});
+ 0x08: tlbp({{ }});
+ }
+
+ format WarnUnimpl {
+ 0x18: eret({{ }});
+ 0x1F: deret({{ }});
+ 0x20: wait({{ }});
+ }
+ }
+ }
+
+ //Table A-13 MIPS32 COP1 Encoding of rs Field
+ 0x1: decode RS_MSB {
+
+ 0x0: decode RS_HI {
+ 0x0: decode RS_LO {
+ format FloatOp {
+ 0x0: mfc1({{ Rt = Fs<31:0>; }});
+ 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}});
+ 0x3: mfhc1({{ Rt = Fs<63:32>;}});
+ 0x4: mtc1({{ Fs<31:0> = Rt}});
+ 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}});
+ 0x7: mftc1({{ Fs<63:32> = Rt}});
+ }
+ }
+
+ 0x1: decode ND {
+ 0x0: decode TF {
+ format Branch {
+ 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
+ 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
+ }
+ }
+
+ 0x1: decode TF {
+ format Branch {
+ 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
+ 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
+ }
+ }
+ }
+ }
+
+ 0x1: decode RS_HI {
+ 0x2: decode RS_LO {
+
+ //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
+ //(( single-word ))
+ 0x0: decode RS_HI {
+ 0x0: decode RS_LO {
+ format FloatOp {
+ 0x0: add_fmt({{ }});
+ 0x1: sub_fmt({{ }});
+ 0x2: mul_fmt({{ }});
+ 0x3: div_fmt({{ }});
+ 0x4: sqrt_fmt({{ }});
+ 0x5: abs_fmt({{ }});
+ 0x6: mov_fmt({{ }});
+ 0x7: neg_fmt({{ }});
+ }
+ }
+
+ 0x1: decode RS_LO {
+ //only legal for 64 bit
+ format Float64Op {
+ 0x0: round_l({{ }});
+ 0x1: trunc_l({{ }});
+ 0x2: ceil_l({{ }});
+ 0x3: floor_l({{ }});
+ }
+
+ format FloatOp {
+ 0x4: round_w({{ }});
+ 0x5: trunc_w({{ }});
+ 0x6: ceil_w({{ }});
+ 0x7: floor_w({{ }});
+ }
+ }
+
+ 0x2: decode RS_LO {
+ 0x1: decode MOVCF {
+ format FloatOp {
+ 0x0: movf_fmt({{ }});
+ 0x1: movt_fmt({{ }});
+ }
+ }
+
+ format BasicOp {
+ 0x2: movz({{ if (Rt == 0) Rd = Rs; }});
+ 0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+ }
+
+ format Float64Op {
+ 0x2: recip({{ }});
+ 0x3: rsqrt{{ }});
+ }
+ }
+
+ 0x4: decode RS_LO {
+ 0x1: cvt_d({{ }});
+ 0x4: cvt_w({{ }});
+
+ //only legal for 64 bit
+ format Float64Op {
+ 0x5: cvt_l({{ }});
+ 0x6: cvt_ps({{ }});
+ }
+ }
+ }
+
+ //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
+ 0x1: decode RS_HI {
+ 0x0: decode RS_LO {
+ format FloatOp {
+ 0x0: add_fmt({{ }});
+ 0x1: sub_fmt({{ }});
+ 0x2: mul_fmt({{ }});
+ 0x3: div_fmt({{ }});
+ 0x4: sqrt_fmt({{ }});
+ 0x5: abs_fmt({{ }});
+ 0x6: mov_fmt({{ }});
+ 0x7: neg_fmt({{ }});
+ }
+ }
+
+ 0x1: decode RS_LO {
+ //only legal for 64 bit
+ format FloatOp64 {
+ 0x0: round_l({{ }});
+ 0x1: trunc_l({{ }});
+ 0x2: ceil_l({{ }});
+ 0x3: floor_l({{ }});
+ }
+
+ format FloatOp {
+ 0x4: round_w({{ }});
+ 0x5: trunc_w({{ }});
+ 0x6: ceil_w({{ }});
+ 0x7: floor_w({{ }});
+ }
+ }
+
+ 0x2: decode RS_LO {
+ 0x1: decode MOVCF {
+ format FloatOp {
+ 0x0: movf_fmt({{ }});
+ 0x1: movt_fmt({{ }});
+ }
+ }
+
+ format BasicOp {
+ 0x2: movz({{ if (Rt == 0) Rd = Rs; }});
+ 0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+ }
+
+ format FloatOp64 {
+ 0x5: recip({{ }});
+ 0x6: rsqrt{{ }});
+ }
+ }
+
+ 0x4: decode RS_LO {
+ format FloatOp {
+ 0x0: cvt_s({{ }});
+ 0x4: cvt_w({{ }});
+ }
+
+ //only legal for 64 bit
+ format FloatOp64 {
+ 0x5: cvt_l({{ }});
+ }
+ }
+ }
+
+ //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
+ 0x4: decode FUNCTION {
+ format FloatOp {
+ 0x10: cvt_s({{ }});
+ 0x10: cvt_d({{ }});
+ }
+ }
+
+ //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
+ //Note: "1. Format type L is legal only if 64-bit floating point operations
+ //are enabled."
+ 0x5: decode FUNCTION_HI {
+ format FloatOp {
+ 0x10: cvt_s({{ }});
+ 0x11: cvt_d({{ }});
+ }
+ }
+
+ //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
+ //Note: "1. Format type PS is legal only if 64-bit floating point operations
+ //are enabled. "
+ 0x6: decode RS_HI {
+ 0x0: decode RS_LO {
+ format FloatOp64 {
+ 0x0: add_fmt({{ }});
+ 0x1: sub_fmt({{ }});
+ 0x2: mul_fmt({{ }});
+ 0x5: abs_fmt({{ }});
+ 0x6: mov_fmt({{ }});
+ 0x7: neg_fmt({{ }});
+ }
+ }
+
+ 0x2: decode RS_LO {
+ 0x1: decode MOVCF {
+ format FloatOp64 {
+ 0x0: movf_fmt({{ }});
+ 0x1: movt_fmt({{ }});
+ }
+ }
+
+ }
+
+ 0x4: decode RS_LO {
+ 0x0: FloatOp64::cvt_s_pu({{ }});
+ }
+
+ 0x5: decode RS_LO {
+ format FloatOp64 {
+ 0x0: cvt_s_pl({{ }});
+ 0x4: pll_s_pl({{ }});
+ 0x5: plu_s_pl({{ }});
+ 0x6: pul_s_pl({{ }});
+ 0x7: puu_s_pl({{ }});
+ }
+ }
+ }
+ }
+
+ //Table A-19 MIPS32 COP2 Encoding of rs Field
+ 0x2: decode RS_MSB {
+ 0x0: decode RS_HI {
+ 0x0: decode RS_LO {
+ format WarnUnimpl {
+ 0x0: mfc2({{ }});
+ 0x2: cfc2({{ }});
+ 0x3: mfhc2({{ }});
+ 0x4: mtc2({{ }});
+ 0x6: ctc2({{ }});
+ 0x7: mftc2({{ }});
+ }
+ }
+
+ 0x1: decode ND {
+ 0x0: decode TF {
+ format Branch {
+ 0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
+ 0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
+ }
+ }
+
+ 0x1: decode TF {
+ format Branch {
+ 0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
+ 0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
+ }
+ }
+ }
+ }
+ }
+
+ //Table A-20 MIPS64 COP1X Encoding of Function Field 1
+ //Note: "COP1X instructions are legal only if 64-bit floating point
+ //operations are enabled."
+ 0x3: decode FUNCTION_HI {
+ 0x0: decode FUNCTION_LO {
+ format Memory {
+ 0x0: lwxc1({{ }});
+ 0x1: ldxc1({{ }});
+ 0x5: luxc1({{ }});
+ }
+ }
+
+ 0x1: decode FUNCTION_LO {
+ format Memory {
+ 0x0: swxc1({{ }});
+ 0x1: sdxc1({{ }});
+ 0x5: suxc1({{ }});
+ 0x7: prefx({{ }});
+ }
+ }
+
+ format FloatOp {
+ 0x3: alnv_ps({{ }});
+
+ 0x4: decode FUNCTION_LO {
+ 0x0: madd_s({{ }});
+ 0x1: madd_d({{ }});
+ 0x6: madd_ps({{ }});
+ }
+
+ 0x5: decode FUNCTION_LO {
+ 0x0: msub_s({{ }});
+ 0x1: msub_d({{ }});
+ 0x6: msub_ps({{ }});
+ }
+
+ 0x6: decode FUNCTION_LO {
+ 0x0: nmadd_s({{ }});
+ 0x1: nmadd_d({{ }});
+ 0x6: nmadd_ps({{ }});
+ }
+
+ 0x7: decode FUNCTION_LO {
+ 0x0: nmsub_s({{ }});
+ 0x1: nmsub_d({{ }});
+ 0x6: nmsub_ps({{ }});
+ }
+ }
+ }
+
+ //MIPS obsolete instructions
+ format Branch {
+ 0x4: beql({{ cond = (Rs.sq == 0); }});
+ 0x5: bnel({{ cond = (Rs.sq != 0); }});
+ 0x6: blezl({{ cond = (Rs.sq <= 0); }});
+ 0x7: bgtzl({{ cond = (Rs.sq > 0); }});
+ }
+ };
+
+ 0x3: decode OPCODE_LO default FailUnimpl::reserved() {
+
+ //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
+ 0x4: decode FUNCTION_HI {
+
+ 0x0: decode FUNCTION_LO {
+ format IntOp {
+ 0x0: madd({{
+ INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
+ temp1 = temp1 + (Rs.sw * Rt.sw);
+ xc->miscRegs.hi->temp1<63:32>;
+ xc->miscRegs.lo->temp1<31:0>
+ }});
+
+ 0x1: maddu({{
+ INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
+ temp1 = temp1 + (Rs.uw * Rt.uw);
+ xc->miscRegs.hi->temp1<63:32>;
+ xc->miscRegs.lo->temp1<31:0>
+ }});
+
+ 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
+
+ 0x4: msub({{
+ INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
+ temp1 = temp1 - (Rs.sw * Rt.sw);
+ xc->miscRegs.hi->temp1<63:32>;
+ xc->miscRegs.lo->temp1<31:0>
+ }});
+
+ 0x5: msubu({{
+ INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
+ temp1 = temp1 - (Rs.uw * Rt.uw);
+ xc->miscRegs.hi->temp1<63:32>;
+ xc->miscRegs.lo->temp1<31:0>
+ }});
+ }
+ }
+
+ 0x4: decode FUNCTION_LO {
+ format BasicOp {
+ 0x0: clz({{
+ int cnt = 0;
+ int idx = 0;
+ while ( Rs.uw<idx>!= 1) {
+ cnt++;
+ idx--;
+ }
+
+ Rd.uw = cnt;
+ }});
+
+ 0x1: clo({{
+ int cnt = 0;
+ int idx = 0;
+ while ( Rs.uw<idx>!= 0) {
+ cnt++;
+ idx--;
+ }
+
+ Rd.uw = cnt;
+ }});
+ }
+ }
+
+ 0x7: decode FUNCTION_LO {
+ 0x7: WarnUnimpl::sdbbp({{ }});
+ }
+ }
+
+ //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
+ 0x7: decode FUNCTION_HI {
+
+ 0x0: decode FUNCTION_LO {
+ format WarnUnimpl {
+ 0x1: ext({{ }});
+ 0x4: ins({{ }});
+ }
+ }
+
+ //Table A-10 MIPS32 BSHFL Encoding of sa Field
+ 0x4: decode SA {
+ format BasicOp {
+ 0x02: wsbh({{ }});
+ 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}});
+ 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}});
+ }
+ }
+
+ 0x6: decode FUNCTION_LO {
+ 0x7: BasicOp::rdhwr({{ }});
+ }
+ }
+ };
+
+ 0x4: decode OPCODE_LO default FailUnimpl::reserved() {
+ format Memory {
+ 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }});
+ 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }});
+ 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign);
+ 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }});
+ 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }});
+ 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }});
+ 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign);
+ };
+
+ 0x7: FailUnimpl::reserved({{ }});
+ };
+
+ 0x5: decode OPCODE_LO default FailUnimpl::reserved() {
+ format Memory {
+ 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }});
+ 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }});
+ 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
+ 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});
+ 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
+ };
+
+ format WarnUnimpl {
+ 0x4: reserved({{ }});
+ 0x5: reserved({{ }});
+ 0x7: cache({{ }});
+ };
+
+ };
+
+ 0x6: decode OPCODE_LO default FailUnimpl::reserved() {
+ format Memory {
+ 0x0: ll({{ }});
+ 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
+ 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
+ };
+ };
+
+ 0x7: decode OPCODE_LO default FailUnimpl::reserved() {
+ format Memory {
+ 0x0: sc({{ }});
+ 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
+ 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
+ };
+
+ }
+}
+
+
diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa
new file mode 100644
index 000000000..404314c7a
--- /dev/null
+++ b/arch/mips/isa/formats.isa
@@ -0,0 +1,22 @@
+//Include the basic format
+//Templates from this format are used later
+##include "m5/arch/mips/isa_desc/formats/basic.format"
+
+//Include the integerOp and integerOpCc format
+##include "m5/arch/mips/isa_desc/formats/integerop.format"
+
+//Include the floatOp format
+##include "m5/arch/mips/isa_desc/formats/floatop.format"
+
+//Include the mem format
+##include "m5/arch/mips/isa_desc/formats/mem.format"
+
+//Include the trap format
+##include "m5/arch/mips/isa_desc/formats/trap.format"
+
+//Include the branch format
+##include "m5/arch/mips/isa_desc/formats/branch.format"
+
+//Include the noop format
+##include "m5/arch/mips/isa_desc/formats/noop.format"
+
diff --git a/arch/mips/isa/formats/basic.isa b/arch/mips/isa/formats/basic.isa
new file mode 100644
index 000000000..8fba9845a
--- /dev/null
+++ b/arch/mips/isa/formats/basic.isa
@@ -0,0 +1,65 @@
+
+// Declarations for execute() methods.
+def template BasicExecDeclare {{
+ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+// Basic instruction class declaration template.
+def template BasicDeclare {{
+ /**
+ * Static instruction class for "%(mnemonic)s".
+ */
+ class %(class_name)s : public %(base_class)s
+ {
+ public:
+ /// Constructor.
+ %(class_name)s(MachInst machInst);
+ %(BasicExecDeclare)s
+ };
+}};
+
+// Basic instruction class constructor template.
+def template BasicConstructor {{
+ inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+ {
+ %(constructor)s;
+ }
+}};
+
+// Basic instruction class execute method template.
+def template BasicExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = No_Fault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(code)s;
+
+ if(fault == No_Fault)
+ {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
+
+// Basic decode template.
+def template BasicDecode {{
+ return new %(class_name)s(machInst);
+}};
+
+// Basic decode template, passing mnemonic in as string arg to constructor.
+def template BasicDecodeWithMnemonic {{
+ return new %(class_name)s("%(mnemonic)s", machInst);
+}};
+
+// The most basic instruction format... used only for a few misc. insts
+def format BasicOperate(code, *flags) {{
+ iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
new file mode 100644
index 000000000..a565eb71b
--- /dev/null
+++ b/arch/mips/isa/formats/branch.isa
@@ -0,0 +1,66 @@
+////////////////////////////////////////////////////////////////////
+//
+// Branch instructions
+//
+
+output header {{
+ /**
+ * Base class for integer operations.
+ */
+ class Branch : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
+output decoder {{
+ std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return "Disassembly of integer instruction\n";
+ }
+}};
+
+def template BranchExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ //Attempt to execute the instruction
+ try
+ {
+ checkPriv;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(code)s;
+ }
+ //If we have an exception for some reason,
+ //deal with it
+ catch(MipsException except)
+ {
+ //Deal with exception
+ return No_Fault;
+ }
+
+ //Write the resulting state to the execution context
+ %(op_wb)s;
+
+ return No_Fault;
+ }
+}};
+
+def format CondBranch(code) {{
+ code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
+ iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
+ ('IsDirectControl', 'IsCondControl'))
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa
new file mode 100644
index 000000000..707109fc2
--- /dev/null
+++ b/arch/mips/isa/formats/fp.isa
@@ -0,0 +1,110 @@
+////////////////////////////////////////////////////////////////////
+//
+// Floating Point operate instructions
+//
+
+output header {{
+ /**
+ * Base class for integer operations.
+ */
+ class FPOp : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
+output decoder {{
+ std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return "Disassembly of integer instruction\n";
+ }
+}};
+
+def template FPExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ //These are set to constants when the execute method
+ //is generated
+ bool useCc = ;
+ bool checkPriv = ;
+
+ //Attempt to execute the instruction
+ try
+ {
+ checkPriv;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(code)s;
+ }
+ //If we have an exception for some reason,
+ //deal with it
+ catch(MipsException except)
+ {
+ //Deal with exception
+ return No_Fault;
+ }
+
+ //Write the resulting state to the execution context
+ %(op_wb)s;
+ if(useCc)
+ {
+ xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
+ xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
+ xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
+ xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
+ xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
+ xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
+ xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
+ xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
+ }
+ return No_Fault;
+ }
+}};
+
+// Primary format for integer operate instructions:
+def format FPOp(code, *opt_flags) {{
+ orig_code = code
+ cblk = CodeBlock(code)
+ checkPriv = (code.find('checkPriv') != -1)
+ code.replace('checkPriv', '')
+ if checkPriv:
+ code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
+ else:
+ code.replace('checkPriv;', '')
+ for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
+ ('xvValue', '0'), ('xcValue', '0')):
+ code.replace(marker, value)
+ iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+ exec_output = IntegerExecute.subst(iop)
+}};
+
+// Primary format for integer operate instructions:
+def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
+ orig_code = code
+ cblk = CodeBlock(code)
+ checkPriv = (code.find('checkPriv') != -1)
+ code.replace('checkPriv', '')
+ if checkPriv:
+ code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
+ else:
+ code.replace('checkPriv;', '')
+ for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
+ ('xvValue', xvValue), ('xcValue', xcValue)):
+ code.replace(marker, value)
+ iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+ exec_output = IntegerExecute.subst(iop)
+}};
diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa
new file mode 100644
index 000000000..5b8df54e9
--- /dev/null
+++ b/arch/mips/isa/formats/int.isa
@@ -0,0 +1,70 @@
+////////////////////////////////////////////////////////////////////
+//
+// Integer operate instructions
+//
+
+output header {{
+ /**
+ * Base class for integer operations.
+ */
+ class IntOp : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ class IntImmOp : public MipsStaticInst
+ {
+ protected:
+ uint16_t imm;
+
+ /// Constructor
+ IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+}};
+
+output decoder {{
+ std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return "Disassembly of integer instruction\n";
+ }
+
+ std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return "Disassembly of integer immediate instruction\n";
+ }
+}};
+
+// Primary format for integer operate instructions:
+def format IntOp(code, *opt_flags) {{
+ orig_code = code
+ cblk = CodeBlock(code)
+
+ //Figure out if we are creating a IntImmOp or a IntOp
+ strlen = len(name)
+ if ( name[strlen-1] = 'i' or ( name[strlen-2:] = 'iu'))
+ iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
+ else:
+ iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
+
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = OperateNopCheckDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
+
+
diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
new file mode 100644
index 000000000..5ed5237c5
--- /dev/null
+++ b/arch/mips/isa/formats/mem.isa
@@ -0,0 +1,78 @@
+////////////////////////////////////////////////////////////////////
+//
+// Mem instructions
+//
+
+output header {{
+ /**
+ * Base class for integer operations.
+ */
+ class Mem : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
+output decoder {{
+ std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return "Disassembly of integer instruction\n";
+ }
+}};
+
+def template MemExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ //Attempt to execute the instruction
+ try
+ {
+
+ %(op_decl)s;
+ %(op_rd)s;
+ ea_code
+ %(code)s;
+ }
+ //If we have an exception for some reason,
+ //deal with it
+ catch(MipsException except)
+ {
+ //Deal with exception
+ return No_Fault;
+ }
+
+ //Write the resulting state to the execution context
+ %(op_wb)s;
+
+ return No_Fault;
+ }
+}};
+
+// Primary format for integer operate instructions:
+def format Mem(code, *opt_flags) {{
+ orig_code = code
+ cblk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+ exec_output = MemExecute.subst(iop)
+ exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
+}};
+
+def format Cas(code, *opt_flags) {{
+ orig_code = code
+ cblk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+ exec_output = MemExecute.subst(iop)
+ exec_output.replace('ea_code', 'EA = R1;');
+}};
diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa
new file mode 100644
index 000000000..b1ece654d
--- /dev/null
+++ b/arch/mips/isa/formats/noop.isa
@@ -0,0 +1,47 @@
+////////////////////////////////////////////////////////////////////
+//
+// Noop instruction
+//
+
+output header {{
+ /**
+ * Base class for integer operations.
+ */
+ class Noop : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
+output decoder {{
+ std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return "Disassembly of integer instruction\n";
+ }
+}};
+
+def template NoopExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ //Nothing to see here, move along
+ return No_Fault;
+ }
+}};
+
+// Primary format for integer operate instructions:
+def format Noop(code, *opt_flags) {{
+ orig_code = code
+ cblk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+ exec_output = NoopExecute.subst(iop)
+}};
diff --git a/arch/mips/isa/formats/tlbop.isa b/arch/mips/isa/formats/tlbop.isa
new file mode 100644
index 000000000..f5e4076f2
--- /dev/null
+++ b/arch/mips/isa/formats/tlbop.isa
@@ -0,0 +1,53 @@
+////////////////////////////////////////////////////////////////////
+//
+// TlbOp instructions
+//
+
+output header {{
+ /**
+ * Base class for integer operations.
+ */
+ class TlbOp : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ TlbOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
+output decoder {{
+ std::string TlbOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return "Disassembly of integer instruction\n";
+ }
+}};
+
+def template TlbOpExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ //Call into the trap handler with the appropriate fault
+ return No_Fault;
+ }
+
+ //Write the resulting state to the execution context
+ %(op_wb)s;
+
+ return No_Fault;
+ }
+}};
+
+// Primary format for integer operate instructions:
+def format TlbOp(code, *opt_flags) {{
+ orig_code = code
+ cblk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+ exec_output = TlbOpExecute.subst(iop)
+}};
diff --git a/arch/mips/isa/formats/trap.isa b/arch/mips/isa/formats/trap.isa
new file mode 100644
index 000000000..78f8d87b0
--- /dev/null
+++ b/arch/mips/isa/formats/trap.isa
@@ -0,0 +1,53 @@
+////////////////////////////////////////////////////////////////////
+//
+// Trap instructions
+//
+
+output header {{
+ /**
+ * Base class for integer operations.
+ */
+ class Trap : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
+output decoder {{
+ std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return "Disassembly of integer instruction\n";
+ }
+}};
+
+def template TrapExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ //Call into the trap handler with the appropriate fault
+ return No_Fault;
+ }
+
+ //Write the resulting state to the execution context
+ %(op_wb)s;
+
+ return No_Fault;
+ }
+}};
+
+// Primary format for integer operate instructions:
+def format Trap(code, *opt_flags) {{
+ orig_code = code
+ cblk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+ exec_output = TrapExecute.subst(iop)
+}};
diff --git a/arch/mips/isa/includes.isa b/arch/mips/isa/includes.isa
new file mode 100644
index 000000000..ff7cb7d1d
--- /dev/null
+++ b/arch/mips/isa/includes.isa
@@ -0,0 +1,40 @@
+////////////////////////////////////////////////////////////////////
+//
+// Output include file directives.
+//
+
+output header {{
+#include <sstream>
+#include <iostream>
+#include <iomanip>
+
+#include "cpu/static_inst.hh"
+#include "traps.hh"
+#include "mem/mem_req.hh" // some constructors use MemReq flags
+}};
+
+output decoder {{
+#include "base/cprintf.hh"
+#include "base/loader/symtab.hh"
+#include "cpu/exec_context.hh" // for Jump::branchTarget()
+
+#include <math.h>
+#if defined(linux)
+#include <fenv.h>
+#endif
+}};
+
+output exec {{
+#include <math.h>
+#if defined(linux)
+#include <fenv.h>
+#endif
+
+#ifdef FULL_SYSTEM
+//#include "arch/alpha/pseudo_inst.hh"
+#endif
+#include "cpu/base.hh"
+#include "cpu/exetrace.hh"
+#include "sim/sim_exit.hh"
+}};
+
diff --git a/arch/mips/isa/main.isa b/arch/mips/isa/main.isa
new file mode 100644
index 000000000..a8c71872b
--- /dev/null
+++ b/arch/mips/isa/main.isa
@@ -0,0 +1,52 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+##include "m5/arch/sparc/isa_desc/includes.h"
+
+////////////////////////////////////////////////////////////////////
+//
+// Namespace statement. Everything below this line will be in the
+// MipsISAInst namespace.
+//
+
+namespace MipsISA;
+
+//Include the bitfield definitions
+##include "m5/arch/mips/isa_desc/bitfields.h"
+
+//Include the operand_types and operand definitions
+##include "m5/arch/mips/isa_desc/operands.h"
+
+//Include the base class for mips instructions, and some support code
+##include "m5/arch/mips/isa_desc/base.h"
+
+//Include the definitions for the instruction formats
+##include "m5/arch/mips/isa_desc/formats.h"
+
+//Include the decoder definition
+##include "m5/arch/mips/isa_desc/decoder.h"
diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
new file mode 100644
index 000000000..58fa2d3cf
--- /dev/null
+++ b/arch/mips/isa/operands.isa
@@ -0,0 +1,36 @@
+def operand_types {{
+ 'sb' : ('signed int', 8),
+ 'ub' : ('unsigned int', 8),
+ 'shw' : ('signed int', 16),
+ 'uhw' : ('unsigned int', 16),
+ 'sw' : ('signed int', 32),
+ 'uw' : ('unsigned int', 32),
+ 'sdw' : ('signed int', 64),
+ 'udw' : ('unsigned int', 64),
+ 'sf' : ('float', 32),
+ 'df' : ('float', 64),
+ 'qf' : ('float', 128)
+}};
+
+def operands {{
+ 'Rd': IntRegOperandTraits('uw', 'RD', 'IsInteger', 1),
+ 'Rs': IntRegOperandTraits('uw', 'RS', 'IsInteger', 2),
+ 'Rt': IntRegOperandTraits('uw', 'RT', 'IsInteger', 3),
+
+ 'IntImm': IntRegOperandTraits('uw', 'INTIMM', 'IsInteger', 3),
+ 'Sa': IntRegOperandTraits('uw', 'SA', 'IsInteger', 4),
+
+ 'Fd': FloatRegOperandTraits('sf', 'FD', 'IsFloating', 1),
+ 'Fs': FloatRegOperandTraits('sf', 'FS', 'IsFloating', 2),
+ 'Ft': FloatRegOperandTraits('sf', 'FT', 'IsFloating', 3),
+
+ 'Mem': MemOperandTraits('udw', None,
+ ('IsMemRef', 'IsLoad', 'IsStore'), 4)
+
+ #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
+ #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
+ #'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
+ # The next two are hacks for non-full-system call-pal emulation
+ #'R0': IntRegOperandTraits('uq', '0', None, 1),
+ #'R16': IntRegOperandTraits('uq', '16', None, 1)
+}};
diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc
new file mode 100644
index 000000000..90a85feb6
--- /dev/null
+++ b/arch/mips/isa_traits.cc
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/mips/isa_traits.hh"
+#include "cpu/static_inst.hh"
+#include "sim/serialize.hh"
+
+// Alpha UNOP (ldq_u r31,0(r0))
+// @todo: fix to MIPS specific
+const MachInst MipsISA::NoopMachInst = 0x2ffe0000;
+
+void
+MipsISA::RegFile::serialize(std::ostream &os)
+{
+ intRegFile.serialize(os);
+ floatRegFile.serialize(os);
+ miscRegs.serialize(os);
+ SERIALIZE_SCALAR(pc);
+ SERIALIZE_SCALAR(npc);
+}
+
+
+void
+MipsISA::RegFile::unserialize(Checkpoint *cp, const std::string &section)
+{
+ intRegFile.unserialize(cp, section);
+ floatRegFile.unserialize(cp, section);
+ miscRegs.unserialize(cp, section);
+ UNSERIALIZE_SCALAR(pc);
+ UNSERIALIZE_SCALAR(npc);
+}
+
+#endif //FULL_SYSTEM
diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh
new file mode 100644
index 000000000..55e9c0dcb
--- /dev/null
+++ b/arch/mips/isa_traits.hh
@@ -0,0 +1,532 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
+#define __ARCH_MIPS_ISA_TRAITS_HH__
+
+//This makes sure the big endian versions of certain functions are used.
+namespace LittleEndianGuest {}
+using namespace LittleEndianGuest
+
+#include "arch/mips/faults.hh"
+#include "base/misc.hh"
+#include "sim/host.hh"
+
+class FastCPU;
+class FullCPU;
+class Checkpoint;
+
+#define TARGET_MIPS
+
+template <class ISA> class StaticInst;
+template <class ISA> class StaticInstPtr;
+
+//namespace EV5
+//{
+// int DTB_ASN_ASN(uint64_t reg);
+// int ITB_ASN_ASN(uint64_t reg);
+//}
+
+class MipsISA
+{
+ public:
+
+ typedef uint32_t MachInst;
+ typedef uint64_t Addr;
+ typedef uint8_t RegIndex;
+
+ enum
+ {
+ MemoryEnd = 0xffffffffffffffffULL,
+
+ NumFloatRegs = 32,
+ NumMiscRegs = 32,
+
+ MaxRegsOfAnyType = 32,
+ // Static instruction parameters
+ MaxInstSrcRegs = 3,
+ MaxInstDestRegs = 2,
+
+ // Maximum trap level
+ MaxTL = 4
+
+ // semantically meaningful register indices
+ ZeroReg = 0, // architecturally meaningful
+ // the rest of these depend on the ABI
+ }
+ typedef uint64_t IntReg;
+
+ class IntRegFile
+ {
+ private:
+ //For right now, let's pretend the register file is static
+ IntReg regs[32];
+ public:
+ IntReg & operator [] (RegIndex index)
+ {
+ //Don't allow indexes outside of the 32 registers
+ index &= 0x1F
+ return regs[index];
+ }
+ };
+
+ void inline serialize(std::ostream & os)
+ {
+ SERIALIZE_ARRAY(regs, 32);
+ }
+
+ void inline unserialize(Checkpoint &*cp, const std::string &section)
+ {
+ UNSERIALIZE_ARRAY(regs, 32);
+ }
+
+ class FloatRegFile
+ {
+ private:
+ //By using the largest data type, we ensure everything
+ //is aligned correctly in memory
+ union
+ {
+ double double rawRegs[16];
+ uint64_t regDump[32];
+ };
+ class QuadRegs
+ {
+ private:
+ FloatRegFile * parent;
+ public:
+ QuadRegs(FloatRegFile * p) : parent(p) {;}
+ double double & operator [] (RegIndex index)
+ {
+ //Quad floats are index by the single
+ //precision register the start on,
+ //and only 16 should be accessed
+ index = (index >> 2) & 0xF;
+ return parent->rawRegs[index];
+ }
+ };
+ class DoubleRegs
+ {
+ private:
+ FloatRegFile * parent;
+ public:
+ DoubleRegs(FloatRegFile * p) : parent(p) {;}
+ double & operator [] (RegIndex index)
+ {
+ //Double floats are index by the single
+ //precision register the start on,
+ //and only 32 should be accessed
+ index = (index >> 1) & 0x1F
+ return ((double [])parent->rawRegs)[index];
+ }
+ }
+ class SingleRegs
+ {
+ private:
+ FloatRegFile * parent;
+ public:
+ SingleRegs(FloatRegFile * p) : parent(p) {;}
+ double & operator [] (RegFile index)
+ {
+ //Only 32 single floats should be accessed
+ index &= 0x1F
+ return ((float [])parent->rawRegs)[index];
+ }
+ }
+ public:
+ void inline serialize(std::ostream & os)
+ {
+ SERIALIZE_ARRAY(regDump, 32);
+ }
+
+ void inline unserialize(Checkpoint &* cp, std::string & section)
+ {
+ UNSERIALIZE_ARRAY(regDump, 32);
+ }
+
+ QuadRegs quadRegs;
+ DoubleRegs doubleRegs;
+ SingleRegs singleRegs;
+ FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this)
+ {;}
+ };
+
+ // control register file contents
+ typedef uint64_t MiscReg;
+ // The control registers, broken out into fields
+ class MiscRegFile
+ {
+ public:
+ union
+ {
+ uint16_t pstate; // Process State Register
+ struct
+ {
+ uint16_t ag:1; // Alternate Globals
+ uint16_t ie:1; // Interrupt enable
+ uint16_t priv:1; // Privelege mode
+ uint16_t am:1; // Address mask
+ uint16_t pef:1; // PSTATE enable floating-point
+ uint16_t red:1; // RED (reset, error, debug) state
+ uint16_t mm:2; // Memory Model
+ uint16_t tle:1; // Trap little-endian
+ uint16_t cle:1; // Current little-endian
+ } pstateFields;
+ }
+ uint64_t tba; // Trap Base Address
+ union
+ {
+ uint64_t y; // Y (used in obsolete multiplication)
+ struct
+ {
+ uint64_t value:32; // The actual value stored in y
+ const uint64_t :32; // reserved bits
+ } yFields;
+ }
+ uint8_t pil; // Process Interrupt Register
+ uint8_t cwp; // Current Window Pointer
+ uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured on the previous level)
+ union
+ {
+ uint8_t ccr; // Condition Code Register
+ struct
+ {
+ union
+ {
+ uint8_t icc:4; // 32-bit condition codes
+ struct
+ {
+ uint8_t c:1; // Carry
+ uint8_t v:1; // Overflow
+ uint8_t z:1; // Zero
+ uint8_t n:1; // Negative
+ } iccFields:4;
+ } :4;
+ union
+ {
+ uint8_t xcc:4; // 64-bit condition codes
+ struct
+ {
+ uint8_t c:1; // Carry
+ uint8_t v:1; // Overflow
+ uint8_t z:1; // Zero
+ uint8_t n:1; // Negative
+ } xccFields:4;
+ } :4;
+ } ccrFields;
+ }
+ uint8_t asi; // Address Space Identifier
+ uint8_t tl; // Trap Level
+ uint64_t tpc[MaxTL]; // Trap Program Counter (value from previous trap level)
+ uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from previous trap level)
+ union
+ {
+ uint64_t tstate[MaxTL]; // Trap State
+ struct
+ {
+ //Values are from previous trap level
+ uint64_t cwp:5; // Current Window Pointer
+ const uint64_t :2; // Reserved bits
+ uint64_t pstate:10; // Process State
+ const uint64_t :6; // Reserved bits
+ uint64_t asi:8; // Address Space Identifier
+ uint64_t ccr:8; // Condition Code Register
+ } tstateFields[MaxTL];
+ }
+ union
+ {
+ uint64_t tick; // Hardware clock-tick counter
+ struct
+ {
+ uint64_t counter:63; // Clock-tick count
+ uint64_t npt:1; // Non-priveleged trap
+ } tickFields;
+ }
+ uint8_t cansave; // Savable windows
+ uint8_t canrestore; // Restorable windows
+ uint8_t otherwin; // Other windows
+ uint8_t cleanwin; // Clean windows
+ union
+ {
+ uint8_t wstate; // Window State
+ struct
+ {
+ uint8_t normal:3; // Bits TT<4:2> are set to on a normal
+ // register window trap
+ uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
+ // register window trap
+ } wstateFields;
+ }
+ union
+ {
+ uint64_t ver; // Version
+ struct
+ {
+ uint64_t maxwin:5; // Max CWP value
+ const uint64_t :2; // Reserved bits
+ uint64_t maxtl:8; // Maximum trap level
+ const uint64_t :8; // Reserved bits
+ uint64_t mask:8; // Processor mask set revision number
+ uint64_t impl:16; // Implementation identification number
+ uint64_t manuf:16; // Manufacturer code
+ } verFields;
+ }
+ union
+ {
+ uint64_t fsr; // Floating-Point State Register
+ struct
+ {
+ union
+ {
+ uint64_t cexc:5; // Current excpetion
+ struct
+ {
+ uint64_t nxc:1; // Inexact
+ uint64_t dzc:1; // Divide by zero
+ uint64_t ufc:1; // Underflow
+ uint64_t ofc:1; // Overflow
+ uint64_t nvc:1; // Invalid operand
+ } cexecFields:5;
+ } :5;
+ union
+ {
+ uint64_t aexc:5; // Accrued exception
+ struct
+ {
+ uint64_t nxc:1; // Inexact
+ uint64_t dzc:1; // Divide by zero
+ uint64_t ufc:1; // Underflow
+ uint64_t ofc:1; // Overflow
+ uint64_t nvc:1; // Invalid operand
+ } aexecFields:5;
+ } :5;
+ uint64_t fcc0:2; // Floating-Point condtion codes
+ const uint64_t :1; // Reserved bits
+ uint64_t qne:1; // Deferred trap queue not empty
+ // with no queue, it should read 0
+ uint64_t ftt:3; // Floating-Point trap type
+ uint64_t ver:3; // Version (of the FPU)
+ const uint64_t :2; // Reserved bits
+ uint64_t ns:1; // Nonstandard floating point
+ union
+ {
+ uint64_t tem:5; // Trap Enable Mask
+ struct
+ {
+ uint64_t nxm:1; // Inexact
+ uint64_t dzm:1; // Divide by zero
+ uint64_t ufm:1; // Underflow
+ uint64_t ofm:1; // Overflow
+ uint64_t nvm:1; // Invalid operand
+ } temFields:5;
+ } :5;
+ const uint64_t :2; // Reserved bits
+ uint64_t rd:2; // Rounding direction
+ uint64_t fcc1:2; // Floating-Point condition codes
+ uint64_t fcc2:2; // Floating-Point condition codes
+ uint64_t fcc3:2; // Floating-Point condition codes
+ const uint64_t :26; // Reserved bits
+ } fsrFields;
+ }
+ union
+ {
+ uint8_t fprs; // Floating-Point Register State
+ struct
+ {
+ dl:1; // Dirty lower
+ du:1; // Dirty upper
+ fef:1; // FPRS enable floating-Point
+ } fprsFields;
+ };
+
+ void serialize(std::ostream & os)
+ {
+ SERIALIZE_SCALAR(pstate);
+ SERIAlIZE_SCALAR(tba);
+ SERIALIZE_SCALAR(y);
+ SERIALIZE_SCALAR(pil);
+ SERIALIZE_SCALAR(cwp);
+ SERIALIZE_ARRAY(tt, MaxTL);
+ SERIALIZE_SCALAR(ccr);
+ SERIALIZE_SCALAR(asi);
+ SERIALIZE_SCALAR(tl);
+ SERIALIZE_SCALAR(tpc);
+ SERIALIZE_SCALAR(tnpc);
+ SERIALIZE_ARRAY(tstate, MaxTL);
+ SERIALIZE_SCALAR(tick);
+ SERIALIZE_SCALAR(cansave);
+ SERIALIZE_SCALAR(canrestore);
+ SERIALIZE_SCALAR(otherwin);
+ SERIALIZE_SCALAR(cleanwin);
+ SERIALIZE_SCALAR(wstate);
+ SERIALIZE_SCALAR(ver);
+ SERIALIZE_SCALAR(fsr);
+ SERIALIZE_SCALAR(fprs);
+ }
+
+ void unserialize(Checkpoint &* cp, std::string & section)
+ {
+ UNSERIALIZE_SCALAR(pstate);
+ UNSERIAlIZE_SCALAR(tba);
+ UNSERIALIZE_SCALAR(y);
+ UNSERIALIZE_SCALAR(pil);
+ UNSERIALIZE_SCALAR(cwp);
+ UNSERIALIZE_ARRAY(tt, MaxTL);
+ UNSERIALIZE_SCALAR(ccr);
+ UNSERIALIZE_SCALAR(asi);
+ UNSERIALIZE_SCALAR(tl);
+ UNSERIALIZE_SCALAR(tpc);
+ UNSERIALIZE_SCALAR(tnpc);
+ UNSERIALIZE_ARRAY(tstate, MaxTL);
+ UNSERIALIZE_SCALAR(tick);
+ UNSERIALIZE_SCALAR(cansave);
+ UNSERIALIZE_SCALAR(canrestore);
+ UNSERIALIZE_SCALAR(otherwin);
+ UNSERIALIZE_SCALAR(cleanwin);
+ UNSERIALIZE_SCALAR(wstate);
+ UNSERIALIZE_SCALAR(ver);
+ UNSERIALIZE_SCALAR(fsr);
+ UNSERIALIZE_SCALAR(fprs);
+ }
+ };
+
+ typedef union
+ {
+ IntReg intreg;
+ FloatReg fpreg;
+ MiscReg ctrlreg;
+ } AnyReg;
+
+ struct RegFile
+ {
+ IntRegFile intRegFile; // (signed) integer register file
+ FloatRegFile floatRegFile; // floating point register file
+ MiscRegFile miscRegFile; // control register file
+
+ Addr pc; // Program Counter
+ Addr npc; // Next Program Counter
+
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string &section);
+ };
+
+ static StaticInstPtr<AlphaISA> decodeInst(MachInst);
+
+ // return a no-op instruction... used for instruction fetch faults
+ static const MachInst NoopMachInst;
+
+ // Instruction address compression hooks
+ static inline Addr realPCToFetchPC(const Addr &addr)
+ {
+ return addr;
+ }
+
+ static inline Addr fetchPCToRealPC(const Addr &addr)
+ {
+ return addr;
+ }
+
+ // the size of "fetched" instructions (not necessarily the size
+ // of real instructions for PISA)
+ static inline size_t fetchInstSize()
+ {
+ return sizeof(MachInst);
+ }
+
+ /**
+ * Function to insure ISA semantics about 0 registers.
+ * @param xc The execution context.
+ */
+ template <class XC>
+ static void zeroRegisters(XC *xc);
+};
+
+
+typedef MIPSISA TheISA;
+
+typedef TheISA::MachInst MachInst;
+typedef TheISA::Addr Addr;
+typedef TheISA::RegIndex RegIndex;
+typedef TheISA::IntReg IntReg;
+typedef TheISA::IntRegFile IntRegFile;
+typedef TheISA::FloatReg FloatReg;
+typedef TheISA::FloatRegFile FloatRegFile;
+typedef TheISA::MiscReg MiscReg;
+typedef TheISA::MiscRegFile MiscRegFile;
+typedef TheISA::AnyReg AnyReg;
+typedef TheISA::RegFile RegFile;
+
+const int VMPageSize = TheISA::VMPageSize;
+const int LogVMPageSize = TheISA::LogVMPageSize;
+const int ZeroReg = TheISA::ZeroReg;
+const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
+const int MaxAddr = (Addr)-1;
+
+#ifndef FULL_SYSTEM
+class SyscallReturn {
+ public:
+ template <class T>
+ SyscallReturn(T v, bool s)
+ {
+ retval = (uint64_t)v;
+ success = s;
+ }
+
+ template <class T>
+ SyscallReturn(T v)
+ {
+ success = (v >= 0);
+ retval = (uint64_t)v;
+ }
+
+ ~SyscallReturn() {}
+
+ SyscallReturn& operator=(const SyscallReturn& s) {
+ retval = s.retval;
+ success = s.success;
+ return *this;
+ }
+
+ bool successful() { return success; }
+ uint64_t value() { return retval; }
+
+
+ private:
+ uint64_t retval;
+ bool success;
+};
+
+#endif
+
+
+#ifdef FULL_SYSTEM
+
+#include "arch/alpha/ev5.hh"
+#endif
+
+#endif // __ARCH_MIPS_ISA_TRAITS_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-23 21:45:51 +0000