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-rw-r--r--arch/mips/faults.cc10
-rw-r--r--arch/mips/faults.hh20
-rw-r--r--arch/mips/isa/base.isa2
-rw-r--r--arch/mips/isa/formats.isa35
-rw-r--r--arch/mips/isa/formats/formats.isa35
-rw-r--r--arch/mips/isa/formats/mem.isa106
-rw-r--r--arch/mips/isa/includes.isa3
-rw-r--r--arch/mips/isa/main.isa12
-rw-r--r--arch/mips/isa_traits.cc16
-rw-r--r--arch/mips/isa_traits.hh10
10 files changed, 197 insertions, 52 deletions
diff --git a/arch/mips/faults.cc b/arch/mips/faults.cc
index 1b31dfa69..a31856f07 100644
--- a/arch/mips/faults.cc
+++ b/arch/mips/faults.cc
@@ -98,6 +98,10 @@ FaultName IntegerOverflowFault::_name = "intover";
FaultVect IntegerOverflowFault::_vect = 0x0501;
FaultStat IntegerOverflowFault::_count;
+FaultName UnimpFault::_name = "Unimplemented Simulator feature";
+FaultVect UnimpFault::_vect = 0x0001;
+FaultStat UnimpFault::_count;
+
#if FULL_SYSTEM
void MipsFault::invoke(ExecContext * xc)
@@ -125,6 +129,12 @@ void ArithmeticFault::invoke(ExecContext * xc)
panic("Arithmetic traps are unimplemented!");
}
+void UnimpFault::invoke(ExecContext * xc)
+{
+ FaultBase::invoke(xc);
+ panic("Unimpfault: %s\n", panicStr.c_str());
+}
+
#endif
} // namespace MipsISA
diff --git a/arch/mips/faults.hh b/arch/mips/faults.hh
index 0bdabe29e..b0d228090 100644
--- a/arch/mips/faults.hh
+++ b/arch/mips/faults.hh
@@ -264,6 +264,26 @@ class IntegerOverflowFault : public MipsFault
FaultStat & countStat() {return _count;}
};
+class UnimpFault : public MipsFault
+{
+ private:
+ std::string panicStr;
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _count;
+ public:
+ UnimpFault(std::string _str)
+ : panicStr(_str)
+ { }
+
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+ void invoke(ExecContext * xc);
+#endif
+};
+
} // MipsISA namespace
#endif // __FAULTS_HH__
diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa
index 139a6d876..9ed9651d2 100644
--- a/arch/mips/isa/base.isa
+++ b/arch/mips/isa/base.isa
@@ -9,8 +9,6 @@
output header {{
#define R31 31
-#include "arch/mips/faults.hh"
-#include "arch/mips/isa_traits.hh"
using namespace MipsISA;
diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa
deleted file mode 100644
index f7a9e4ce2..000000000
--- a/arch/mips/isa/formats.isa
+++ /dev/null
@@ -1,35 +0,0 @@
-// -*- mode:c++ -*-
-
-//Templates from this format are used later
-//Include the basic format
-##include "m5/arch/mips/isa/formats/basic.isa"
-
-//Include the basic format
-##include "m5/arch/mips/isa/formats/noop.isa"
-
-//Include utility formats/functions
-##include "m5/arch/mips/isa/formats/util.isa"
-
-//Include the cop0 formats
-##include "m5/arch/mips/isa/formats/cop0.isa"
-
-//Include the integer formats
-##include "m5/arch/mips/isa/formats/int.isa"
-
-//Include the floatOp format
-##include "m5/arch/mips/isa/formats/fp.isa"
-
-//Include the mem format
-##include "m5/arch/mips/isa/formats/mem.isa"
-
-//Include the trap format
-##include "m5/arch/mips/isa/formats/trap.isa"
-
-//Include the branch format
-##include "m5/arch/mips/isa/formats/branch.isa"
-
-//Include the noop format
-##include "m5/arch/mips/isa/formats/unimp.isa"
-
-//Include the noop format
-##include "m5/arch/mips/isa/formats/unknown.isa"
diff --git a/arch/mips/isa/formats/formats.isa b/arch/mips/isa/formats/formats.isa
new file mode 100644
index 000000000..7d493ffae
--- /dev/null
+++ b/arch/mips/isa/formats/formats.isa
@@ -0,0 +1,35 @@
+// -*- mode:c++ -*-
+
+//Templates from this format are used later
+//Include the basic format
+##include "basic.isa"
+
+//Include the basic format
+##include "noop.isa"
+
+//Include utility functions
+##include "util.isa"
+
+//Include the cop0 formats
+##include "cop0.isa"
+
+//Include the integer formats
+##include "int.isa"
+
+//Include the floatOp format
+##include "fp.isa"
+
+//Include the mem format
+##include "mem.isa"
+
+//Include the trap format
+##include "trap.isa"
+
+//Include the branch format
+##include "branch.isa"
+
+//Include the noop format
+##include "unimp.isa"
+
+//Include the noop format
+##include "unknown.isa"
diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
index a42976331..df1dca4e1 100644
--- a/arch/mips/isa/formats/mem.isa
+++ b/arch/mips/isa/formats/mem.isa
@@ -199,8 +199,23 @@ def template LoadMemAccExecute {{
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
+ Addr EA;
Fault fault = NoFault;
- //Fill in Code for Out-of-Order CPUs
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ EA = xc->getEA();
+
+ if (fault == NoFault) {
+ fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+ %(code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
return fault;
}
}};
@@ -236,8 +251,18 @@ def template LoadInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
+ Addr EA;
Fault fault = NoFault;
- //Fill in Code for Out-of-Order CPUs
+
+ %(fp_enable_check)s;
+ %(op_src_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
+ }
+
return fault;
}
}};
@@ -249,7 +274,20 @@ def template LoadCompleteAcc {{
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
- //Fill in Code for Out-of-Order CPUs
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+
+ memcpy(&Mem, data, sizeof(Mem));
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
return fault;
}
}};
@@ -260,8 +298,33 @@ def template StoreMemAccExecute {{
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
+ Addr EA;
Fault fault = NoFault;
- //Fill in Code for Out-of-Order CPUs
+ uint64_t write_result = 0;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ EA = xc->getEA();
+
+ if (fault == NoFault) {
+ %(code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, &write_result);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
return fault;
}
}};
@@ -306,8 +369,25 @@ def template StoreInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
+ Addr EA;
Fault fault = NoFault;
- //Fill in Code for Out-of-Order CPUs
+ uint64_t write_result = 0;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, &write_result);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
return fault;
}
}};
@@ -319,7 +399,21 @@ def template StoreCompleteAcc {{
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
- //Fill in Code for Out-of-Order CPUs
+ uint64_t write_result = 0;
+
+ %(fp_enable_check)s;
+ %(op_dest_decl)s;
+
+ memcpy(&write_result, data, sizeof(write_result));
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
return fault;
}
}};
diff --git a/arch/mips/isa/includes.isa b/arch/mips/isa/includes.isa
index b81c4eda2..9c370fbe3 100644
--- a/arch/mips/isa/includes.isa
+++ b/arch/mips/isa/includes.isa
@@ -17,6 +17,8 @@ output decoder {{
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/exec_context.hh" // for Jump::branchTarget()
+#include "arch/mips/faults.hh"
+#include "arch/mips/isa_traits.hh"
#include <math.h>
#if defined(linux)
@@ -27,6 +29,7 @@ using namespace MipsISA;
}};
output exec {{
+#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
#include <math.h>
#if defined(linux)
diff --git a/arch/mips/isa/main.isa b/arch/mips/isa/main.isa
index 411e398b4..01d81323e 100644
--- a/arch/mips/isa/main.isa
+++ b/arch/mips/isa/main.isa
@@ -26,7 +26,7 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-##include "m5/arch/mips/isa/includes.isa"
+##include "includes.isa"
////////////////////////////////////////////////////////////////////
//
@@ -37,16 +37,16 @@
namespace MipsISA;
//Include the bitfield definitions
-##include "m5/arch/mips/isa/bitfields.isa"
+##include "bitfields.isa"
//Include the operand_types and operand definitions
-##include "m5/arch/mips/isa/operands.isa"
+##include "operands.isa"
//Include the base class for mips instructions, and some support code
-##include "m5/arch/mips/isa/base.isa"
+##include "base.isa"
//Include the definitions for the instruction formats
-##include "m5/arch/mips/isa/formats.isa"
+##include "formats/formats.isa"
//Include the decoder definition
-##include "m5/arch/mips/isa/decoder.isa"
+##include "decoder.isa"
diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc
index 849d3311d..c6cfb2a0f 100644
--- a/arch/mips/isa_traits.cc
+++ b/arch/mips/isa_traits.cc
@@ -275,9 +275,21 @@ RoundPage(Addr addr)
{ return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); }
void
+IntRegFile::serialize(std::ostream &os)
+{
+ SERIALIZE_ARRAY(regs, NumIntRegs);
+}
+
+void
+IntRegFile::unserialize(Checkpoint *cp, const std::string &section)
+{
+ UNSERIALIZE_ARRAY(regs, NumIntRegs);
+}
+
+void
RegFile::serialize(std::ostream &os)
{
- SERIALIZE_ARRAY(intRegFile, NumIntRegs);
+ intRegFile.serialize(os);
//SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
//SERIALIZE_SCALAR(miscRegs.fpcr);
//SERIALIZE_SCALAR(miscRegs.uniq);
@@ -298,7 +310,7 @@ RegFile::serialize(std::ostream &os)
void
RegFile::unserialize(Checkpoint *cp, const std::string &section)
{
- UNSERIALIZE_ARRAY(intRegFile, NumIntRegs);
+ intRegFile.unserialize(cp, section);
//UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
//UNSERIALIZE_SCALAR(miscRegs.fpcr);
//UNSERIALIZE_SCALAR(miscRegs.uniq);
diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh
index fd6f6e5c7..83b021540 100644
--- a/arch/mips/isa_traits.hh
+++ b/arch/mips/isa_traits.hh
@@ -43,7 +43,6 @@ class Checkpoint;
class ExecContext;
namespace LittleEndianGuest {};
-using namespace LittleEndianGuest;
#define TARGET_MIPS
@@ -92,6 +91,8 @@ class SyscallReturn {
namespace MipsISA
{
+ using namespace LittleEndianGuest;
+
typedef uint32_t MachInst;
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
@@ -515,6 +516,13 @@ extern const Addr PageOffset;
void createCP0Regs();
void coldReset();
+
+ typedef int ContextParam;
+ typedef int ContextVal;
+
+ void changeContext(ContextParam param, ContextVal val)
+ {
+ }
};
StaticInstPtr decodeInst(ExtMachInst);
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-11 01:07:14 +0000