diff options
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/isa/decoder.isa | 16 | ||||
| -rw-r--r-- | arch/mips/isa/formats/branch.isa | 4 | ||||
| -rw-r--r-- | arch/mips/isa/formats/noop.isa | 4 | ||||
| -rw-r--r-- | arch/mips/isa_traits.hh | 99 | ||||
| -rw-r--r-- | arch/mips/process.cc | 2 |
5 files changed, 66 insertions, 59 deletions
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index ac97241ed..93e7238f8 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -30,11 +30,17 @@ decode OPCODE_HI default Unknown::unknown() { //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." - 0x0: decode RS { - 0x0: sll({{ Rd = Rt.uw << SA; }}); - //0x0:nop({{ ; }}); //really sll r0,r0,0 - // 0x1:ssnop({{ ; }});//really sll r0,r0,1 - // 0x3:ehb({{ ; }}); //really sll r0,r0,3 + 0x0: decode RS { + 0x0: decode RT { + 0x0: decode RD default Nop::nop() { + 0x0: decode SA { + 0x1: ssnop({{ ; }}); //really sll r0,r0,1 + 0x3: ehb({{ ; }}); //really sll r0,r0,3 + } + } + } + + default: sll({{ Rd = Rt.uw << SA; }}); } 0x2: decode SRL { diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa index 0d2ad7855..ce84f4b51 100644 --- a/arch/mips/isa/formats/branch.isa +++ b/arch/mips/isa/formats/branch.isa @@ -265,8 +265,6 @@ def format Branch(code,*flags) {{ code += ' NNPC = NNPC;\n' code += '} \n' - code += 'cout << hex << "NPC: " << NPC << " + " << disp << " = " << NNPC << endl;' - iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), ('IsDirectControl', 'IsCondControl')) @@ -305,8 +303,6 @@ def format Jump(code,*flags) {{ if strlen > 1 and name[1:] == 'al': code = 'r31 = NNPC;\n' + code - #code += 'if(NNPC == 0x80000638) { NNPC = r31; cout << "SKIPPING JUMP TO SIM_GET_MEM_CONF" << endl;}' - #code += 'target = NNPC;' iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\ ('IsIndirectControl', 'IsUncondControl')) diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa index d35179005..2aa4816e3 100644 --- a/arch/mips/isa/formats/noop.isa +++ b/arch/mips/isa/formats/noop.isa @@ -88,3 +88,7 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{ exec_output = BasicExecute.subst(iop) }}; +def format Nop() {{ + decode_block = 'return new Nop(\"sll r0,r0,0\",machInst);\n' +}}; + diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh index 4850010d4..bd56ce2cc 100644 --- a/arch/mips/isa_traits.hh +++ b/arch/mips/isa_traits.hh @@ -96,46 +96,56 @@ namespace MipsISA typedef uint64_t ExtMachInst; typedef uint8_t RegIndex; // typedef uint64_t Addr; - enum { - MemoryEnd = 0xffffffffffffffffULL, - - NumIntRegs = 32, - NumFloatRegs = 32, - NumMiscRegs = 258, //account for hi,lo regs - - MaxRegsOfAnyType = 32, - // Static instruction parameters - MaxInstSrcRegs = 3, - MaxInstDestRegs = 2, - - // semantically meaningful register indices - ZeroReg = 0, // architecturally meaningful - // the rest of these depend on the ABI - StackPointerReg = 30, - GlobalPointerReg = 29, - ProcedureValueReg = 27, - ReturnAddressReg = 26, - ReturnValueReg = 0, - FramePointerReg = 15, - ArgumentReg0 = 16, - ArgumentReg1 = 17, - ArgumentReg2 = 18, - ArgumentReg3 = 19, - ArgumentReg4 = 20, - ArgumentReg5 = 21, - SyscallNumReg = ReturnValueReg, - SyscallPseudoReturnReg = ArgumentReg4, - SyscallSuccessReg = 19, - LogVMPageSize = 13, // 8K bytes - VMPageSize = (1 << LogVMPageSize), - - BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned - - WordBytes = 4, - HalfwordBytes = 2, - ByteBytes = 1, - DepNA = 0, - }; + + // Constants Related to the number of registers + + const int NumIntArchRegs = 32; + const int NumPALShadowRegs = 8; + const int NumFloatArchRegs = 32; + // @todo: Figure out what this number really should be. + const int NumMiscArchRegs = 32; + + const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; + const int NumFloatRegs = NumFloatArchRegs; + const int NumMiscRegs = NumMiscArchRegs; + + const int TotalNumRegs = NumIntRegs + NumFloatRegs + + NumMiscRegs + 0/*NumInternalProcRegs*/; + + const int TotalDataRegs = NumIntRegs + NumFloatRegs; + + // Static instruction parameters + const int MaxInstSrcRegs = 3; + const int MaxInstDestRegs = 2; + + // semantically meaningful register indices + const int ZeroReg = 31; // architecturally meaningful + // the rest of these depend on the ABI + const int StackPointerReg = 30; + const int GlobalPointerReg = 29; + const int ProcedureValueReg = 27; + const int ReturnAddressReg = 26; + const int ReturnValueReg = 0; + const int FramePointerReg = 15; + const int ArgumentReg0 = 16; + const int ArgumentReg1 = 17; + const int ArgumentReg2 = 18; + const int ArgumentReg3 = 19; + const int ArgumentReg4 = 20; + const int ArgumentReg5 = 21; + const int SyscallNumReg = ReturnValueReg; + const int SyscallPseudoReturnReg = ArgumentReg4; + const int SyscallSuccessReg = 19; + + const int LogVMPageSize = 13; // 8K bytes + const int VMPageSize = (1 << LogVMPageSize); + + const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned + + const int WordBytes = 4; + const int HalfwordBytes = 2; + const int ByteBytes = 1; + // These enumerate all the registers for dependence tracking. enum DependenceTags { @@ -402,15 +412,6 @@ extern const Addr PageOffset; }; #endif - enum { - TotalNumRegs = - NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs - }; - - enum { - TotalDataRegs = NumIntRegs + NumFloatRegs - }; - typedef union { IntReg intreg; FloatReg fpreg; diff --git a/arch/mips/process.cc b/arch/mips/process.cc index f63e668b5..8f8a34934 100644 --- a/arch/mips/process.cc +++ b/arch/mips/process.cc @@ -27,7 +27,7 @@ */ #include "arch/mips/process.hh" -#include "arch/mips/linux/process.hh" +#include "arch/mips/linux_process.hh" #include "base/loader/object_file.hh" #include "base/misc.hh" |