summaryrefslogtreecommitdiff
path: root/arch/sparc/isa/formats/integerop.isa
diff options
context:
space:
mode:
Diffstat (limited to 'arch/sparc/isa/formats/integerop.isa')
-rw-r--r--arch/sparc/isa/formats/integerop.isa110
1 files changed, 110 insertions, 0 deletions
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
new file mode 100644
index 000000000..275a346d3
--- /dev/null
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -0,0 +1,110 @@
+////////////////////////////////////////////////////////////////////
+//
+// Integer operate instructions
+//
+
+output header {{
+ /**
+ * Base class for integer operations.
+ */
+ class IntegerOp : public SparcStaticInst
+ {
+ protected:
+
+ /// Constructor
+ IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
+output decoder {{
+ std::string IntegerOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return "Disassembly of integer instruction\n";
+ }
+}};
+
+def template IntegerExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ //These are set to constants when the execute method
+ //is generated
+ bool useCc = ;
+ bool checkPriv = ;
+
+ //Attempt to execute the instruction
+ try
+ {
+ checkPriv;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(code)s;
+ }
+ //If we have an exception for some reason,
+ //deal with it
+ catch(SparcException except)
+ {
+ //Deal with exception
+ return No_Fault;
+ }
+
+ //Write the resulting state to the execution context
+ %(op_wb)s;
+ if(useCc)
+ {
+ xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
+ xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
+ xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
+ xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
+ xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
+ xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
+ xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
+ xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
+ }
+ return No_Fault;
+ }
+}};
+
+// Primary format for integer operate instructions:
+def format IntegerOp(code, *opt_flags) {{
+ orig_code = code
+ cblk = CodeBlock(code)
+ checkPriv = (code.find('checkPriv') != -1)
+ code.replace('checkPriv', '')
+ if checkPriv:
+ code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
+ else:
+ code.replace('checkPriv;', '')
+ for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
+ ('xvValue', '0'), ('xcValue', '0')):
+ code.replace(marker, value)
+ iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+ exec_output = IntegerExecute.subst(iop)
+}};
+
+// Primary format for integer operate instructions:
+def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
+ orig_code = code
+ cblk = CodeBlock(code)
+ checkPriv = (code.find('checkPriv') != -1)
+ code.replace('checkPriv', '')
+ if checkPriv:
+ code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
+ else:
+ code.replace('checkPriv;', '')
+ for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
+ ('xvValue', xvValue), ('xcValue', xcValue)):
+ code.replace(marker, value)
+ iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+ exec_output = IntegerExecute.subst(iop)
+}};