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Diffstat (limited to 'arch/sparc/isa/formats')
-rw-r--r--arch/sparc/isa/formats/branch.isa241
-rw-r--r--arch/sparc/isa/formats/integerop.isa291
-rw-r--r--arch/sparc/isa/formats/mem.isa95
-rw-r--r--arch/sparc/isa/formats/nop.isa (renamed from arch/sparc/isa/formats/noop.isa)34
-rw-r--r--arch/sparc/isa/formats/trap.isa4
-rw-r--r--arch/sparc/isa/formats/unknown.isa2
6 files changed, 564 insertions, 103 deletions
diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa
index b9dc960de..e4ce4592c 100644
--- a/arch/sparc/isa/formats/branch.isa
+++ b/arch/sparc/isa/formats/branch.isa
@@ -5,7 +5,7 @@
output header {{
/**
- * Base class for integer operations.
+ * Base class for branch operations.
*/
class Branch : public SparcStaticInst
{
@@ -19,12 +19,187 @@ output header {{
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
+
+ /**
+ * Base class for branch operations with an immediate displacement.
+ */
+ class BranchDisp : public Branch
+ {
+ protected:
+ // Constructor
+ BranchDisp(const char *mnem, MachInst _machInst,
+ OpClass __opClass) :
+ Branch(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ int32_t disp;
+ };
+
+ /**
+ * Base class for branches with 19 bit displacements.
+ */
+ class Branch19 : public BranchDisp
+ {
+ protected:
+ // Constructor
+ Branch19(const char *mnem, MachInst _machInst,
+ OpClass __opClass) :
+ BranchDisp(mnem, _machInst, __opClass)
+ {
+ disp = sign_ext(DISP19 << 2, 21);
+ }
+ };
+
+ /**
+ * Base class for branches with 22 bit displacements.
+ */
+ class Branch22 : public BranchDisp
+ {
+ protected:
+ // Constructor
+ Branch22(const char *mnem, MachInst _machInst,
+ OpClass __opClass) :
+ BranchDisp(mnem, _machInst, __opClass)
+ {
+ disp = sign_ext(DISP22 << 2, 24);
+ }
+ };
+
+ /**
+ * Base class for branches with 30 bit displacements.
+ */
+ class Branch30 : public BranchDisp
+ {
+ protected:
+ // Constructor
+ Branch30(const char *mnem, MachInst _machInst,
+ OpClass __opClass) :
+ BranchDisp(mnem, _machInst, __opClass)
+ {
+ disp = sign_ext(DISP30 << 2, 32);
+ }
+ };
+
+ /**
+ * Base class for 16bit split displacements.
+ */
+ class BranchSplit : public BranchDisp
+ {
+ protected:
+ // Constructor
+ BranchSplit(const char *mnem, MachInst _machInst,
+ OpClass __opClass) :
+ BranchDisp(mnem, _machInst, __opClass)
+ {
+ disp = sign_ext((D16HI << 16) | (D16LO << 2), 18);
+ }
+ };
+
+ /**
+ * Base class for branches that use an immediate and a register to
+ * compute their displacements.
+ */
+ class BranchImm13 : public Branch
+ {
+ protected:
+ // Constructor
+ BranchImm13(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ Branch(mnem, _machInst, __opClass), imm(sign_ext(SIMM13, 13))
+ {
+ }
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ int32_t imm;
+ };
}};
output decoder {{
- std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ std::string Branch::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
{
- return "Branch instruction\n";
+ std::stringstream response;
+
+ printMnemonic(response, mnemonic);
+
+ if (_numSrcRegs > 0)
+ {
+ printReg(response, _srcRegIdx[0]);
+ for(int x = 1; x < _numSrcRegs; x++)
+ {
+ response << ", ";
+ printReg(response, _srcRegIdx[x]);
+ }
+ }
+
+ if (_numDestRegs > 0)
+ {
+ if(_numSrcRegs > 0)
+ response << ", ";
+ printReg(response, _destRegIdx[0]);
+ }
+
+ return response.str();
+ }
+
+ std::string BranchImm13::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+
+ printMnemonic(response, mnemonic);
+
+ if (_numSrcRegs > 0)
+ {
+ printReg(response, _srcRegIdx[0]);
+ for(int x = 1; x < _numSrcRegs; x++)
+ {
+ response << ", ";
+ printReg(response, _srcRegIdx[x]);
+ }
+ }
+
+ if(_numSrcRegs > 0)
+ response << ", ";
+
+ ccprintf(response, "0x%x", imm);
+
+ if (_numDestRegs > 0)
+ {
+ response << ", ";
+ printReg(response, _destRegIdx[0]);
+ }
+
+ return response.str();
+ }
+
+ std::string BranchDisp::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+ std::string symbol;
+ Addr symbolAddr;
+
+ Addr target = disp + pc;
+
+ printMnemonic(response, mnemonic);
+ ccprintf(response, "0x%x", target);
+
+ if(symtab->findNearestSymbol(target, symbol, symbolAddr))
+ {
+ ccprintf(response, " <%s", symbol);
+ if(symbolAddr != target)
+ ccprintf(response, "+0x%x>", target - symbolAddr);
+ else
+ ccprintf(response, ">");
+ }
+
+ return response.str();
}
}};
@@ -37,6 +212,8 @@ def template BranchExecute {{
%(op_decl)s;
%(op_rd)s;
+
+ NNPC = xc->readNextNPC();
%(code)s;
if(fault == NoFault)
@@ -49,13 +226,63 @@ def template BranchExecute {{
}
}};
-// Primary format for integer operate instructions:
+// Primary format for branch instructions:
def format Branch(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+ (usesImm, code, immCode,
+ rString, iString) = splitOutImm(code)
+ codeBlk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'Branch', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
+ exec_output = BranchExecute.subst(iop)
+ if usesImm:
+ imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString,
+ codeBlk, opt_flags)
+ header_output += BasicDeclare.subst(imm_iop)
+ decoder_output += BasicConstructor.subst(imm_iop)
+ exec_output += BranchExecute.subst(imm_iop)
+ decode_block = ROrImmDecode.subst(iop)
+ else:
+ decode_block = BasicDecode.subst(iop)
+}};
+
+// Primary format for branch instructions:
+def format Branch19(code, *opt_flags) {{
+ codeBlk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ exec_output = BranchExecute.subst(iop)
decode_block = BasicDecode.subst(iop)
+}};
+
+// Primary format for branch instructions:
+def format Branch22(code, *opt_flags) {{
+ codeBlk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+}};
+
+// Primary format for branch instructions:
+def format Branch30(code, *opt_flags) {{
+ codeBlk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ exec_output = BranchExecute.subst(iop)
+ decode_block = BasicDecode.subst(iop)
}};
+
+// Primary format for branch instructions:
+def format BranchSplit(code, *opt_flags) {{
+ codeBlk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ exec_output = BranchExecute.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+}};
+
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
index e7bd4c2a4..2c2123f86 100644
--- a/arch/sparc/isa/formats/integerop.isa
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -11,103 +11,230 @@ output header {{
{
protected:
// Constructor
- IntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+ IntOp(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
+
+ virtual bool printPseudoOps(std::ostream &os, Addr pc,
+ const SymbolTable *symtab) const;
};
/**
- * Base class for 10 bit immediate integer operations.
+ * Base class for immediate integer operations.
*/
- class IntOpImm10 : public IntOp
+ class IntOpImm : public IntOp
{
protected:
// Constructor
- IntOpImm10(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- IntOp(mnem, _machInst, __opClass), imm(SIMM10)
+ IntOpImm(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ IntOp(mnem, _machInst, __opClass)
{
}
uint32_t imm;
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ virtual bool printPseudoOps(std::ostream &os, Addr pc,
+ const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Base class for 10 bit immediate integer operations.
+ */
+ class IntOpImm10 : public IntOpImm
+ {
+ protected:
+ // Constructor
+ IntOpImm10(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ IntOpImm(mnem, _machInst, __opClass)
+ {
+ imm = SIMM10;
+ }
};
/**
* Base class for 13 bit immediate integer operations.
*/
- class IntOpImm13 : public IntOp
+ class IntOpImm13 : public IntOpImm
{
protected:
// Constructor
- IntOpImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- IntOp(mnem, _machInst, __opClass), imm(SIMM13)
+ IntOpImm13(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ IntOpImm(mnem, _machInst, __opClass)
{
+ imm = SIMM13;
}
+ };
- uint32_t imm;
+ /**
+ * Base class for sethi.
+ */
+ class SetHi : public IntOpImm
+ {
+ protected:
+ // Constructor
+ SetHi(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ IntOpImm(mnem, _machInst, __opClass)
+ {
+ imm = (IMM22 << 10) & 0xFFFFFC00;
+ }
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
};
}};
+def template SetHiDecode {{
+ {
+ if(RD == 0 && IMM22 == 0)
+ return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass));
+ else
+ return (SparcStaticInst *)(new %(class_name)s(machInst));
+ }
+}};
+
output decoder {{
- std::string IntOp::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
+
+ bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
+ const SymbolTable *symbab) const
{
- return "Integer instruction\n";
+ if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
+ {
+ printMnemonic(os, "mov");
+ if(_numSrcRegs > 0)
+ printReg(os, _srcRegIdx[1]);
+ ccprintf(os, ", ");
+ if(_numDestRegs > 0)
+ printReg(os, _destRegIdx[0]);
+
+ return true;
+ }
+ return false;
}
-}};
-def template IntOpExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
+ bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
+ const SymbolTable *symbab) const
{
- Fault fault = NoFault;
+ if(!strcmp(mnemonic, "or"))
+ {
+ if(_srcRegIdx[0] == 0)
+ {
+ if(imm == 0)
+ {
+ printMnemonic(os, "clr");
+ if(_numDestRegs > 0)
+ printReg(os, _destRegIdx[0]);
+ return true;
+ }
+ else
+ {
+ printMnemonic(os, "mov");
+ ccprintf(os, ", 0x%x, ", imm);
+ if(_numDestRegs > 0)
+ printReg(os, _destRegIdx[0]);
+ return true;
+ }
+ }
+ else if(imm == 0)
+ {
+ printMnemonic(os, "mov");
+ if(_numSrcRegs > 0)
+ printReg(os, _srcRegIdx[0]);
+ ccprintf(os, ", ");
+ if(_numDestRegs > 0)
+ printReg(os, _destRegIdx[0]);
+ return true;
+ }
+ }
+ return false;
+ }
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
+ std::string IntOp::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
- //Write the resulting state to the execution context
- if(fault == NoFault)
- %(op_wb)s;
- return fault;
+ if(!printPseudoOps(response, pc, symtab))
+ {
+ printMnemonic(response, mnemonic);
+ if (_numSrcRegs > 0)
+ {
+ printReg(response, _srcRegIdx[0]);
+ for(int x = 1; x < _numSrcRegs; x++)
+ {
+ response << ", ";
+ printReg(response, _srcRegIdx[x]);
+ }
+ }
+ if (_numDestRegs > 0)
+ {
+ if(_numSrcRegs > 0)
+ response << ", ";
+ printReg(response, _destRegIdx[0]);
+ }
+ }
+ return response.str();
}
-}};
-def template IntOpCcExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
+ std::string IntOpImm::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
{
- Fault fault;
-
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
+ std::stringstream response;
- //Write the resulting state to the execution context
- if(fault == NoFault)
+ if(!printPseudoOps(response, pc, symtab))
{
- %(op_wb)s;
- CcrIccN = Rd & (1 << 63);
- CcrIccZ = (Rd == 0);
- CcrIccV = ivValue;
- CcrIccC = icValue;
- CcrXccN = Rd & (1 << 31);
- CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
- CcrXccV = xvValue;
- CcrXccC = xcValue;
+ printMnemonic(response, mnemonic);
+ if (_numSrcRegs > 1)
+ {
+ printReg(response, _srcRegIdx[0]);
+ for(int x = 1; x < _numSrcRegs - 1; x++)
+ {
+ response << ", ";
+ printReg(response, _srcRegIdx[x]);
+ }
+ }
+ if(_numSrcRegs > 0)
+ response << ", ";
+ ccprintf(response, "0x%x", imm);
+ if (_numDestRegs > 0)
+ {
+ response << ", ";
+ printReg(response, _destRegIdx[0]);
+ }
}
- return fault;
+ return response.str();
+ }
+
+ std::string SetHi::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+
+ printMnemonic(response, mnemonic);
+ if(_numSrcRegs > 0)
+ response << ", ";
+ ccprintf(response, "%%hi(0x%x), ", imm);
+ printReg(response, _destRegIdx[0]);
+ return response.str();
}
}};
-def template IntOpCcResExecute {{
+def template IntOpExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault;
+ Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
@@ -117,49 +244,83 @@ def template IntOpCcResExecute {{
if(fault == NoFault)
{
%(op_wb)s;
- CcrIccN = Rd & (1 << 63);
- CcrIccZ = (Rd == 0);
- CcrXccN = Rd & (1 << 31);
- CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
- CcrIccV = CcrIccC = CcrXccV = CcrXccC = 0;
+ %(cc_code)s;
}
return fault;
}
}};
let {{
- def doIntFormat(code, execTemplate, name, Name, opt_flags):
- (usesImm, cblk, immCblk, rString, iString) = splitOutImm(code)
- iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
+ def doIntFormat(code, ccCode, name, Name, opt_flags):
+ (usesImm, code, immCode,
+ rString, iString) = splitOutImm(code)
+ iop = genCompositeIop(code, name, Name,
+ 'IntOp', opt_flags, cc_code=ccCode)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
- exec_output = execTemplate.subst(iop)
+ exec_output = IntOpExecute.subst(iop)
if usesImm:
- imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
- immCblk, opt_flags)
+ imm_iop = genCompositeIop(code, name, Name + 'Imm',
+ 'IntOpImm' + iString, opt_flags, cc_code=ccCode)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
- exec_output += execTemplate.subst(imm_iop)
+ exec_output += IntOpExecute.subst(imm_iop)
decode_block = ROrImmDecode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
+ return (header_output, decoder_output, exec_output, decode_block)
+
+ calcCcCode = '''
+ CcrIccN = (Rd >> 63) & 1;
+ CcrIccZ = (Rd == 0);
+ CcrXccN = (Rd >> 31) & 1;
+ CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
+ CcrIccV = %(ivValue)s;
+ CcrIccC = %(icValue)s;
+ CcrXccV = %(xvValue)s;
+ CcrXccC = %(xcValue)s;
+ '''
}};
// Primary format for integer operate instructions:
def format IntOp(code, *opt_flags) {{
- doIntFormat(code, IntOpExecute, name, Name, opt_flags)
+ ccCode = ''
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doIntFormat(code, ccCode,
+ name, Name, opt_flags)
}};
// Primary format for integer operate instructions:
def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
- for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
- ('xvValue', xvValue), ('xcValue', xcValue)):
- code.replace(marker, value)
- doIntFormat(code, IntOpCcExecute, name, Name, opt_flags)
+ ccCode = calcCcCode % vars()
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doIntFormat(code, ccCode,
+ name, Name, opt_flags)
}};
// Primary format for integer operate instructions:
def format IntOpCcRes(code, *opt_flags) {{
- doIntFormat(code, IntOpCcResExecute, name, Name, opt_flags)
+ ccCode = calcCcCode % {"icValue":"0",
+ "ivValue":"0",
+ "xcValue":"0",
+ "xvValue":"0"}
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doIntFormat(code, ccCode,
+ name, Name, opt_flags)
+}};
+
+def format SetHi(code, *opt_flags) {{
+ iop = genCompositeIop(code, name, Name, 'SetHi',
+ opt_flags, cc_code='')
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ exec_output = IntOpExecute.subst(iop)
+ decode_block = SetHiDecode.subst(iop)
}};
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
index f1162e24b..8c9d21c01 100644
--- a/arch/sparc/isa/formats/mem.isa
+++ b/arch/sparc/isa/formats/mem.isa
@@ -5,7 +5,7 @@
output header {{
/**
- * Base class for integer operations.
+ * Base class for memory operations.
*/
class Mem : public SparcStaticInst
{
@@ -20,12 +20,76 @@ output header {{
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
+
+ /**
+ * Class for memory operations which use an immediate offset.
+ */
+ class MemImm : public Mem
+ {
+ protected:
+
+ // Constructor
+ MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+ Mem(mnem, _machInst, __opClass), imm(SIMM13)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ int imm;
+ };
}};
output decoder {{
- std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ std::string Mem::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
{
- return "Memory instruction\n";
+ std::stringstream response;
+ bool load = (_numDestRegs == 1);
+
+ printMnemonic(response, mnemonic);
+ if(!load)
+ {
+ printReg(response, _srcRegIdx[0]);
+ ccprintf(response, ", ");
+ }
+ ccprintf(response, "[ ");
+ printReg(response, _srcRegIdx[load ? 0 : 1]);
+ ccprintf(response, " + ");
+ printReg(response, _srcRegIdx[load ? 1 : 2]);
+ ccprintf(response, " ]");
+ if(load)
+ {
+ ccprintf(response, ", ");
+ printReg(response, _destRegIdx[0]);
+ }
+
+ return response.str();
+ }
+
+ std::string MemImm::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+ bool load = (_numDestRegs == 1);
+
+ printMnemonic(response, mnemonic);
+ if(!load)
+ {
+ printReg(response, _srcRegIdx[0]);
+ ccprintf(response, ", ");
+ }
+ ccprintf(response, "[ ");
+ printReg(response, _srcRegIdx[load ? 0 : 1]);
+ ccprintf(response, " + 0x%x ]", imm);
+ if(load)
+ {
+ ccprintf(response, ", ");
+ printReg(response, _destRegIdx[0]);
+ }
+
+ return response.str();
}
}};
@@ -50,19 +114,16 @@ def template MemExecute {{
}
}};
-// Primary format for integer operate instructions:
+// Primary format for memory instructions:
def format Mem(code, *opt_flags) {{
- addrCalc = 'EA = I ? (Rs1 + SIMM13) : Rs1 + Rs2;'
- composite = code + '\n' + addrCalc
- origCodeBlk = CodeBlock(code)
- compositeBlk = CodeBlock(composite)
- addrCalcBlk = CodeBlock(addrCalc)
- iop = InstObjParams(name, Name, 'SparcStaticInst', compositeBlk, opt_flags)
- iop.code = origCodeBlk.code
- iop.orig_code = origCodeBlk.orig_code
- iop.ea_code = addrCalcBlk.code
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = MemExecute.subst(iop)
+ addrCalcReg = 'EA = Rs1 + Rs2;'
+ addrCalcImm = 'EA = Rs1 + SIMM13;'
+ iop = genCompositeIop(code, name, Name, 'Mem',
+ opt_flags, ea_code=addrCalcReg)
+ iop_imm = genCompositeIop(code, name, Name + 'Imm', 'MemImm',
+ opt_flags, ea_code=addrCalcImm)
+ header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
+ decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
+ decode_block = ROrImmDecode.subst(iop)
+ exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
}};
diff --git a/arch/sparc/isa/formats/noop.isa b/arch/sparc/isa/formats/nop.isa
index 5007f5bcb..df7503eee 100644
--- a/arch/sparc/isa/formats/noop.isa
+++ b/arch/sparc/isa/formats/nop.isa
@@ -1,35 +1,47 @@
////////////////////////////////////////////////////////////////////
//
-// Noop instruction
+// Nop instruction
//
output header {{
/**
- * Noop class.
+ * Nop class.
*/
- class Noop : public SparcStaticInst
+ class Nop : public SparcStaticInst
{
- protected:
+ public:
// Constructor
- Noop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+ Nop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
+ // All Nop instructions do the same thing, so this can be
+ // defined here. Nops can be defined directly, so there needs
+ // to be a default implementation
+ Fault execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ //Nothing to see here, move along
+ return NoFault;
+ }
+
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
- std::string Noop::generateDisassembly(Addr pc,
+ std::string Nop::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
- return "Noop\n";
+ std::stringstream response;
+ printMnemonic(response, mnemonic);
+ return response.str();
}
}};
-def template NoopExecute {{
+def template NopExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -39,12 +51,12 @@ def template NoopExecute {{
}};
// Primary format for integer operate instructions:
-def format Noop(code, *opt_flags) {{
+def format Nop(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+ iop = InstObjParams(name, Name, 'Nop', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = NoopExecute.subst(iop)
+ exec_output = NopExecute.subst(iop)
}};
diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa
index db4494132..5608548bd 100644
--- a/arch/sparc/isa/formats/trap.isa
+++ b/arch/sparc/isa/formats/trap.isa
@@ -27,7 +27,7 @@ output decoder {{
std::string Trap::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
- return "Trap instruction\n";
+ return "Trap instruction";
}
}};
@@ -46,7 +46,7 @@ def template TrapExecute {{
def format Trap(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+ iop = InstObjParams(name, Name, 'Trap', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/arch/sparc/isa/formats/unknown.isa b/arch/sparc/isa/formats/unknown.isa
index eeb2b9496..223111905 100644
--- a/arch/sparc/isa/formats/unknown.isa
+++ b/arch/sparc/isa/formats/unknown.isa
@@ -29,7 +29,7 @@ output decoder {{
std::string Unknown::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
- return "Unknown instruction\n";
+ return "Unknown instruction";
}
}};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 15:17:50 +0000