diff options
Diffstat (limited to 'arch/sparc/isa/formats')
| -rw-r--r-- | arch/sparc/isa/formats/basic.isa | 68 | ||||
| -rw-r--r-- | arch/sparc/isa/formats/branch.isa | 308 | ||||
| -rw-r--r-- | arch/sparc/isa/formats/integerop.isa | 349 | ||||
| -rw-r--r-- | arch/sparc/isa/formats/mem.isa | 171 | ||||
| -rw-r--r-- | arch/sparc/isa/formats/nop.isa | 62 | ||||
| -rw-r--r-- | arch/sparc/isa/formats/priv.isa | 139 | ||||
| -rw-r--r-- | arch/sparc/isa/formats/trap.isa | 64 | ||||
| -rw-r--r-- | arch/sparc/isa/formats/unknown.isa | 46 |
8 files changed, 0 insertions, 1207 deletions
diff --git a/arch/sparc/isa/formats/basic.isa b/arch/sparc/isa/formats/basic.isa deleted file mode 100644 index 73df7617d..000000000 --- a/arch/sparc/isa/formats/basic.isa +++ /dev/null @@ -1,68 +0,0 @@ - -// Declarations for execute() methods. -def template BasicExecDeclare {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; -}}; - -// Basic instruction class declaration template. -def template BasicDeclare {{ - /** - * Static instruction class for "%(mnemonic)s". - */ - class %(class_name)s : public %(base_class)s - { - public: - // Constructor. - %(class_name)s(MachInst machInst); - %(BasicExecDeclare)s - }; -}}; - -// Basic instruction class constructor template. -def template BasicConstructor {{ - inline %(class_name)s::%(class_name)s(MachInst machInst) - : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) - { - %(constructor)s; - } -}}; - -// Basic instruction class execute method template. -def template BasicExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - %(code)s; - - if(fault == NoFault) - { - %(op_wb)s; - } - return fault; - } -}}; - -// Basic decode template. -def template BasicDecode {{ - return new %(class_name)s(machInst); -}}; - -// Basic decode template, passing mnemonic in as string arg to constructor. -def template BasicDecodeWithMnemonic {{ - return new %(class_name)s("%(mnemonic)s", machInst); -}}; - -// The most basic instruction format... used only for a few misc. insts -def format BasicOperate(code, *flags) {{ - iop = InstObjParams(name, Name, 'SparcStaticInst', - CodeBlock(code), flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa deleted file mode 100644 index 37bdb9402..000000000 --- a/arch/sparc/isa/formats/branch.isa +++ /dev/null @@ -1,308 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Branch instructions -// - -output header {{ - /** - * Base class for branch operations. - */ - class Branch : public SparcStaticInst - { - protected: - // Constructor - Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : - SparcStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - }; - - /** - * Base class for branch operations with an immediate displacement. - */ - class BranchDisp : public Branch - { - protected: - // Constructor - BranchDisp(const char *mnem, MachInst _machInst, - OpClass __opClass) : - Branch(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - - int32_t disp; - }; - - /** - * Base class for branches with 19 bit displacements. - */ - class Branch19 : public BranchDisp - { - protected: - // Constructor - Branch19(const char *mnem, MachInst _machInst, - OpClass __opClass) : - BranchDisp(mnem, _machInst, __opClass) - { - disp = sign_ext(DISP19 << 2, 21); - } - }; - - /** - * Base class for branches with 22 bit displacements. - */ - class Branch22 : public BranchDisp - { - protected: - // Constructor - Branch22(const char *mnem, MachInst _machInst, - OpClass __opClass) : - BranchDisp(mnem, _machInst, __opClass) - { - disp = sign_ext(DISP22 << 2, 24); - } - }; - - /** - * Base class for branches with 30 bit displacements. - */ - class Branch30 : public BranchDisp - { - protected: - // Constructor - Branch30(const char *mnem, MachInst _machInst, - OpClass __opClass) : - BranchDisp(mnem, _machInst, __opClass) - { - disp = sign_ext(DISP30 << 2, 32); - } - }; - - /** - * Base class for 16bit split displacements. - */ - class BranchSplit : public BranchDisp - { - protected: - // Constructor - BranchSplit(const char *mnem, MachInst _machInst, - OpClass __opClass) : - BranchDisp(mnem, _machInst, __opClass) - { - disp = sign_ext((D16HI << 16) | (D16LO << 2), 18); - } - }; - - /** - * Base class for branches that use an immediate and a register to - * compute their displacements. - */ - class BranchImm13 : public Branch - { - protected: - // Constructor - BranchImm13(const char *mnem, MachInst _machInst, OpClass __opClass) : - Branch(mnem, _machInst, __opClass), imm(sign_ext(SIMM13, 13)) - { - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - - int32_t imm; - }; -}}; - -output decoder {{ - std::string Branch::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - - printMnemonic(response, mnemonic); - - if (_numSrcRegs > 0) - { - printReg(response, _srcRegIdx[0]); - for(int x = 1; x < _numSrcRegs; x++) - { - response << ", "; - printReg(response, _srcRegIdx[x]); - } - } - - if (_numDestRegs > 0) - { - if(_numSrcRegs > 0) - response << ", "; - printReg(response, _destRegIdx[0]); - } - - return response.str(); - } - - std::string BranchImm13::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - - printMnemonic(response, mnemonic); - - if (_numSrcRegs > 0) - { - printReg(response, _srcRegIdx[0]); - for(int x = 1; x < _numSrcRegs; x++) - { - response << ", "; - printReg(response, _srcRegIdx[x]); - } - } - - if(_numSrcRegs > 0) - response << ", "; - - ccprintf(response, "0x%x", imm); - - if (_numDestRegs > 0) - { - response << ", "; - printReg(response, _destRegIdx[0]); - } - - return response.str(); - } - - std::string BranchDisp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - std::string symbol; - Addr symbolAddr; - - Addr target = disp + pc; - - printMnemonic(response, mnemonic); - ccprintf(response, "0x%x", target); - - if(symtab->findNearestSymbol(target, symbol, symbolAddr)) - { - ccprintf(response, " <%s", symbol); - if(symbolAddr != target) - ccprintf(response, "+%d>", target - symbolAddr); - else - ccprintf(response, ">"); - } - - return response.str(); - } -}}; - -def template BranchExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - //Attempt to execute the instruction - Fault fault = NoFault; - - %(op_decl)s; - %(op_rd)s; - - NNPC = xc->readNextNPC(); - %(code)s; - - if(fault == NoFault) - { - //Write the resulting state to the execution context - %(op_wb)s; - } - - return fault; - } -}}; - -let {{ - handle_annul = ''' - { - if(A) - { - NPC = xc->readNextNPC(); - NNPC = NPC + 4; - } - else - { - NPC = xc->readNextPC(); - NNPC = xc->readNextNPC(); - } - }''' -}}; - -// Primary format for branch instructions: -def format Branch(code, *opt_flags) {{ - code = re.sub(r'handle_annul', handle_annul, code) - (usesImm, code, immCode, - rString, iString) = splitOutImm(code) - iop = InstObjParams(name, Name, 'Branch', code, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = BranchExecute.subst(iop) - if usesImm: - imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString, - immCode, opt_flags) - header_output += BasicDeclare.subst(imm_iop) - decoder_output += BasicConstructor.subst(imm_iop) - exec_output += BranchExecute.subst(imm_iop) - decode_block = ROrImmDecode.subst(iop) - else: - decode_block = BasicDecode.subst(iop) -}}; - -// Primary format for branch instructions: -def format Branch19(code, *opt_flags) {{ - code = re.sub(r'handle_annul', handle_annul, code) - codeBlk = CodeBlock(code) - iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = BranchExecute.subst(iop) - decode_block = BasicDecode.subst(iop) -}}; - -// Primary format for branch instructions: -def format Branch22(code, *opt_flags) {{ - code = re.sub(r'handle_annul', handle_annul, code) - codeBlk = CodeBlock(code) - iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = BranchExecute.subst(iop) - decode_block = BasicDecode.subst(iop) -}}; - -// Primary format for branch instructions: -def format Branch30(code, *opt_flags) {{ - code = re.sub(r'handle_annul', handle_annul, code) - codeBlk = CodeBlock(code) - iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = BranchExecute.subst(iop) - decode_block = BasicDecode.subst(iop) -}}; - -// Primary format for branch instructions: -def format BranchSplit(code, *opt_flags) {{ - code = re.sub(r'handle_annul', handle_annul, code) - codeBlk = CodeBlock(code) - iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = BranchExecute.subst(iop) - decode_block = BasicDecode.subst(iop) -}}; - diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa deleted file mode 100644 index 881154b67..000000000 --- a/arch/sparc/isa/formats/integerop.isa +++ /dev/null @@ -1,349 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Integer operate instructions -// - -output header {{ - /** - * Base class for integer operations. - */ - class IntOp : public SparcStaticInst - { - protected: - // Constructor - IntOp(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - SparcStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - - virtual bool printPseudoOps(std::ostream &os, Addr pc, - const SymbolTable *symtab) const; - }; - - /** - * Base class for immediate integer operations. - */ - class IntOpImm : public IntOp - { - protected: - // Constructor - IntOpImm(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - IntOp(mnem, _machInst, __opClass) - { - } - - int32_t imm; - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - - virtual bool printPseudoOps(std::ostream &os, Addr pc, - const SymbolTable *symtab) const; - }; - - /** - * Base class for 10 bit immediate integer operations. - */ - class IntOpImm10 : public IntOpImm - { - protected: - // Constructor - IntOpImm10(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - IntOpImm(mnem, _machInst, __opClass) - { - imm = sign_ext(SIMM10, 10); - } - }; - - /** - * Base class for 11 bit immediate integer operations. - */ - class IntOpImm11 : public IntOpImm - { - protected: - // Constructor - IntOpImm11(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - IntOpImm(mnem, _machInst, __opClass) - { - imm = sign_ext(SIMM11, 11); - } - }; - - /** - * Base class for 13 bit immediate integer operations. - */ - class IntOpImm13 : public IntOpImm - { - protected: - // Constructor - IntOpImm13(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - IntOpImm(mnem, _machInst, __opClass) - { - imm = sign_ext(SIMM13, 13); - } - }; - - /** - * Base class for sethi. - */ - class SetHi : public IntOpImm - { - protected: - // Constructor - SetHi(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - IntOpImm(mnem, _machInst, __opClass) - { - imm = (IMM22 << 10) & 0xFFFFFC00; - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - }; -}}; - -def template SetHiDecode {{ - { - if(RD == 0 && IMM22 == 0) - return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass)); - else - return (SparcStaticInst *)(new %(class_name)s(machInst)); - } -}}; - -output decoder {{ - - bool IntOp::printPseudoOps(std::ostream &os, Addr pc, - const SymbolTable *symbab) const - { - if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) - { - printMnemonic(os, "mov"); - if(_numSrcRegs > 0) - printReg(os, _srcRegIdx[1]); - ccprintf(os, ", "); - if(_numDestRegs > 0) - printReg(os, _destRegIdx[0]); - - return true; - } - return false; - } - - bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc, - const SymbolTable *symbab) const - { - if(!strcmp(mnemonic, "or")) - { - if(_srcRegIdx[0] == 0) - { - if(imm == 0) - { - printMnemonic(os, "clr"); - if(_numDestRegs > 0) - printReg(os, _destRegIdx[0]); - return true; - } - else - { - printMnemonic(os, "mov"); - ccprintf(os, ", 0x%x, ", imm); - if(_numDestRegs > 0) - printReg(os, _destRegIdx[0]); - return true; - } - } - else if(imm == 0) - { - printMnemonic(os, "mov"); - if(_numSrcRegs > 0) - printReg(os, _srcRegIdx[0]); - ccprintf(os, ", "); - if(_numDestRegs > 0) - printReg(os, _destRegIdx[0]); - return true; - } - } - return false; - } - - std::string IntOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - - if(!printPseudoOps(response, pc, symtab)) - { - printMnemonic(response, mnemonic); - if (_numSrcRegs > 0) - { - printReg(response, _srcRegIdx[0]); - for(int x = 1; x < _numSrcRegs; x++) - { - response << ", "; - printReg(response, _srcRegIdx[x]); - } - } - if (_numDestRegs > 0) - { - if(_numSrcRegs > 0) - response << ", "; - printReg(response, _destRegIdx[0]); - } - } - return response.str(); - } - - std::string IntOpImm::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - - if(!printPseudoOps(response, pc, symtab)) - { - printMnemonic(response, mnemonic); - if (_numSrcRegs > 0) - { - printReg(response, _srcRegIdx[0]); - for(int x = 1; x < _numSrcRegs - 1; x++) - { - response << ", "; - printReg(response, _srcRegIdx[x]); - } - } - if(_numSrcRegs > 0) - response << ", "; - ccprintf(response, "0x%x", imm); - if (_numDestRegs > 0) - { - response << ", "; - printReg(response, _destRegIdx[0]); - } - } - return response.str(); - } - - std::string SetHi::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - - printMnemonic(response, mnemonic); - if(_numSrcRegs > 0) - response << ", "; - ccprintf(response, "%%hi(0x%x), ", imm); - printReg(response, _destRegIdx[0]); - return response.str(); - } -}}; - -def template IntOpExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - - %(op_decl)s; - %(op_rd)s; - %(code)s; - - //Write the resulting state to the execution context - if(fault == NoFault) - { - %(cc_code)s; - %(op_wb)s; - } - return fault; - } -}}; - -let {{ - def doIntFormat(code, ccCode, name, Name, opt_flags): - (usesImm, code, immCode, - rString, iString) = splitOutImm(code) - iop = InstObjParams(name, Name, 'IntOp', code, - opt_flags, ("cc_code", ccCode)) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = IntOpExecute.subst(iop) - if usesImm: - imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString, - immCode, opt_flags, ("cc_code", ccCode)) - header_output += BasicDeclare.subst(imm_iop) - decoder_output += BasicConstructor.subst(imm_iop) - exec_output += IntOpExecute.subst(imm_iop) - decode_block = ROrImmDecode.subst(iop) - else: - decode_block = BasicDecode.subst(iop) - return (header_output, decoder_output, exec_output, decode_block) - - calcCcCode = ''' - CcrIccN = (Rd >> 31) & 1; - CcrIccZ = ((Rd & 0xFFFFFFFF) == 0); - CcrXccN = (Rd >> 63) & 1; - CcrXccZ = (Rd == 0); - CcrIccV = %(ivValue)s; - CcrIccC = %(icValue)s; - CcrXccV = %(xvValue)s; - CcrXccC = %(xcValue)s; - DPRINTF(Sparc, "in = %%d\\n", CcrIccN); - DPRINTF(Sparc, "iz = %%d\\n", CcrIccZ); - DPRINTF(Sparc, "xn = %%d\\n", CcrXccN); - DPRINTF(Sparc, "xz = %%d\\n", CcrXccZ); - DPRINTF(Sparc, "iv = %%d\\n", CcrIccV); - DPRINTF(Sparc, "ic = %%d\\n", CcrIccC); - DPRINTF(Sparc, "xv = %%d\\n", CcrXccV); - DPRINTF(Sparc, "xc = %%d\\n", CcrXccC); - ''' -}}; - -// Primary format for integer operate instructions: -def format IntOp(code, *opt_flags) {{ - ccCode = '' - (header_output, - decoder_output, - exec_output, - decode_block) = doIntFormat(code, ccCode, - name, Name, opt_flags) -}}; - -// Primary format for integer operate instructions: -def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ - ccCode = calcCcCode % vars() - (header_output, - decoder_output, - exec_output, - decode_block) = doIntFormat(code, ccCode, - name, Name, opt_flags) -}}; - -// Primary format for integer operate instructions: -def format IntOpCcRes(code, *opt_flags) {{ - ccCode = calcCcCode % {"icValue":"0", - "ivValue":"0", - "xcValue":"0", - "xvValue":"0"} - (header_output, - decoder_output, - exec_output, - decode_block) = doIntFormat(code, ccCode, - name, Name, opt_flags) -}}; - -def format SetHi(code, *opt_flags) {{ - iop = InstObjParams(name, Name, 'SetHi', - code, opt_flags, ("cc_code", '')) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = IntOpExecute.subst(iop) - decode_block = SetHiDecode.subst(iop) -}}; - diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa deleted file mode 100644 index 12dae57e5..000000000 --- a/arch/sparc/isa/formats/mem.isa +++ /dev/null @@ -1,171 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Mem instructions -// - -output header {{ - /** - * Base class for memory operations. - */ - class Mem : public SparcStaticInst - { - protected: - - // Constructor - Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - SparcStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - }; - - /** - * Class for memory operations which use an immediate offset. - */ - class MemImm : public Mem - { - protected: - - // Constructor - MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - Mem(mnem, _machInst, __opClass) - { - imm = sign_ext(SIMM13, 13); - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - - int32_t imm; - }; -}}; - -output decoder {{ - std::string Mem::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - bool load = flags[IsLoad]; - bool save = flags[IsStore]; - - printMnemonic(response, mnemonic); - if(save) - { - printReg(response, _srcRegIdx[0]); - ccprintf(response, ", "); - } - ccprintf(response, "[ "); - printReg(response, _srcRegIdx[!save ? 0 : 1]); - ccprintf(response, " + "); - printReg(response, _srcRegIdx[!save ? 1 : 2]); - ccprintf(response, " ]"); - if(load) - { - ccprintf(response, ", "); - printReg(response, _destRegIdx[0]); - } - - return response.str(); - } - - std::string MemImm::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - bool load = flags[IsLoad]; - bool save = flags[IsStore]; - - printMnemonic(response, mnemonic); - if(save) - { - printReg(response, _srcRegIdx[0]); - ccprintf(response, ", "); - } - ccprintf(response, "[ "); - printReg(response, _srcRegIdx[!save ? 0 : 1]); - if(imm >= 0) - ccprintf(response, " + 0x%x ]", imm); - else - ccprintf(response, " + -0x%x ]", -imm); - if(load) - { - ccprintf(response, ", "); - printReg(response, _destRegIdx[0]); - } - - return response.str(); - } -}}; - -def template MemExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - Addr EA; - %(op_decl)s; - %(op_rd)s; - %(ea_code)s; - DPRINTF(Sparc, "The address is 0x%x\n", EA); - %(load)s; - %(code)s; - %(store)s; - - if(fault == NoFault) - { - //Write the resulting state to the execution context - %(op_wb)s; - } - - return fault; - } -}}; - -let {{ - # Leave memAccessFlags at 0 for now - loadString = "xc->read(EA, (uint%(width)s_t&)Mem, 0);" - storeString = "uint64_t write_result = 0; \ - xc->write((uint%(width)s_t)Mem, EA, 0, &write_result);" - - def doMemFormat(code, load, store, name, Name, opt_flags): - addrCalcReg = 'EA = Rs1 + Rs2;' - addrCalcImm = 'EA = Rs1 + imm;' - iop = InstObjParams(name, Name, 'Mem', code, - opt_flags, ("ea_code", addrCalcReg), - ("load", load), ("store", store)) - iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code, - opt_flags, ("ea_code", addrCalcImm), - ("load", load), ("store", store)) - header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm) - decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm) - decode_block = ROrImmDecode.subst(iop) - exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm) - return (header_output, decoder_output, exec_output, decode_block) -}}; - -def format Load(code, width, *opt_flags) {{ - (header_output, - decoder_output, - exec_output, - decode_block) = doMemFormat(code, - loadString % {"width":width}, '', name, Name, opt_flags) -}}; - -def format Store(code, width, *opt_flags) {{ - (header_output, - decoder_output, - exec_output, - decode_block) = doMemFormat(code, '', - storeString % {"width":width}, name, Name, opt_flags) -}}; - -def format LoadStore(code, width, *opt_flags) {{ - (header_output, - decoder_output, - exec_output, - decode_block) = doMemFormat(code, - loadString % {"width":width}, storeString % {"width":width}, - name, Name, opt_flags) -}}; diff --git a/arch/sparc/isa/formats/nop.isa b/arch/sparc/isa/formats/nop.isa deleted file mode 100644 index df7503eee..000000000 --- a/arch/sparc/isa/formats/nop.isa +++ /dev/null @@ -1,62 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Nop instruction -// - -output header {{ - /** - * Nop class. - */ - class Nop : public SparcStaticInst - { - public: - // Constructor - Nop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - SparcStaticInst(mnem, _machInst, __opClass) - { - } - - // All Nop instructions do the same thing, so this can be - // defined here. Nops can be defined directly, so there needs - // to be a default implementation - Fault execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - //Nothing to see here, move along - return NoFault; - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string Nop::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - printMnemonic(response, mnemonic); - return response.str(); - } -}}; - -def template NopExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - //Nothing to see here, move along - return NoFault; - } -}}; - -// Primary format for integer operate instructions: -def format Nop(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'Nop', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = NopExecute.subst(iop) -}}; diff --git a/arch/sparc/isa/formats/priv.isa b/arch/sparc/isa/formats/priv.isa deleted file mode 100644 index f9fea01f2..000000000 --- a/arch/sparc/isa/formats/priv.isa +++ /dev/null @@ -1,139 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Privilege mode instructions -// - -output header {{ - /** - * Base class for privelege mode operations. - */ - class Priv : public SparcStaticInst - { - protected: - // Constructor - Priv(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - SparcStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - }; - - /** - * Base class for user mode "tick" access. - */ - class PrivTick : public SparcStaticInst - { - protected: - // Constructor - PrivTick(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - SparcStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - }; - - /** - * Base class for privelege mode operations with immediates. - */ - class PrivImm : public Priv - { - protected: - // Constructor - PrivImm(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - Priv(mnem, _machInst, __opClass), imm(SIMM13) - { - } - - int32_t imm; - }; - - /** - * Base class for user mode "tick" access with immediates. - */ - class PrivTickImm : public PrivTick - { - protected: - // Constructor - PrivTickImm(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - PrivTick(mnem, _machInst, __opClass), imm(SIMM13) - { - } - - int32_t imm; - }; -}}; - -output decoder {{ - std::string Priv::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - return "Privileged Instruction"; - } - - std::string PrivTick::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - return "Regular access to Tick"; - } -}}; - -def template PrivExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - %(op_decl)s; - %(op_rd)s; - - //If the processor isn't in privileged mode, fault out right away - if(%(check)s) - return new PrivilegedAction; - - %(code)s; - %(op_wb)s; - return NoFault; - } -}}; - -let {{ - def doPrivFormat(code, checkCode, name, Name, opt_flags): - (usesImm, code, immCode, - rString, iString) = splitOutImm(code) - iop = InstObjParams(name, Name, 'Priv', code, - opt_flags, ("check", checkCode)) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = PrivExecute.subst(iop) - if usesImm: - imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', - immCode, opt_flags, ("check", checkCode)) - header_output += BasicDeclare.subst(imm_iop) - decoder_output += BasicConstructor.subst(imm_iop) - exec_output += PrivExecute.subst(imm_iop) - decode_block = ROrImmDecode.subst(iop) - else: - decode_block = BasicDecode.subst(iop) - return (header_output, decoder_output, exec_output, decode_block) -}}; - -// Primary format for integer operate instructions: -def format Priv(code, *opt_flags) {{ - checkCode = "(!PstatePriv)" - (header_output, decoder_output, - exec_output, decode_block) = doPrivFormat(code, - checkCode, name, Name, opt_flags) -}}; - -// Primary format for integer operate instructions: -def format PrivTick(code, *opt_flags) {{ - checkCode = "(!PstatePriv && TickNpt)" - (header_output, decoder_output, - exec_output, decode_block) = doPrivFormat(code, - checkCode, name, Name, opt_flags) -}}; diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa deleted file mode 100644 index f6a45ca48..000000000 --- a/arch/sparc/isa/formats/trap.isa +++ /dev/null @@ -1,64 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Trap instructions -// - -output header {{ - /** - * Base class for trap instructions, - * or instructions that always fault. - */ - class Trap : public SparcStaticInst - { - protected: - - // Constructor - Trap(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - SparcStaticInst(mnem, _machInst, __opClass), trapNum(SW_TRAP) - { - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - - int trapNum; - }; -}}; - -output decoder {{ - std::string Trap::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - - printMnemonic(response, mnemonic); - ccprintf(response, " "); - printReg(response, _srcRegIdx[0]); - ccprintf(response, ", 0x%x", trapNum); - ccprintf(response, ", or "); - printReg(response, _srcRegIdx[1]); - return response.str(); - } -}}; - -def template TrapExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - %(op_decl)s; - %(op_rd)s; - %(code)s - return fault; - } -}}; - -def format Trap(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'Trap', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = TrapExecute.subst(iop) -}}; diff --git a/arch/sparc/isa/formats/unknown.isa b/arch/sparc/isa/formats/unknown.isa deleted file mode 100644 index 223111905..000000000 --- a/arch/sparc/isa/formats/unknown.isa +++ /dev/null @@ -1,46 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Unknown instructions -// - -output header {{ - /** - * Class for Unknown/Illegal instructions - */ - class Unknown : public SparcStaticInst - { - public: - - // Constructor - Unknown(ExtMachInst _machInst) : - SparcStaticInst("unknown", _machInst, No_OpClass) - { - } - - %(BasicExecDeclare)s - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - - }; -}}; - -output decoder {{ - std::string Unknown::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - return "Unknown instruction"; - } -}}; - -output exec {{ - Fault Unknown::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - return new IllegalInstruction; - } -}}; - -def format Unknown() {{ - decode_block = 'return new Unknown(machInst);\n' -}}; |