diff options
Diffstat (limited to 'arch/sparc/isa/formats')
-rw-r--r-- | arch/sparc/isa/formats/branch.isa | 23 | ||||
-rw-r--r-- | arch/sparc/isa/formats/integerop.isa | 31 | ||||
-rw-r--r-- | arch/sparc/isa/formats/mem.isa | 11 |
3 files changed, 57 insertions, 8 deletions
diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa index b76f7a9f6..37bdb9402 100644 --- a/arch/sparc/isa/formats/branch.isa +++ b/arch/sparc/isa/formats/branch.isa @@ -194,7 +194,7 @@ output decoder {{ { ccprintf(response, " <%s", symbol); if(symbolAddr != target) - ccprintf(response, "+0x%x>", target - symbolAddr); + ccprintf(response, "+%d>", target - symbolAddr); else ccprintf(response, ">"); } @@ -226,8 +226,25 @@ def template BranchExecute {{ } }}; +let {{ + handle_annul = ''' + { + if(A) + { + NPC = xc->readNextNPC(); + NNPC = NPC + 4; + } + else + { + NPC = xc->readNextPC(); + NNPC = xc->readNextNPC(); + } + }''' +}}; + // Primary format for branch instructions: def format Branch(code, *opt_flags) {{ + code = re.sub(r'handle_annul', handle_annul, code) (usesImm, code, immCode, rString, iString) = splitOutImm(code) iop = InstObjParams(name, Name, 'Branch', code, opt_flags) @@ -247,6 +264,7 @@ def format Branch(code, *opt_flags) {{ // Primary format for branch instructions: def format Branch19(code, *opt_flags) {{ + code = re.sub(r'handle_annul', handle_annul, code) codeBlk = CodeBlock(code) iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags) header_output = BasicDeclare.subst(iop) @@ -257,6 +275,7 @@ def format Branch19(code, *opt_flags) {{ // Primary format for branch instructions: def format Branch22(code, *opt_flags) {{ + code = re.sub(r'handle_annul', handle_annul, code) codeBlk = CodeBlock(code) iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags) header_output = BasicDeclare.subst(iop) @@ -267,6 +286,7 @@ def format Branch22(code, *opt_flags) {{ // Primary format for branch instructions: def format Branch30(code, *opt_flags) {{ + code = re.sub(r'handle_annul', handle_annul, code) codeBlk = CodeBlock(code) iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags) header_output = BasicDeclare.subst(iop) @@ -277,6 +297,7 @@ def format Branch30(code, *opt_flags) {{ // Primary format for branch instructions: def format BranchSplit(code, *opt_flags) {{ + code = re.sub(r'handle_annul', handle_annul, code) codeBlk = CodeBlock(code) iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags) header_output = BasicDeclare.subst(iop) diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa index 401af2e51..881154b67 100644 --- a/arch/sparc/isa/formats/integerop.isa +++ b/arch/sparc/isa/formats/integerop.isa @@ -62,6 +62,21 @@ output header {{ }; /** + * Base class for 11 bit immediate integer operations. + */ + class IntOpImm11 : public IntOpImm + { + protected: + // Constructor + IntOpImm11(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + IntOpImm(mnem, _machInst, __opClass) + { + imm = sign_ext(SIMM11, 11); + } + }; + + /** * Base class for 13 bit immediate integer operations. */ class IntOpImm13 : public IntOpImm @@ -271,14 +286,22 @@ let {{ return (header_output, decoder_output, exec_output, decode_block) calcCcCode = ''' - CcrIccN = (Rd >> 63) & 1; - CcrIccZ = (Rd == 0); - CcrXccN = (Rd >> 31) & 1; - CcrXccZ = ((Rd & 0xFFFFFFFF) == 0); + CcrIccN = (Rd >> 31) & 1; + CcrIccZ = ((Rd & 0xFFFFFFFF) == 0); + CcrXccN = (Rd >> 63) & 1; + CcrXccZ = (Rd == 0); CcrIccV = %(ivValue)s; CcrIccC = %(icValue)s; CcrXccV = %(xvValue)s; CcrXccC = %(xcValue)s; + DPRINTF(Sparc, "in = %%d\\n", CcrIccN); + DPRINTF(Sparc, "iz = %%d\\n", CcrIccZ); + DPRINTF(Sparc, "xn = %%d\\n", CcrXccN); + DPRINTF(Sparc, "xz = %%d\\n", CcrXccZ); + DPRINTF(Sparc, "iv = %%d\\n", CcrIccV); + DPRINTF(Sparc, "ic = %%d\\n", CcrIccC); + DPRINTF(Sparc, "xv = %%d\\n", CcrXccV); + DPRINTF(Sparc, "xc = %%d\\n", CcrXccC); ''' }}; diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa index e15349c7b..12dae57e5 100644 --- a/arch/sparc/isa/formats/mem.isa +++ b/arch/sparc/isa/formats/mem.isa @@ -30,8 +30,9 @@ output header {{ // Constructor MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - Mem(mnem, _machInst, __opClass), imm(SIMM13) + Mem(mnem, _machInst, __opClass) { + imm = sign_ext(SIMM13, 13); } std::string generateDisassembly(Addr pc, @@ -84,7 +85,10 @@ output decoder {{ } ccprintf(response, "[ "); printReg(response, _srcRegIdx[!save ? 0 : 1]); - ccprintf(response, " + 0x%x ]", imm); + if(imm >= 0) + ccprintf(response, " + 0x%x ]", imm); + else + ccprintf(response, " + -0x%x ]", -imm); if(load) { ccprintf(response, ", "); @@ -104,6 +108,7 @@ def template MemExecute {{ %(op_decl)s; %(op_rd)s; %(ea_code)s; + DPRINTF(Sparc, "The address is 0x%x\n", EA); %(load)s; %(code)s; %(store)s; @@ -126,7 +131,7 @@ let {{ def doMemFormat(code, load, store, name, Name, opt_flags): addrCalcReg = 'EA = Rs1 + Rs2;' - addrCalcImm = 'EA = Rs1 + SIMM13;' + addrCalcImm = 'EA = Rs1 + imm;' iop = InstObjParams(name, Name, 'Mem', code, opt_flags, ("ea_code", addrCalcReg), ("load", load), ("store", store)) |