diff options
Diffstat (limited to 'arch/sparc/isa/operands.isa')
| -rw-r--r-- | arch/sparc/isa/operands.isa | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa index 0d521fae0..17e58ad59 100644 --- a/arch/sparc/isa/operands.isa +++ b/arch/sparc/isa/operands.isa @@ -25,11 +25,13 @@ def operands {{ #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), - #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), + 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 4), + 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 4), #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), - 'R0': ('IntReg', 'udw', '0', None, 1), - 'R16': ('IntReg', 'udw', '16', None, 1), + 'R0': ('IntReg', 'udw', '0', None, 6), + 'R15': ('IntReg', 'udw', '15', 'IsInteger', 7), + 'R16': ('IntReg', 'udw', '16', None, 8), # Control registers 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1), 'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2), @@ -57,7 +59,7 @@ def operands {{ 'CcrXccC': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22), 'CcrXccV': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23), 'CcrXccZ': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24), - 'CcrXccN': ('ControlReg', 'udw', 'MISCREG_XCC_N', None, 25), + 'CcrXccN': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_N', None, 25), 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26), 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27), #'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28), |