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-rw-r--r--arch/sparc/isa/base.isa46
-rw-r--r--arch/sparc/isa/decoder.isa790
-rw-r--r--arch/sparc/isa/formats.isa22
-rw-r--r--arch/sparc/isa/formats/branch.isa241
-rw-r--r--arch/sparc/isa/formats/integerop.isa291
-rw-r--r--arch/sparc/isa/formats/mem.isa130
-rw-r--r--arch/sparc/isa/formats/nop.isa (renamed from arch/sparc/isa/formats/noop.isa)34
-rw-r--r--arch/sparc/isa/formats/priv.isa80
-rw-r--r--arch/sparc/isa/formats/trap.isa6
-rw-r--r--arch/sparc/isa/formats/unknown.isa2
-rw-r--r--arch/sparc/isa/includes.isa1
-rw-r--r--arch/sparc/isa/main.isa12
-rw-r--r--arch/sparc/isa/operands.isa20
13 files changed, 1143 insertions, 532 deletions
diff --git a/arch/sparc/isa/base.isa b/arch/sparc/isa/base.isa
index 4721f728b..434426ffa 100644
--- a/arch/sparc/isa/base.isa
+++ b/arch/sparc/isa/base.isa
@@ -57,6 +57,12 @@ output header {{
};
bool passesCondition(uint32_t codes, uint32_t condition);
+
+ inline int64_t sign_ext(uint64_t data, int origWidth)
+ {
+ int shiftAmount = 64 - origWidth;
+ return (((int64_t)data) << shiftAmount) >> shiftAmount;
+ }
}};
def template ROrImmDecode {{
@@ -68,28 +74,46 @@ def template ROrImmDecode {{
let {{
def splitOutImm(code):
- matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>d{0,2})')
+ matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)')
rOrImmMatch = matcher.search(code)
if (rOrImmMatch == None):
- return (False, CodeBlock(code), None, '', '')
- rString = matcher.sub(r'(?P=rNum)', rOrImmMatch.string)
- iString = matcher.sub(r'(?P=iNum)', rOrImmMatch.string)
+ return (False, code, '', '', '')
+ rString = rOrImmMatch.group("rNum")
+ iString = rOrImmMatch.group("iNum")
orig_code = code
- code = matcher.sub(r'Rs(?P<rNum>)', orig_code)
+ code = matcher.sub('Rs' + rOrImmMatch.group("rNum"), orig_code)
imm_code = matcher.sub('imm', orig_code)
- return (True, CodeBlock(code), CodeBlock(imm_code), rString, iString)
+ return (True, code, imm_code, rString, iString)
}};
output decoder {{
+ inline void printMnemonic(std::ostream &os, const char * mnemonic)
+ {
+ ccprintf(os, "\t%s ", mnemonic);
+ }
+
void
SparcStaticInst::printReg(std::ostream &os, int reg) const
{
- if (reg < FP_Base_DepTag) {
- ccprintf(os, "r%d", reg);
- }
+ const int MaxGlobal = 8;
+ const int MaxOutput = 16;
+ const int MaxLocal = 24;
+ const int MaxInput = 32;
+ if (reg == FramePointerReg)
+ ccprintf(os, "%%fp");
+ else if (reg == StackPointerReg)
+ ccprintf(os, "%%sp");
+ else if(reg < MaxGlobal)
+ ccprintf(os, "%%g%d", reg);
+ else if(reg < MaxOutput)
+ ccprintf(os, "%%o%d", reg - MaxGlobal);
+ else if(reg < MaxLocal)
+ ccprintf(os, "%%l%d", reg - MaxOutput);
+ else if(reg < MaxInput)
+ ccprintf(os, "%%i%d", reg - MaxLocal);
else {
- ccprintf(os, "f%d", reg - FP_Base_DepTag);
+ ccprintf(os, "%%f%d", reg - FP_Base_DepTag);
}
}
@@ -98,7 +122,7 @@ output decoder {{
{
std::stringstream ss;
- ccprintf(ss, "%-10s ", mnemonic);
+ printMnemonic(ss, mnemonic);
// just print the first two source regs... if there's
// a third one, it's a read-modify-write dest (Rc),
diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
index a1bbf8984..b4084518c 100644
--- a/arch/sparc/isa/decoder.isa
+++ b/arch/sparc/isa/decoder.isa
@@ -7,61 +7,64 @@ decode OP default Unknown::unknown()
{
0x0: decode OP2
{
- format Branch
+ //Throw an illegal instruction acception
+ 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
+ 0x1: decode BPCC
{
- //Throw an illegal instruction acception
- 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
- 0x1: decode BPCC
+ format Branch19
{
0x0: bpcci({{
if(passesCondition(CcrIcc, COND2))
- ;//branchHere
+ NNPC = xc->readPC() + disp;
}});
0x2: bpccx({{
if(passesCondition(CcrXcc, COND2))
- ;//branchHere
+ NNPC = xc->readPC() + disp;
}});
}
- 0x2: bicc({{
- if(passesCondition(CcrIcc, COND2))
- ;//branchHere
- }});
- 0x3: decode RCOND2
+ }
+ 0x2: Branch22::bicc({{
+ if(passesCondition(CcrIcc, COND2))
+ NNPC = xc->readPC() + disp;
+ }});
+ 0x3: decode RCOND2
+ {
+ format BranchSplit
{
0x1: bpreq({{
if(Rs1 == 0)
- ;//branchHere
+ NNPC = xc->readPC() + disp;
}});
0x2: bprle({{
if(Rs1 <= 0)
- ;//branchHere
+ NNPC = xc->readPC() + disp;
}});
0x3: bprl({{
if(Rs1 < 0)
- ;//branchHere
+ NNPC = xc->readPC() + disp;
}});
0x5: bprne({{
if(Rs1 != 0)
- ;//branchHere
+ NNPC = xc->readPC() + disp;
}});
0x6: bprg({{
if(Rs1 > 0)
- ;//branchHere
+ NNPC = xc->readPC() + disp;
}});
0x7: bprge({{
if(Rs1 >= 0)
- ;//branchHere
+ NNPC = xc->readPC() + disp;
}});
}
- //SETHI (or NOP if rd == 0 and imm == 0)
- 0x4: IntOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
- 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
- 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
}
+ //SETHI (or NOP if rd == 0 and imm == 0)
+ 0x4: SetHi::sethi({{Rd = imm;}});
+ 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
+ 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
}
- 0x1: Branch::call({{
- //branch here
- Rd = xc->readPC();
+ 0x1: Branch30::call({{
+ R15 = xc->readPC();
+ NNPC = R15 + disp;
}});
0x2: decode OP3 {
format IntOp {
@@ -69,74 +72,73 @@ decode OP default Unknown::unknown()
0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}});
0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}});
0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}});
- 0x04: sub({{Rd = Rs1.sdw + (~Rs2_or_imm)+1;}});
- 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm;}});
- 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm;}});
- 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm);}});
- 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm + CcrIccC;}});
- 0x09: mulx({{Rd = Rs1 * Rs2_or_imm;}});
+ 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
+ 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}});
+ 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}});
+ 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}});
+ 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + CcrIccC;}});
+ 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}});
0x0A: umul({{
- Rd = Rs1.udw<31:0> * Rs2_or_imm<31:0>;
+ Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
YValue = Rd<63:32>;
}});
0x0B: smul({{
- Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm<31:0>;
+ Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
YValue = Rd.sdw;
}});
- 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm) + 1 + CcrIccC;}});
+ 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + CcrIccC;}});
0x0D: udivx({{
- if(val2 == 0) fault = new DivisionByZero;
- else Rd.udw = Rs1.udw / Rs2_or_imm;
+ if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
+ else Rd.udw = Rs1.udw / Rs2_or_imm13;
}});
0x0E: udiv({{
- uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>);
- if(Rs2_or_imm.udw == 0) fault = new DivisionByZero;
+ if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
else
{
- Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm.udw;
+ Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
if(Rd.udw >> 32 != 0)
Rd.udw = 0xFFFFFFFF;
}
}});
0x0F: sdiv({{
- if(val2 == 0)
+ if(Rs2_or_imm13 == 0)
fault = new DivisionByZero;
else
{
- Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm;
+ Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm13;
if(Rd.udw<63:31> != 0)
Rd.udw = 0x7FFFFFFF;
else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
Rd.udw = 0xFFFFFFFF80000000;
}
- }});//SDIV
+ }});
}
format IntOpCc {
0x10: addcc({{
- int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
+ int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2;}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
- );//ADDcc
+ );
0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
0x14: subcc({{
- int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2);
+ int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 - val2;}},
- {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
+ {{((Rs1 & 0xFFFFFFFF - val2 & 0xFFFFFFFF) >> 31)}},
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
- {{((Rs1 >> 1) + (~val2) >> 1) +
+ {{(((Rs1 >> 1) + (~val2) >> 1) +
((Rs1 | ~val2) & 0x1))<63:>}},
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
- );//SUBcc
+ );
0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
0x18: addccc({{
- int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
+ int64_t resTemp, val2 = Rs2_or_imm13;
int64_t carryin = CcrIccC;
Rd = resTemp = Rs1 + val2 + carryin;}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
@@ -145,83 +147,84 @@ decode OP default Unknown::unknown()
{{((Rs1 >> 1) + (val2 >> 1) +
((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
- );//ADDCcc
+ );
0x1A: umulcc({{
- uint64_t resTemp, val2 = (I ? SIMM13 : Rs2);
+ uint64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
YValue = resTemp<63:32>;}},
- {{0}},{{0}},{{0}},{{0}});//UMULcc
+ {{0}},{{0}},{{0}},{{0}});
0x1B: smulcc({{
- int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
+ int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
- YValue = resTemp<63:32>;}}
- ,{{0}},{{0}},{{0}},{{0}});//SMULcc
+ YValue = resTemp<63:32>;}},
+ {{0}},{{0}},{{0}},{{0}});
0x1C: subccc({{
- int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2);
+ int64_t resTemp, val2 = Rs2_or_imm13;
int64_t carryin = CcrIccC;
Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
{{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
- {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
+ {{(((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
- );//SUBCcc
+ );
0x1D: udivxcc({{
- uint64_t val2 = (I ? SIMM13 : Rs2.udw);
- if(val2 == 0) fault = new DivisionByZero;
- else Rd.udw = Rs1.udw / val2;}}
- ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
+ if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
+ else Rd = Rs1.udw / Rs2_or_imm13;}}
+ ,{{0}},{{0}},{{0}},{{0}});
0x1E: udivcc({{
- uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>);
+ uint32_t resTemp, val2 = Rs2_or_imm13;
+ int32_t overflow;
if(val2 == 0) fault = new DivisionByZero;
else
{
resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2;
- int32_t overflow = (resTemp<63:32> != 0);
- if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
- else rd.udw = resTemp;
+ overflow = (resTemp<63:32> != 0);
+ if(overflow) Rd = resTemp = 0xFFFFFFFF;
+ else Rd = resTemp;
} }},
{{0}},
{{overflow}},
{{0}},
{{0}}
- );//UDIVcc
+ );
0x1F: sdivcc({{
- int32_t resTemp, val2 = (I ? SIMM13 : Rs2.sdw<31:0>);
+ int32_t resTemp, val2 = Rs2_or_imm13;
+ int32_t overflow, underflow;
if(val2 == 0) fault = new DivisionByZero;
else
{
- Rd.sdw = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2;
- int32_t overflow = (resTemp<63:31> != 0);
- int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
- if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
- else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
- else rd.udw = resTemp;
+ Rd = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2;
+ overflow = (resTemp<63:31> != 0);
+ underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
+ if(overflow) Rd = resTemp = 0x7FFFFFFF;
+ else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000;
+ else Rd = resTemp;
} }},
{{0}},
{{overflow || underflow}},
{{0}},
{{0}}
- );//SDIVcc
+ );
0x20: taddcc({{
- int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
+ int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
{{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
- );//TADDcc
+ );
0x21: tsubcc({{
- int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
+ int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
- {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+ {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
{{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
- );//TSUBcc
+ );
0x22: taddcctv({{
- int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
+ int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
if(overflow) fault = new TagOverflow;}},
@@ -229,9 +232,9 @@ decode OP default Unknown::unknown()
{{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
- );//TADDccTV
+ );
0x23: tsubcctv({{
- int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
+ int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
if(overflow) fault = new TagOverflow;}},
@@ -239,12 +242,12 @@ decode OP default Unknown::unknown()
{{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
- );//TSUBccTV
+ );
0x24: mulscc({{
- int64_t resTemp, multiplicand = (I ? SIMM13 : Rs2);
+ int64_t resTemp, multiplicand = Rs2_or_imm13;
int32_t multiplier = Rs1<31:0>;
int32_t savedLSB = Rs1<0:>;
- multiplier = multipler<31:1> |
+ multiplier = multiplier<31:1> |
((CcrIccN
^ CcrIccV) << 32);
if(!YValue<0:>)
@@ -255,286 +258,387 @@ decode OP default Unknown::unknown()
{{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
{{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
{{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
- );//MULScc
+ );
+ }
+ format IntOp
+ {
+ 0x25: decode X {
+ 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
+ 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
}
- format IntOp
- {
- 0x25: decode X {
- 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
- 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
- }
- 0x26: decode X {
- 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
- 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
- }
- 0x27: decode X {
- 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
- 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
- }
- 0x28: decode RS1 {
- 0x0: rdy({{Rd = YValue;}}); //RDY
- 0x2: rdccr({{Rd = Ccr;}}); //RDCCR
- 0x3: rdasi({{Rd = Asi;}}); //RDASI
- 0x4: PrivTick::rdtick({{Rd = Tick;}});
- 0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
- 0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS
- 0xF: decode I {
- 0x0: Noop::membar({{//Membar isn't needed yet}});
- 0x1: Noop::stbar({{//Stbar isn't needed yet}});
- }
- }
- 0x2A: decode RS1 {
- format Priv
- {
- 0x0: rdprtpc({{
- Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
- }});
- 0x1: rdprtnpc({{
- Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
- }});
- 0x2: rdprtstate({{
- Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl);
- }});
- 0x3: rdprtt({{
- Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl);
- }});
- 0x4: rdprtick({{Rd = Tick;}});
- 0x5: rdprtba({{Rd = Tba;}});
- 0x6: rdprpstate({{Rd = Pstate;}});
- 0x7: rdprtl({{Rd = Tl;}});
- 0x8: rdprpil({{Rd = Pil;}});
- 0x9: rdprcwp({{Rd = Cwp;}});
- 0xA: rdprcansave({{Rd = Cansave;}});
- 0xB: rdprcanrestore({{Rd = CanRestore;}});
- 0xC: rdprcleanwin({{Rd = Cleanwin;}});
- 0xD: rdprotherwin({{Rd = Otherwin;}});
- 0xE: rdprwstate({{Rd = Wstate;}});
- }
- //The floating point queue isn't implemented right now.
- 0xF: Trap::rdprfq({{fault = IllegalInstruction;}});
- 0x1F: Priv::rdprver({{Rd = Ver;}});
+ 0x26: decode X {
+ 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
+ 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
+ }
+ 0x27: decode X {
+ 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
+ 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
+ }
+ 0x28: decode RS1 {
+ 0x0: rdy({{Rd = YValue;}});
+ 0x2: rdccr({{Rd = Ccr;}});
+ 0x3: rdasi({{Rd = Asi;}});
+ 0x4: PrivTick::rdtick({{Rd = Tick;}});
+ 0x5: rdpc({{Rd = xc->readPC();}});
+ 0x6: rdfprs({{Rd = Fprs;}});
+ 0xF: decode I {
+ 0x0: Nop::membar({{/*Membar isn't needed yet*/}});
+ 0x1: Nop::stbar({{/*Stbar isn't needed yet*/}});
}
- 0x2B: BasicOperate::flushw({{//window toilet}}); //FLUSHW
- 0x2C: decode MOVCC3
+ }
+ 0x2A: decode RS1 {
+ format Priv
{
- 0x0: Trap::movccfcc({{fault = new FpDisabled}});
- 0x1: decode CC
- {
- 0x0: movcci({{
- if(passesCondition(CcrIcc, COND4))
- Rd = (I ? SIMM11 : RS2);
- }});
- 0x2: movccx({{
- if(passesCondition(CcrXcc, COND4))
- Rd = (I ? SIMM11 : RS2);
- }});
- }
- }
- 0x2D: sdivx({{
- if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
- else Rd.sdw = Rs1.sdw / Rs2_or_imm13;
- }});//SDIVX
- 0x2E: decode RS1 {
- 0x0: IntOp::popc({{
- int64_t count = 0, val2 = Rs2_or_imm;
- uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
- for(unsigned int x = 0; x < 16; x++)
- {
- count += oneBits[Rs2_or_imm13 & 0xF];
- val2 >> 4;
- }
- }});//POPC
+ 0x0: rdprtpc({{
+ Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
+ }});
+ 0x1: rdprtnpc({{
+ Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
+ }});
+ 0x2: rdprtstate({{
+ Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl);
+ }});
+ 0x3: rdprtt({{
+ Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl);
+ }});
+ 0x4: rdprtick({{Rd = Tick;}});
+ 0x5: rdprtba({{Rd = Tba;}});
+ 0x6: rdprpstate({{Rd = Pstate;}});
+ 0x7: rdprtl({{Rd = Tl;}});
+ 0x8: rdprpil({{Rd = Pil;}});
+ 0x9: rdprcwp({{Rd = Cwp;}});
+ 0xA: rdprcansave({{Rd = Cansave;}});
+ 0xB: rdprcanrestore({{Rd = Canrestore;}});
+ 0xC: rdprcleanwin({{Rd = Cleanwin;}});
+ 0xD: rdprotherwin({{Rd = Otherwin;}});
+ 0xE: rdprwstate({{Rd = Wstate;}});
}
- 0x2F: decode RCOND3
+ //The floating point queue isn't implemented right now.
+ 0xF: Trap::rdprfq({{fault = new IllegalInstruction;}});
+ 0x1F: Priv::rdprver({{Rd = Ver;}});
+ }
+ 0x2B: BasicOperate::flushw({{
+ if(NWindows - 2 - Cansave == 0)
{
- 0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}});
- 0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}});
- 0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}});
- 0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}});
- 0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}});
- 0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}});
+ if(Otherwin)
+ fault = new SpillNOther(WstateOther);
+ else
+ fault = new SpillNNormal(WstateNormal);
}
- 0x30: decode RD {
- 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
- 0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
- 0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
- 0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}});
- 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
- }
- 0x31: decode FCN {
- 0x0: BasicOperate::saved({{//Boogy Boogy}}); //SAVED
- 0x1: BasicOperate::restored({{//Boogy Boogy}}); //RESTORED
+ }});
+ 0x2C: decode MOVCC3
+ {
+ 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
+ 0x1: decode CC
+ {
+ 0x0: movcci({{
+ if(passesCondition(CcrIcc, COND4))
+ Rd = (I ? SIMM11 : RS2);
+ }});
+ 0x2: movccx({{
+ if(passesCondition(CcrXcc, COND4))
+ Rd = (I ? SIMM11 : RS2);
+ }});
}
- 0x32: decode RD {
- format Priv
+ }
+ 0x2D: sdivx({{
+ if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
+ else Rd.sdw = Rs1.sdw / Rs2_or_imm13;
+ }});
+ 0x2E: decode RS1 {
+ 0x0: IntOp::popc({{
+ int64_t count = 0;
+ uint64_t temp = Rs2_or_imm13;
+ //Count the 1s in the front 4bits until none are left
+ uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
+ while(temp)
{
- 0x0: wrprtpc({{
- xc->setMiscReg(MISCREG_TPC_BASE + Tl,
- Rs1 ^ Rs2_or_imm13);
- }});
- 0x1: wrprtnpc({{
- xc->setMiscReg(MISCREG_TNPC_BASE + Tl,
- Rs1 ^ Rs2_or_imm13);
- }});
- 0x2: wrprtstate({{
- xc->setMiscReg(MISCREG_TSTATE_BASE + Tl,
- Rs1 ^ Rs2_or_imm13);
- }});
- 0x3: wrprtt({{
- xc->setMiscReg(MISCREG_TT_BASE + Tl,
- Rs1 ^ Rs2_or_imm13);
- }});
- 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
- 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
- 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
- 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}});
- 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
- 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
- 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
- 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
- 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
- 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
- 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
+ count += oneBits[temp & 0xF];
+ temp = temp >> 4;
}
+ }});
+ }
+ 0x2F: decode RCOND3
+ {
+ 0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}});
+ 0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}});
+ 0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}});
+ 0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}});
+ 0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}});
+ 0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}});
+ }
+ 0x30: decode RD {
+ 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
+ 0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
+ 0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
+ 0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}});
+ 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
+ }
+ 0x31: decode FCN {
+ 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
+ 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
+ }
+ 0x32: decode RD {
+ format Priv
+ {
+ 0x0: wrprtpc({{
+ xc->setMiscReg(MISCREG_TPC_BASE + Tl,
+ Rs1 ^ Rs2_or_imm13);
+ }});
+ 0x1: wrprtnpc({{
+ xc->setMiscReg(MISCREG_TNPC_BASE + Tl,
+ Rs1 ^ Rs2_or_imm13);
+ }});
+ 0x2: wrprtstate({{
+ xc->setMiscReg(MISCREG_TSTATE_BASE + Tl,
+ Rs1 ^ Rs2_or_imm13);
+ }});
+ 0x3: wrprtt({{
+ xc->setMiscReg(MISCREG_TT_BASE + Tl,
+ Rs1 ^ Rs2_or_imm13);
+ }});
+ 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
+ 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
+ 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
+ 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}});
+ 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
+ 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
+ 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
+ 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
+ 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
+ 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
+ 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
}
-
- 0x34: Trap::fpop1({{fault = new FpDisabled;}});
- 0x35: Trap::fpop2({{fault = new FpDisabled;}});
-
- 0x38: Branch::jmpl({{//Stuff}}); //JMPL
- 0x39: Branch::return({{//Other Stuff}}); //RETURN
- 0x3A: decode CC
+ }
+ 0x34: Trap::fpop1({{fault = new FpDisabled;}});
+ 0x35: Trap::fpop2({{fault = new FpDisabled;}});
+ 0x38: Branch::jmpl({{
+ Addr target = Rs1 + Rs2_or_imm13;
+ if(target & 0x3)
+ fault = new MemAddressNotAligned;
+ else
{
- 0x0: Trap::tcci({{
+ Rd = xc->readPC();
+ NNPC = target;
+ }
+ }});
+ 0x39: Branch::return({{
+ Addr target = Rs1 + Rs2_or_imm13;
+ if(target & 0x3)
+ fault = new MemAddressNotAligned;
+ else
+ NNPC = target;
+ //This needs to change the register window
+ //like restore does
+ }});
+ 0x3A: decode CC
+ {
+ 0x0: Trap::tcci({{
#if FULL_SYSTEM
- fault = new TrapInstruction;
+ fault = new TrapInstruction;
#else
- if(passesCondition(CcrIcc, machInst<25:28>))
- // At least glibc only uses trap 0,
- // solaris/sunos may use others
- assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
- xc->syscall();
+ if(passesCondition(CcrIcc, machInst<25:28>))
+ {
+ // At least glibc only uses trap 0,
+ // solaris/sunos may use others
+ assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
+ xc->syscall();
+ }
#endif
- }});
- 0x2: Trap::tccx({{
+ }});
+ 0x2: Trap::tccx({{
#if FULL_SYSTEM
- fault = new TrapInstruction;
+ fault = new TrapInstruction;
#else
- if(passesCondition(CcrXcc, machInst<25:28>))
- // At least glibc only uses trap 0,
- // solaris/sunos may use others
- assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
- xc->syscall();
+ if(passesCondition(CcrXcc, machInst<25:28>))
+ {
+ // At least glibc only uses trap 0,
+ // solaris/sunos may use others
+ assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
+ xc->syscall();
+ }
#endif
- }});
+ }});
+ }
+ 0x3B: Nop::flush({{/*Instruction memory flush*/}});
+ 0x3C: save({{
+ //CWP should be set directly so that it always happens
+ //Also, this will allow writing to the new window and
+ //reading from the old one
+ if(Cansave == 0)
+ {
+ if(Otherwin)
+ fault = new SpillNOther(WstateOther);
+ else
+ fault = new SpillNNormal(WstateNormal);
+ Cwp = (Cwp + 2) % NWindows;
+ }
+ else if(Cleanwin - Canrestore == 0)
+ {
+ Cwp = (Cwp + 1) % NWindows;
+ fault = new CleanWindow;
}
- 0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
- 0x3C: BasicOperate::save({{//leprechauns); //SAVE
- 0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
- 0x3E: decode FCN {
- 0x1: BasicOperate::done({{//Done thing}}); //DONE
- 0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
+ else
+ {
+ Cwp = (Cwp + 1) % NWindows;
+ Rd = Rs1 + Rs2_or_imm13;
+ Cansave--;
+ Canrestore++;
+ }
+ //This is here to make sure the CWP is written
+ //no matter what. This ensures that the results
+ //are written in the new window as well.
+ xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
+ }});
+ 0x3D: restore({{
+ //CWP should be set directly so that it always happens
+ //Also, this will allow writing to the new window and
+ //reading from the old one
+ Cwp = (Cwp - 1 + NWindows) % NWindows;
+ if(Canrestore == 0)
+ {
+ if(Otherwin)
+ fault = new FillNOther(WstateOther);
+ else
+ fault = new FillNNormal(WstateNormal);
}
+ else
+ {
+ Rd = Rs1 + Rs2_or_imm13;
+ Cansave++;
+ Canrestore--;
+ }
+ //This is here to make sure the CWP is written
+ //no matter what. This ensures that the results
+ //are written in the new window as well.
+ xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
+ }});
+ 0x3E: decode FCN {
+ 0x0: Priv::done({{
+ if(Tl == 0)
+ return new IllegalInstruction;
+ Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl);
+ Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl);
+ Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl);
+ Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl);
+ NPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
+ NNPC = NPC + 4;
+ Tl = Tl - 1;
+ }});
+ 0x1: BasicOperate::retry({{
+ if(Tl == 0)
+ return new IllegalInstruction;
+ Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl);
+ Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl);
+ Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl);
+ Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl);
+ NPC = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
+ NNPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
+ Tl = Tl - 1;
+ }});
}
+ }
}
0x3: decode OP3 {
- format Mem {
- 0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW
- 0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
- 0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
- 0x03: ldd({{
- uint64_t val = Mem.udw;
- setIntReg(RD & (~1), val<31:0>);
- setIntReg(RD | 1, val<63:32>);
- }});//LDD
- 0x04: stw({{Mem.sw = Rd.sw;}}); //STW
- 0x05: stb({{Mem.sb = Rd.sb;}}); //STB
- 0x06: sth({{Mem.shw = Rd.shw;}}); //STH
- 0x07: std({{
- Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
- }});//STD
- 0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
- 0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
- 0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH
- 0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX
-
- 0x0D: ldstub({{
- Rd.ub = Mem.ub;
- Mem.ub = 0xFF;
- }}); //LDSTUB
- 0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
- 0x0F: swap({{
- uint32_t temp = Rd.uw;
- Rd.uw = Mem.uw;
- Mem.uw = temp;
- }}); //SWAP
- 0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA
- 0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
- 0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
- 0x13: ldda({{
- uint64_t val = Mem.udw;
- setIntReg(RD & (~1), val<31:0>);
- setIntReg(RD | 1, val<63:32>);
- }}); //LDDA
- 0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
- 0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
- 0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
- 0x17: stda({{
- Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
- }}); //STDA
- 0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
- 0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
- 0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA
- 0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA
-
- 0x1D: ldstuba({{
- Rd.ub = Mem.ub;
- Mem.ub = 0xFF;
- }}); //LDSTUBA
- 0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
- 0x1F: swapa({{
- uint32_t temp = Rd.uw;
- Rd.uw = Mem.uw;
- Mem.uw = temp;
- }}); //SWAPA
- 0x20: Trap::ldf({{fault = new FpDisabled;}});
- 0x21: decode X {
- 0x0: Trap::ldfsr({{fault = new FpDisabled;}});
- 0x1: Trap::ldxfsr({{fault = new FpDisabled;}});
- }
- 0x22: Trap::ldqf({{fault = new FpDisabled;}});
- 0x23: Trap::lddf({{fault = new FpDisabled;}});
- 0x24: Trap::stf({{fault = new FpDisabled;}});
- 0x25: decode X {
- 0x0: Trap::stfsr({{fault = new FpDisabled;}});
- 0x1: Trap::stxfsr({{fault = new FpDisabled;}});
- }
- 0x26: Trap::stqf({{fault = new FpDisabled;}});
- 0x27: Trap::stdf({{fault = new FpDisabled;}});
-
- 0x2D: Noop::prefetch({{ }}); //PREFETCH
-
- 0x30: Trap::ldfa({{return new FpDisabled;}});
-
- 0x32: Trap::ldqfa({{fault = new FpDisabled;}});
- 0x33: Trap::lddfa({{fault = new FpDisabled;}});
- 0x34: Trap::stfa({{fault = new FpDisabled;}});
- 0x35: Trap::stqfa({{fault = new FpDisabled;}});
- 0x36: Trap::stdfa({{fault = new FpDisabled;}});
-
- 0x3C: Cas::casa(
- {{uint64_t val = Mem.uw;
- if(Rs2.uw == val)
- Mem.uw = Rd.uw;
- Rd.uw = val;
- }}); //CASA
- 0x3D: Noop::prefetcha({{ }}); //PREFETCHA
- 0x3E: Cas::casxa({{
- uint64_t val = Mem.udw;
- if(Rs2 == val)
- Mem.udw = Rd;
- Rd = val;
- }}); //CASXA
+ format Load {
+ 0x00: lduw({{Rd = Mem;}}, {{32}});
+ 0x01: ldub({{Rd = Mem;}}, {{8}});
+ 0x02: lduh({{Rd = Mem;}}, {{16}});
+ 0x03: ldd({{
+ uint64_t val = Mem;
+ RdLow = val<31:0>;
+ RdHigh = val<63:32>;
+ }}, {{64}});
+ }
+ format Store {
+ 0x04: stw({{Mem = Rd.sw;}}, {{32}});
+ 0x05: stb({{Mem = Rd.sb;}}, {{8}});
+ 0x06: sth({{Mem = Rd.shw;}}, {{16}});
+ 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
+ }
+ format Load {
+ 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}});
+ 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}});
+ 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}});
+ 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}});
+ 0x0D: ldstub({{
+ Rd = Mem;
+ Mem = 0xFF;
+ }}, {{8}});
+ }
+ 0x0E: Store::stx({{Mem = Rd}}, {{64}});
+ 0x0F: LoadStore::swap({{
+ uint32_t temp = Rd;
+ Rd = Mem;
+ Mem = temp;
+ }}, {{32}});
+ format Load {
+ 0x10: lduwa({{Rd = Mem;}}, {{32}});
+ 0x11: lduba({{Rd = Mem;}}, {{8}});
+ 0x12: lduha({{Rd = Mem;}}, {{16}});
+ 0x13: ldda({{
+ uint64_t val = Mem;
+ RdLow = val<31:0>;
+ RdHigh = val<63:32>;
+ }}, {{64}});
+ }
+ format Store {
+ 0x14: stwa({{Mem = Rd;}}, {{32}});
+ 0x15: stba({{Mem = Rd;}}, {{8}});
+ 0x16: stha({{Mem = Rd;}}, {{16}});
+ 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
+ }
+ format Load {
+ 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}});
+ 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}});
+ 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}});
+ 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}});
+ }
+ 0x1D: LoadStore::ldstuba({{
+ Rd = Mem;
+ Mem = 0xFF;
+ }}, {{8}});
+ 0x1E: Store::stxa({{Mem = Rd}}, {{64}});
+ 0x1F: LoadStore::swapa({{
+ uint32_t temp = Rd;
+ Rd = Mem;
+ Mem = temp;
+ }}, {{32}});
+ format Trap {
+ 0x20: ldf({{fault = new FpDisabled;}});
+ 0x21: decode X {
+ 0x0: ldfsr({{fault = new FpDisabled;}});
+ 0x1: ldxfsr({{fault = new FpDisabled;}});
+ }
+ 0x22: ldqf({{fault = new FpDisabled;}});
+ 0x23: lddf({{fault = new FpDisabled;}});
+ 0x24: stf({{fault = new FpDisabled;}});
+ 0x25: decode X {
+ 0x0: stfsr({{fault = new FpDisabled;}});
+ 0x1: stxfsr({{fault = new FpDisabled;}});
}
+ 0x26: stqf({{fault = new FpDisabled;}});
+ 0x27: stdf({{fault = new FpDisabled;}});
+ 0x2D: Nop::prefetch({{ }});
+ 0x30: ldfa({{return new FpDisabled;}});
+ 0x32: ldqfa({{fault = new FpDisabled;}});
+ 0x33: lddfa({{fault = new FpDisabled;}});
+ 0x34: stfa({{fault = new FpDisabled;}});
+ 0x35: stqfa({{fault = new FpDisabled;}});
+ 0x36: stdfa({{fault = new FpDisabled;}});
+ 0x3C: Cas::casa({{
+ uint64_t val = Mem.uw;
+ if(Rs2.uw == val)
+ Mem.uw = Rd.uw;
+ Rd.uw = val;
+ }});
+ 0x3D: Nop::prefetcha({{ }});
+ 0x3E: Cas::casxa({{
+ uint64_t val = Mem.udw;
+ if(Rs2 == val)
+ Mem.udw = Rd;
+ Rd = val;
+ }});
+ }
}
}
diff --git a/arch/sparc/isa/formats.isa b/arch/sparc/isa/formats.isa
index 9310ba3d3..17d68061b 100644
--- a/arch/sparc/isa/formats.isa
+++ b/arch/sparc/isa/formats.isa
@@ -1,28 +1,28 @@
//Include the basic format
//Templates from this format are used later
-##include "m5/arch/sparc/isa/formats/basic.isa"
+##include "formats/basic.isa"
+
+//Include the noop format
+##include "formats/nop.isa"
//Include the integerOp and integerOpCc format
-##include "m5/arch/sparc/isa/formats/integerop.isa"
+##include "formats/integerop.isa"
//Include the memory format
-##include "m5/arch/sparc/isa/formats/mem.isa"
+##include "formats/mem.isa"
//Include the compare and swap format
-##include "m5/arch/sparc/isa/formats/cas.isa"
+##include "formats/cas.isa"
//Include the trap format
-##include "m5/arch/sparc/isa/formats/trap.isa"
+##include "formats/trap.isa"
//Include the "unknown" format
-##include "m5/arch/sparc/isa/formats/unknown.isa"
+##include "formats/unknown.isa"
//Include the priveleged mode format
-##include "m5/arch/sparc/isa/formats/priv.isa"
+##include "formats/priv.isa"
//Include the branch format
-##include "m5/arch/sparc/isa/formats/branch.isa"
-
-//Include the noop format
-##include "m5/arch/sparc/isa/formats/noop.isa"
+##include "formats/branch.isa"
diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa
index b9dc960de..e4ce4592c 100644
--- a/arch/sparc/isa/formats/branch.isa
+++ b/arch/sparc/isa/formats/branch.isa
@@ -5,7 +5,7 @@
output header {{
/**
- * Base class for integer operations.
+ * Base class for branch operations.
*/
class Branch : public SparcStaticInst
{
@@ -19,12 +19,187 @@ output header {{
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
+
+ /**
+ * Base class for branch operations with an immediate displacement.
+ */
+ class BranchDisp : public Branch
+ {
+ protected:
+ // Constructor
+ BranchDisp(const char *mnem, MachInst _machInst,
+ OpClass __opClass) :
+ Branch(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ int32_t disp;
+ };
+
+ /**
+ * Base class for branches with 19 bit displacements.
+ */
+ class Branch19 : public BranchDisp
+ {
+ protected:
+ // Constructor
+ Branch19(const char *mnem, MachInst _machInst,
+ OpClass __opClass) :
+ BranchDisp(mnem, _machInst, __opClass)
+ {
+ disp = sign_ext(DISP19 << 2, 21);
+ }
+ };
+
+ /**
+ * Base class for branches with 22 bit displacements.
+ */
+ class Branch22 : public BranchDisp
+ {
+ protected:
+ // Constructor
+ Branch22(const char *mnem, MachInst _machInst,
+ OpClass __opClass) :
+ BranchDisp(mnem, _machInst, __opClass)
+ {
+ disp = sign_ext(DISP22 << 2, 24);
+ }
+ };
+
+ /**
+ * Base class for branches with 30 bit displacements.
+ */
+ class Branch30 : public BranchDisp
+ {
+ protected:
+ // Constructor
+ Branch30(const char *mnem, MachInst _machInst,
+ OpClass __opClass) :
+ BranchDisp(mnem, _machInst, __opClass)
+ {
+ disp = sign_ext(DISP30 << 2, 32);
+ }
+ };
+
+ /**
+ * Base class for 16bit split displacements.
+ */
+ class BranchSplit : public BranchDisp
+ {
+ protected:
+ // Constructor
+ BranchSplit(const char *mnem, MachInst _machInst,
+ OpClass __opClass) :
+ BranchDisp(mnem, _machInst, __opClass)
+ {
+ disp = sign_ext((D16HI << 16) | (D16LO << 2), 18);
+ }
+ };
+
+ /**
+ * Base class for branches that use an immediate and a register to
+ * compute their displacements.
+ */
+ class BranchImm13 : public Branch
+ {
+ protected:
+ // Constructor
+ BranchImm13(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ Branch(mnem, _machInst, __opClass), imm(sign_ext(SIMM13, 13))
+ {
+ }
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ int32_t imm;
+ };
}};
output decoder {{
- std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ std::string Branch::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
{
- return "Branch instruction\n";
+ std::stringstream response;
+
+ printMnemonic(response, mnemonic);
+
+ if (_numSrcRegs > 0)
+ {
+ printReg(response, _srcRegIdx[0]);
+ for(int x = 1; x < _numSrcRegs; x++)
+ {
+ response << ", ";
+ printReg(response, _srcRegIdx[x]);
+ }
+ }
+
+ if (_numDestRegs > 0)
+ {
+ if(_numSrcRegs > 0)
+ response << ", ";
+ printReg(response, _destRegIdx[0]);
+ }
+
+ return response.str();
+ }
+
+ std::string BranchImm13::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+
+ printMnemonic(response, mnemonic);
+
+ if (_numSrcRegs > 0)
+ {
+ printReg(response, _srcRegIdx[0]);
+ for(int x = 1; x < _numSrcRegs; x++)
+ {
+ response << ", ";
+ printReg(response, _srcRegIdx[x]);
+ }
+ }
+
+ if(_numSrcRegs > 0)
+ response << ", ";
+
+ ccprintf(response, "0x%x", imm);
+
+ if (_numDestRegs > 0)
+ {
+ response << ", ";
+ printReg(response, _destRegIdx[0]);
+ }
+
+ return response.str();
+ }
+
+ std::string BranchDisp::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+ std::string symbol;
+ Addr symbolAddr;
+
+ Addr target = disp + pc;
+
+ printMnemonic(response, mnemonic);
+ ccprintf(response, "0x%x", target);
+
+ if(symtab->findNearestSymbol(target, symbol, symbolAddr))
+ {
+ ccprintf(response, " <%s", symbol);
+ if(symbolAddr != target)
+ ccprintf(response, "+0x%x>", target - symbolAddr);
+ else
+ ccprintf(response, ">");
+ }
+
+ return response.str();
}
}};
@@ -37,6 +212,8 @@ def template BranchExecute {{
%(op_decl)s;
%(op_rd)s;
+
+ NNPC = xc->readNextNPC();
%(code)s;
if(fault == NoFault)
@@ -49,13 +226,63 @@ def template BranchExecute {{
}
}};
-// Primary format for integer operate instructions:
+// Primary format for branch instructions:
def format Branch(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+ (usesImm, code, immCode,
+ rString, iString) = splitOutImm(code)
+ codeBlk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'Branch', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
+ exec_output = BranchExecute.subst(iop)
+ if usesImm:
+ imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString,
+ codeBlk, opt_flags)
+ header_output += BasicDeclare.subst(imm_iop)
+ decoder_output += BasicConstructor.subst(imm_iop)
+ exec_output += BranchExecute.subst(imm_iop)
+ decode_block = ROrImmDecode.subst(iop)
+ else:
+ decode_block = BasicDecode.subst(iop)
+}};
+
+// Primary format for branch instructions:
+def format Branch19(code, *opt_flags) {{
+ codeBlk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ exec_output = BranchExecute.subst(iop)
decode_block = BasicDecode.subst(iop)
+}};
+
+// Primary format for branch instructions:
+def format Branch22(code, *opt_flags) {{
+ codeBlk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+}};
+
+// Primary format for branch instructions:
+def format Branch30(code, *opt_flags) {{
+ codeBlk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ exec_output = BranchExecute.subst(iop)
+ decode_block = BasicDecode.subst(iop)
}};
+
+// Primary format for branch instructions:
+def format BranchSplit(code, *opt_flags) {{
+ codeBlk = CodeBlock(code)
+ iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ exec_output = BranchExecute.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+}};
+
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
index e7bd4c2a4..f14f9e858 100644
--- a/arch/sparc/isa/formats/integerop.isa
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -11,103 +11,230 @@ output header {{
{
protected:
// Constructor
- IntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+ IntOp(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
+
+ virtual bool printPseudoOps(std::ostream &os, Addr pc,
+ const SymbolTable *symtab) const;
};
/**
- * Base class for 10 bit immediate integer operations.
+ * Base class for immediate integer operations.
*/
- class IntOpImm10 : public IntOp
+ class IntOpImm : public IntOp
{
protected:
// Constructor
- IntOpImm10(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- IntOp(mnem, _machInst, __opClass), imm(SIMM10)
+ IntOpImm(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ IntOp(mnem, _machInst, __opClass)
{
}
- uint32_t imm;
+ int32_t imm;
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ virtual bool printPseudoOps(std::ostream &os, Addr pc,
+ const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Base class for 10 bit immediate integer operations.
+ */
+ class IntOpImm10 : public IntOpImm
+ {
+ protected:
+ // Constructor
+ IntOpImm10(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ IntOpImm(mnem, _machInst, __opClass)
+ {
+ imm = sign_ext(SIMM10, 10);
+ }
};
/**
* Base class for 13 bit immediate integer operations.
*/
- class IntOpImm13 : public IntOp
+ class IntOpImm13 : public IntOpImm
{
protected:
// Constructor
- IntOpImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- IntOp(mnem, _machInst, __opClass), imm(SIMM13)
+ IntOpImm13(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ IntOpImm(mnem, _machInst, __opClass)
{
+ imm = sign_ext(SIMM13, 13);
}
+ };
- uint32_t imm;
+ /**
+ * Base class for sethi.
+ */
+ class SetHi : public IntOpImm
+ {
+ protected:
+ // Constructor
+ SetHi(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ IntOpImm(mnem, _machInst, __opClass)
+ {
+ imm = (IMM22 << 10) & 0xFFFFFC00;
+ }
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
};
}};
+def template SetHiDecode {{
+ {
+ if(RD == 0 && IMM22 == 0)
+ return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass));
+ else
+ return (SparcStaticInst *)(new %(class_name)s(machInst));
+ }
+}};
+
output decoder {{
- std::string IntOp::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
+
+ bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
+ const SymbolTable *symbab) const
{
- return "Integer instruction\n";
+ if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
+ {
+ printMnemonic(os, "mov");
+ if(_numSrcRegs > 0)
+ printReg(os, _srcRegIdx[1]);
+ ccprintf(os, ", ");
+ if(_numDestRegs > 0)
+ printReg(os, _destRegIdx[0]);
+
+ return true;
+ }
+ return false;
}
-}};
-def template IntOpExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
+ bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
+ const SymbolTable *symbab) const
{
- Fault fault = NoFault;
+ if(!strcmp(mnemonic, "or"))
+ {
+ if(_srcRegIdx[0] == 0)
+ {
+ if(imm == 0)
+ {
+ printMnemonic(os, "clr");
+ if(_numDestRegs > 0)
+ printReg(os, _destRegIdx[0]);
+ return true;
+ }
+ else
+ {
+ printMnemonic(os, "mov");
+ ccprintf(os, ", 0x%x, ", imm);
+ if(_numDestRegs > 0)
+ printReg(os, _destRegIdx[0]);
+ return true;
+ }
+ }
+ else if(imm == 0)
+ {
+ printMnemonic(os, "mov");
+ if(_numSrcRegs > 0)
+ printReg(os, _srcRegIdx[0]);
+ ccprintf(os, ", ");
+ if(_numDestRegs > 0)
+ printReg(os, _destRegIdx[0]);
+ return true;
+ }
+ }
+ return false;
+ }
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
+ std::string IntOp::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
- //Write the resulting state to the execution context
- if(fault == NoFault)
- %(op_wb)s;
- return fault;
+ if(!printPseudoOps(response, pc, symtab))
+ {
+ printMnemonic(response, mnemonic);
+ if (_numSrcRegs > 0)
+ {
+ printReg(response, _srcRegIdx[0]);
+ for(int x = 1; x < _numSrcRegs; x++)
+ {
+ response << ", ";
+ printReg(response, _srcRegIdx[x]);
+ }
+ }
+ if (_numDestRegs > 0)
+ {
+ if(_numSrcRegs > 0)
+ response << ", ";
+ printReg(response, _destRegIdx[0]);
+ }
+ }
+ return response.str();
}
-}};
-def template IntOpCcExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
+ std::string IntOpImm::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
{
- Fault fault;
-
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
+ std::stringstream response;
- //Write the resulting state to the execution context
- if(fault == NoFault)
+ if(!printPseudoOps(response, pc, symtab))
{
- %(op_wb)s;
- CcrIccN = Rd & (1 << 63);
- CcrIccZ = (Rd == 0);
- CcrIccV = ivValue;
- CcrIccC = icValue;
- CcrXccN = Rd & (1 << 31);
- CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
- CcrXccV = xvValue;
- CcrXccC = xcValue;
+ printMnemonic(response, mnemonic);
+ if (_numSrcRegs > 0)
+ {
+ printReg(response, _srcRegIdx[0]);
+ for(int x = 1; x < _numSrcRegs - 1; x++)
+ {
+ response << ", ";
+ printReg(response, _srcRegIdx[x]);
+ }
+ }
+ if(_numSrcRegs > 0)
+ response << ", ";
+ ccprintf(response, "0x%x", imm);
+ if (_numDestRegs > 0)
+ {
+ response << ", ";
+ printReg(response, _destRegIdx[0]);
+ }
}
- return fault;
+ return response.str();
+ }
+
+ std::string SetHi::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+
+ printMnemonic(response, mnemonic);
+ if(_numSrcRegs > 0)
+ response << ", ";
+ ccprintf(response, "%%hi(0x%x), ", imm);
+ printReg(response, _destRegIdx[0]);
+ return response.str();
}
}};
-def template IntOpCcResExecute {{
+def template IntOpExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault;
+ Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
@@ -117,49 +244,83 @@ def template IntOpCcResExecute {{
if(fault == NoFault)
{
%(op_wb)s;
- CcrIccN = Rd & (1 << 63);
- CcrIccZ = (Rd == 0);
- CcrXccN = Rd & (1 << 31);
- CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
- CcrIccV = CcrIccC = CcrXccV = CcrXccC = 0;
+ %(cc_code)s;
}
return fault;
}
}};
let {{
- def doIntFormat(code, execTemplate, name, Name, opt_flags):
- (usesImm, cblk, immCblk, rString, iString) = splitOutImm(code)
- iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
+ def doIntFormat(code, ccCode, name, Name, opt_flags):
+ (usesImm, code, immCode,
+ rString, iString) = splitOutImm(code)
+ iop = InstObjParams(name, Name, 'IntOp', code,
+ opt_flags, ("cc_code", ccCode))
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
- exec_output = execTemplate.subst(iop)
+ exec_output = IntOpExecute.subst(iop)
if usesImm:
imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
- immCblk, opt_flags)
+ immCode, opt_flags, ("cc_code", ccCode))
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
- exec_output += execTemplate.subst(imm_iop)
+ exec_output += IntOpExecute.subst(imm_iop)
decode_block = ROrImmDecode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
+ return (header_output, decoder_output, exec_output, decode_block)
+
+ calcCcCode = '''
+ CcrIccN = (Rd >> 63) & 1;
+ CcrIccZ = (Rd == 0);
+ CcrXccN = (Rd >> 31) & 1;
+ CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
+ CcrIccV = %(ivValue)s;
+ CcrIccC = %(icValue)s;
+ CcrXccV = %(xvValue)s;
+ CcrXccC = %(xcValue)s;
+ '''
}};
// Primary format for integer operate instructions:
def format IntOp(code, *opt_flags) {{
- doIntFormat(code, IntOpExecute, name, Name, opt_flags)
+ ccCode = ''
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doIntFormat(code, ccCode,
+ name, Name, opt_flags)
}};
// Primary format for integer operate instructions:
def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
- for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
- ('xvValue', xvValue), ('xcValue', xcValue)):
- code.replace(marker, value)
- doIntFormat(code, IntOpCcExecute, name, Name, opt_flags)
+ ccCode = calcCcCode % vars()
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doIntFormat(code, ccCode,
+ name, Name, opt_flags)
}};
// Primary format for integer operate instructions:
def format IntOpCcRes(code, *opt_flags) {{
- doIntFormat(code, IntOpCcResExecute, name, Name, opt_flags)
+ ccCode = calcCcCode % {"icValue":"0",
+ "ivValue":"0",
+ "xcValue":"0",
+ "xvValue":"0"}
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doIntFormat(code, ccCode,
+ name, Name, opt_flags)
+}};
+
+def format SetHi(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'SetHi',
+ code, opt_flags, ("cc_code", ''))
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ exec_output = IntOpExecute.subst(iop)
+ decode_block = SetHiDecode.subst(iop)
}};
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
index 06725eae8..db2a4aaaa 100644
--- a/arch/sparc/isa/formats/mem.isa
+++ b/arch/sparc/isa/formats/mem.isa
@@ -5,7 +5,7 @@
output header {{
/**
- * Base class for integer operations.
+ * Base class for memory operations.
*/
class Mem : public SparcStaticInst
{
@@ -20,12 +20,76 @@ output header {{
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
+
+ /**
+ * Class for memory operations which use an immediate offset.
+ */
+ class MemImm : public Mem
+ {
+ protected:
+
+ // Constructor
+ MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+ Mem(mnem, _machInst, __opClass), imm(SIMM13)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ int32_t imm;
+ };
}};
output decoder {{
- std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ std::string Mem::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+ bool load = flags[IsLoad];
+
+ printMnemonic(response, mnemonic);
+ if(!load)
+ {
+ printReg(response, _srcRegIdx[0]);
+ ccprintf(response, ", ");
+ }
+ ccprintf(response, "[ ");
+ printReg(response, _srcRegIdx[load ? 0 : 1]);
+ ccprintf(response, " + ");
+ printReg(response, _srcRegIdx[load ? 1 : 2]);
+ ccprintf(response, " ]");
+ if(load)
+ {
+ ccprintf(response, ", ");
+ printReg(response, _destRegIdx[0]);
+ }
+
+ return response.str();
+ }
+
+ std::string MemImm::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
{
- return "Memory instruction\n";
+ std::stringstream response;
+ bool load = flags[IsLoad];
+
+ printMnemonic(response, mnemonic);
+ if(!load)
+ {
+ printReg(response, _srcRegIdx[0]);
+ ccprintf(response, ", ");
+ }
+ ccprintf(response, "[ ");
+ printReg(response, _srcRegIdx[load ? 0 : 1]);
+ ccprintf(response, " + 0x%x ]", imm);
+ if(load)
+ {
+ ccprintf(response, ", ");
+ printReg(response, _destRegIdx[0]);
+ }
+
+ return response.str();
}
}};
@@ -34,10 +98,13 @@ def template MemExecute {{
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
+ Addr EA;
%(op_decl)s;
%(op_rd)s;
- ea_code
+ %(ea_code)s;
+ %(load)s;
%(code)s;
+ %(store)s;
if(fault == NoFault)
{
@@ -49,14 +116,49 @@ def template MemExecute {{
}
}};
-// Primary format for integer operate instructions:
-def format Mem(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = MemExecute.subst(iop)
- exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
+let {{
+ # Leave memAccessFlags at 0 for now
+ loadString = "xc->read(EA, (uint%(width)s_t&)Mem, 0);"
+ storeString = "uint64_t write_result = 0; \
+ xc->write((uint%(width)s_t)Mem, EA, 0, &write_result);"
+
+ def doMemFormat(code, load, store, name, Name, opt_flags):
+ addrCalcReg = 'EA = Rs1 + Rs2;'
+ addrCalcImm = 'EA = Rs1 + SIMM13;'
+ iop = InstObjParams(name, Name, 'Mem', code,
+ opt_flags, ("ea_code", addrCalcReg),
+ ("load", load), ("store", store))
+ iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code,
+ opt_flags, ("ea_code", addrCalcImm),
+ ("load", load), ("store", store))
+ header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
+ decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
+ decode_block = ROrImmDecode.subst(iop)
+ exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
+ return (header_output, decoder_output, exec_output, decode_block)
+}};
+
+def format Load(code, width, *opt_flags) {{
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doMemFormat(code,
+ loadString % {"width":width}, '', name, Name, opt_flags)
+}};
+
+def format Store(code, width, *opt_flags) {{
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doMemFormat(code, '',
+ storeString % {"width":width}, name, Name, opt_flags)
+}};
+
+def format LoadStore(code, width, *opt_flags) {{
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doMemFormat(code,
+ loadString % {"width":width}, storeString % {"width":width},
+ name, Name, opt_flags)
}};
diff --git a/arch/sparc/isa/formats/noop.isa b/arch/sparc/isa/formats/nop.isa
index 5007f5bcb..df7503eee 100644
--- a/arch/sparc/isa/formats/noop.isa
+++ b/arch/sparc/isa/formats/nop.isa
@@ -1,35 +1,47 @@
////////////////////////////////////////////////////////////////////
//
-// Noop instruction
+// Nop instruction
//
output header {{
/**
- * Noop class.
+ * Nop class.
*/
- class Noop : public SparcStaticInst
+ class Nop : public SparcStaticInst
{
- protected:
+ public:
// Constructor
- Noop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+ Nop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
+ // All Nop instructions do the same thing, so this can be
+ // defined here. Nops can be defined directly, so there needs
+ // to be a default implementation
+ Fault execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ //Nothing to see here, move along
+ return NoFault;
+ }
+
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
- std::string Noop::generateDisassembly(Addr pc,
+ std::string Nop::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
- return "Noop\n";
+ std::stringstream response;
+ printMnemonic(response, mnemonic);
+ return response.str();
}
}};
-def template NoopExecute {{
+def template NopExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -39,12 +51,12 @@ def template NoopExecute {{
}};
// Primary format for integer operate instructions:
-def format Noop(code, *opt_flags) {{
+def format Nop(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+ iop = InstObjParams(name, Name, 'Nop', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = NoopExecute.subst(iop)
+ exec_output = NopExecute.subst(iop)
}};
diff --git a/arch/sparc/isa/formats/priv.isa b/arch/sparc/isa/formats/priv.isa
index c89e769b4..f9fea01f2 100644
--- a/arch/sparc/isa/formats/priv.isa
+++ b/arch/sparc/isa/formats/priv.isa
@@ -50,7 +50,7 @@ output header {{
{
}
- uint32_t imm;
+ int32_t imm;
};
/**
@@ -66,7 +66,7 @@ output header {{
{
}
- uint32_t imm;
+ int32_t imm;
};
}};
@@ -92,74 +92,48 @@ def template PrivExecute {{
%(op_rd)s;
//If the processor isn't in privileged mode, fault out right away
- if(!PstatePriv)
- return new PrivilegedOpcode
+ if(%(check)s)
+ return new PrivilegedAction;
%(code)s;
%(op_wb)s;
+ return NoFault;
}
}};
-def template PrivTickExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- %(op_decl)s;
- %(op_rd)s;
-
- //If the processor isn't in privileged mode, fault out right away
- if(!PstatePriv && TickNpt)
- return new PrivilegedAction
-
- %(code)s;
- %(op_wb)s;
- }
-}};
-
-// Primary format for integer operate instructions:
-def format Priv(code, *opt_flags) {{
- uses_imm = (code.find('Rs2_or_imm13') != -1)
- if uses_imm:
- orig_code = code
- code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code)
- imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code)
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'Priv', cblk, opt_flags)
+let {{
+ def doPrivFormat(code, checkCode, name, Name, opt_flags):
+ (usesImm, code, immCode,
+ rString, iString) = splitOutImm(code)
+ iop = InstObjParams(name, Name, 'Priv', code,
+ opt_flags, ("check", checkCode))
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = PrivExecute.subst(iop)
- if uses_imm:
- imm_cblk = CodeBlock(imm_code)
- imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', imm_cblk,
- opt_flags)
+ if usesImm:
+ imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm',
+ immCode, opt_flags, ("check", checkCode))
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += PrivExecute.subst(imm_iop)
decode_block = ROrImmDecode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
+ return (header_output, decoder_output, exec_output, decode_block)
+}};
+
+// Primary format for integer operate instructions:
+def format Priv(code, *opt_flags) {{
+ checkCode = "(!PstatePriv)"
+ (header_output, decoder_output,
+ exec_output, decode_block) = doPrivFormat(code,
+ checkCode, name, Name, opt_flags)
}};
// Primary format for integer operate instructions:
def format PrivTick(code, *opt_flags) {{
- uses_imm = (code.find('Rs2_or_imm13') != -1)
- if uses_imm:
- orig_code = code
- code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code)
- imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code)
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'PrivTick', cblk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = PrivTickExecute.subst(iop)
- if uses_imm:
- imm_cblk = CodeBlock(imm_code)
- imm_iop = InstObjParams(name, Name + 'Imm', 'PrivTickImm', imm_cblk,
- opt_flags)
- header_output += BasicDeclare.subst(imm_iop)
- decoder_output += BasicConstructor.subst(imm_iop)
- exec_output += PrivTickExecute.subst(imm_iop)
- decode_block = Rb2OrImmDecode.subst(iop)
- else:
- decode_block = BasicDecode.subst(iop)
+ checkCode = "(!PstatePriv && TickNpt)"
+ (header_output, decoder_output,
+ exec_output, decode_block) = doPrivFormat(code,
+ checkCode, name, Name, opt_flags)
}};
diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa
index 935fbfe6b..5608548bd 100644
--- a/arch/sparc/isa/formats/trap.isa
+++ b/arch/sparc/isa/formats/trap.isa
@@ -27,7 +27,7 @@ output decoder {{
std::string Trap::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
- return "Trap instruction\n";
+ return "Trap instruction";
}
}};
@@ -36,6 +36,8 @@ def template TrapExecute {{
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
+ %(op_decl)s;
+ %(op_rd)s;
%(code)s
return fault;
}
@@ -44,7 +46,7 @@ def template TrapExecute {{
def format Trap(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+ iop = InstObjParams(name, Name, 'Trap', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/arch/sparc/isa/formats/unknown.isa b/arch/sparc/isa/formats/unknown.isa
index eeb2b9496..223111905 100644
--- a/arch/sparc/isa/formats/unknown.isa
+++ b/arch/sparc/isa/formats/unknown.isa
@@ -29,7 +29,7 @@ output decoder {{
std::string Unknown::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
- return "Unknown instruction\n";
+ return "Unknown instruction";
}
}};
diff --git a/arch/sparc/isa/includes.isa b/arch/sparc/isa/includes.isa
index c39fc2ef9..ff4174899 100644
--- a/arch/sparc/isa/includes.isa
+++ b/arch/sparc/isa/includes.isa
@@ -12,6 +12,7 @@ output header {{
#include "arch/sparc/faults.hh"
#include "mem/request.hh" // some constructors use MemReq flags
#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/regfile.hh"
}};
output decoder {{
diff --git a/arch/sparc/isa/main.isa b/arch/sparc/isa/main.isa
index ab0290d58..35167d6b7 100644
--- a/arch/sparc/isa/main.isa
+++ b/arch/sparc/isa/main.isa
@@ -26,7 +26,7 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-##include "m5/arch/sparc/isa/includes.isa"
+##include "includes.isa"
////////////////////////////////////////////////////////////////////
//
@@ -37,16 +37,16 @@
namespace SparcISA;
//Include the bitfield definitions
-##include "m5/arch/sparc/isa/bitfields.isa"
+##include "bitfields.isa"
//Include the operand_types and operand definitions
-##include "m5/arch/sparc/isa/operands.isa"
+##include "operands.isa"
//Include the base class for sparc instructions, and some support code
-##include "m5/arch/sparc/isa/base.isa"
+##include "base.isa"
//Include the definitions for the instruction formats
-##include "m5/arch/sparc/isa/formats.isa"
+##include "formats.isa"
//Include the decoder definition
-##include "m5/arch/sparc/isa/decoder.isa"
+##include "decoder.isa"
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa
index abfdf7bcd..17e58ad59 100644
--- a/arch/sparc/isa/operands.isa
+++ b/arch/sparc/isa/operands.isa
@@ -16,18 +16,22 @@ def operands {{
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'.
- 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
- 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2),
- 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3),
+ 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
+ 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
+ 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
+ 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
+ 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
#'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
#'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
#'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
- 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
- #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
+ 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
+ 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 4),
+ 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 4),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
- 'R0': ('IntReg', 'udw', '0', None, 1),
- 'R16': ('IntReg', 'udw', '16', None, 1),
+ 'R0': ('IntReg', 'udw', '0', None, 6),
+ 'R15': ('IntReg', 'udw', '15', 'IsInteger', 7),
+ 'R16': ('IntReg', 'udw', '16', None, 8),
# Control registers
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
@@ -55,7 +59,7 @@ def operands {{
'CcrXccC': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22),
'CcrXccV': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23),
'CcrXccZ': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24),
- 'CcrXccN': ('ControlReg', 'udw', 'MISCREG_XCC_N', None, 25),
+ 'CcrXccN': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_N', None, 25),
'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27),
#'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-05 02:51:57 +0000