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-rw-r--r--arch/sparc/isa/base.isa222
-rw-r--r--arch/sparc/isa/bitfields.isa48
-rw-r--r--arch/sparc/isa/decoder.isa691
-rw-r--r--arch/sparc/isa/formats.isa28
-rw-r--r--arch/sparc/isa/formats/basic.isa68
-rw-r--r--arch/sparc/isa/formats/branch.isa308
-rw-r--r--arch/sparc/isa/formats/integerop.isa349
-rw-r--r--arch/sparc/isa/formats/mem.isa171
-rw-r--r--arch/sparc/isa/formats/nop.isa62
-rw-r--r--arch/sparc/isa/formats/priv.isa139
-rw-r--r--arch/sparc/isa/formats/trap.isa64
-rw-r--r--arch/sparc/isa/formats/unknown.isa46
-rw-r--r--arch/sparc/isa/includes.isa46
-rw-r--r--arch/sparc/isa/main.isa52
-rw-r--r--arch/sparc/isa/operands.isa115
15 files changed, 0 insertions, 2409 deletions
diff --git a/arch/sparc/isa/base.isa b/arch/sparc/isa/base.isa
deleted file mode 100644
index 8ea11b40e..000000000
--- a/arch/sparc/isa/base.isa
+++ /dev/null
@@ -1,222 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Base class for sparc instructions, and some support functions
-//
-
-output header {{
-
- union CondCodes
- {
- struct
- {
- uint8_t c:1;
- uint8_t v:1;
- uint8_t z:1;
- uint8_t n:1;
- };
- uint32_t bits;
- };
-
- enum CondTest
- {
- Always=0x8,
- Never=0x0,
- NotEqual=0x9,
- Equal=0x1,
- Greater=0xA,
- LessOrEqual=0x2,
- GreaterOrEqual=0xB,
- Less=0x3,
- GreaterUnsigned=0xC,
- LessOrEqualUnsigned=0x4,
- CarryClear=0xD,
- CarrySet=0x5,
- Positive=0xE,
- Negative=0x6,
- OverflowClear=0xF,
- OverflowSet=0x7
- };
-
- extern char * CondTestAbbrev[];
-
- /**
- * Base class for all SPARC static instructions.
- */
- class SparcStaticInst : public StaticInst
- {
- protected:
- // Constructor.
- SparcStaticInst(const char *mnem,
- MachInst _machInst, OpClass __opClass)
- : StaticInst(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
-
- void printReg(std::ostream &os, int reg) const;
- };
-
- bool passesCondition(uint32_t codes, uint32_t condition);
-
- inline int64_t sign_ext(uint64_t data, int origWidth)
- {
- int shiftAmount = 64 - origWidth;
- return (((int64_t)data) << shiftAmount) >> shiftAmount;
- }
-}};
-
-output decoder {{
-
- char * CondTestAbbrev[] =
- {
- "nev", //Never
- "e", //Equal
- "le", //Less or Equal
- "l", //Less
- "leu", //Less or Equal Unsigned
- "c", //Carry set
- "n", //Negative
- "o", //Overflow set
- "a", //Always
- "ne", //Not Equal
- "g", //Greater
- "ge", //Greater or Equal
- "gu", //Greater Unsigned
- "cc", //Carry clear
- "p", //Positive
- "oc" //Overflow Clear
- };
-}};
-
-def template ROrImmDecode {{
- {
- return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
- : (SparcStaticInst *)(new %(class_name)s(machInst)));
- }
-}};
-
-let {{
- def splitOutImm(code):
- matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)(?P<typeQual>\.\w+)?')
- rOrImmMatch = matcher.search(code)
- if (rOrImmMatch == None):
- return (False, code, '', '', '')
- rString = rOrImmMatch.group("rNum")
- if (rOrImmMatch.group("typeQual") != None):
- rString += rOrImmMatch.group("typeQual")
- iString = rOrImmMatch.group("iNum")
- orig_code = code
- code = matcher.sub('Rs' + rString, orig_code)
- imm_code = matcher.sub('imm', orig_code)
- return (True, code, imm_code, rString, iString)
-}};
-
-output decoder {{
-
- inline void printMnemonic(std::ostream &os, const char * mnemonic)
- {
- ccprintf(os, "\t%s ", mnemonic);
- }
-
- void
- SparcStaticInst::printReg(std::ostream &os, int reg) const
- {
- const int MaxGlobal = 8;
- const int MaxOutput = 16;
- const int MaxLocal = 24;
- const int MaxInput = 32;
- if (reg == FramePointerReg)
- ccprintf(os, "%%fp");
- else if (reg == StackPointerReg)
- ccprintf(os, "%%sp");
- else if(reg < MaxGlobal)
- ccprintf(os, "%%g%d", reg);
- else if(reg < MaxOutput)
- ccprintf(os, "%%o%d", reg - MaxGlobal);
- else if(reg < MaxLocal)
- ccprintf(os, "%%l%d", reg - MaxOutput);
- else if(reg < MaxInput)
- ccprintf(os, "%%i%d", reg - MaxLocal);
- else {
- ccprintf(os, "%%f%d", reg - FP_Base_DepTag);
- }
- }
-
- std::string SparcStaticInst::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream ss;
-
- printMnemonic(ss, mnemonic);
-
- // just print the first two source regs... if there's
- // a third one, it's a read-modify-write dest (Rc),
- // e.g. for CMOVxx
- if(_numSrcRegs > 0)
- {
- printReg(ss, _srcRegIdx[0]);
- }
- if(_numSrcRegs > 1)
- {
- ss << ",";
- printReg(ss, _srcRegIdx[1]);
- }
-
- // just print the first dest... if there's a second one,
- // it's generally implicit
- if(_numDestRegs > 0)
- {
- if(_numSrcRegs > 0)
- ss << ",";
- printReg(ss, _destRegIdx[0]);
- }
-
- return ss.str();
- }
-
- bool passesCondition(uint32_t codes, uint32_t condition)
- {
- CondCodes condCodes;
- condCodes.bits = codes;
- switch(condition)
- {
- case Always:
- return true;
- case Never:
- return false;
- case NotEqual:
- return !condCodes.z;
- case Equal:
- return condCodes.z;
- case Greater:
- return !(condCodes.z | (condCodes.n ^ condCodes.v));
- case LessOrEqual:
- return condCodes.z | (condCodes.n ^ condCodes.v);
- case GreaterOrEqual:
- return !(condCodes.n ^ condCodes.v);
- case Less:
- return (condCodes.n ^ condCodes.v);
- case GreaterUnsigned:
- return !(condCodes.c | condCodes.z);
- case LessOrEqualUnsigned:
- return (condCodes.c | condCodes.z);
- case CarryClear:
- return !condCodes.c;
- case CarrySet:
- return condCodes.c;
- case Positive:
- return !condCodes.n;
- case Negative:
- return condCodes.n;
- case OverflowClear:
- return !condCodes.v;
- case OverflowSet:
- return condCodes.v;
- }
- panic("Tried testing condition nonexistant "
- "condition code %d", condition);
- }
-}};
-
diff --git a/arch/sparc/isa/bitfields.isa b/arch/sparc/isa/bitfields.isa
deleted file mode 100644
index 2e4478099..000000000
--- a/arch/sparc/isa/bitfields.isa
+++ /dev/null
@@ -1,48 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Bitfield definitions.
-//
-
-// Bitfields are shared liberally between instruction formats, so they are
-// simply defined alphabetically
-
-def bitfield A <29>;
-def bitfield BPCC <21:20>; // for BPcc & FBPcc
-def bitfield FCMPCC <26:56>; // for FCMP & FCMPEa
-def bitfield FMOVCC <13:11>; // for FMOVcc
-def bitfield CC <12:11>; // for MOVcc & Tcc
-def bitfield MOVCC3 <18>; // also for MOVcc
-def bitfield CMASK <6:4>;
-def bitfield COND2 <28:25>;
-def bitfield COND4 <17:14>;
-def bitfield D16HI <21:20>;
-def bitfield D16LO <13:0>;
-def bitfield DISP19 <18:0>;
-def bitfield DISP22 <21:0>;
-def bitfield DISP30 <29:0>;
-def bitfield FCN <29:26>;
-def bitfield I <13>;
-def bitfield IMM_ASI <12:5>;
-def bitfield IMM22 <21:0>;
-def bitfield MMASK <3:0>;
-def bitfield OP <31:30>;
-def bitfield OP2 <24:22>;
-def bitfield OP3 <24:19>;
-def bitfield OPF <13:5>;
-def bitfield OPF_CC <13:11>;
-def bitfield OPF_LOW5 <9:5>;
-def bitfield OPF_LOW6 <10:5>;
-def bitfield P <19>;
-def bitfield RCOND2 <27:25>;
-def bitfield RCOND3 <12:10>;
-def bitfield RCOND4 <12:10>;
-def bitfield RD <29:25>;
-def bitfield RS1 <18:14>;
-def bitfield RS2 <4:0>;
-def bitfield SHCNT32 <4:0>;
-def bitfield SHCNT64 <5:0>;
-def bitfield SIMM10 <9:0>;
-def bitfield SIMM11 <10:0>;
-def bitfield SIMM13 <12:0>;
-def bitfield SW_TRAP <7:0>;
-def bitfield X <12>;
diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
deleted file mode 100644
index 52ca5d7cd..000000000
--- a/arch/sparc/isa/decoder.isa
+++ /dev/null
@@ -1,691 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// The actual decoder specification
-//
-
-decode OP default Unknown::unknown()
-{
- 0x0: decode OP2
- {
- //Throw an illegal instruction acception
- 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
- 0x1: decode BPCC
- {
- format Branch19
- {
- 0x0: bpcci({{
- if(passesCondition(CcrIcc, COND2))
- NNPC = xc->readPC() + disp;
- else
- handle_annul
- }});
- 0x2: bpccx({{
- if(passesCondition(CcrXcc, COND2))
- NNPC = xc->readPC() + disp;
- else
- handle_annul
- }});
- }
- }
- 0x2: Branch22::bicc({{
- if(passesCondition(CcrIcc, COND2))
- NNPC = xc->readPC() + disp;
- else
- handle_annul
- }});
- 0x3: decode RCOND2
- {
- format BranchSplit
- {
- 0x1: bpreq({{
- if(Rs1.sdw == 0)
- NNPC = xc->readPC() + disp;
- else
- handle_annul
- }});
- 0x2: bprle({{
- if(Rs1.sdw <= 0)
- NNPC = xc->readPC() + disp;
- else
- handle_annul
- }});
- 0x3: bprl({{
- if(Rs1.sdw < 0)
- NNPC = xc->readPC() + disp;
- else
- handle_annul
- }});
- 0x5: bprne({{
- if(Rs1.sdw != 0)
- NNPC = xc->readPC() + disp;
- else
- handle_annul
- }});
- 0x6: bprg({{
- if(Rs1.sdw > 0)
- NNPC = xc->readPC() + disp;
- else
- handle_annul
- }});
- 0x7: bprge({{
- if(Rs1.sdw >= 0)
- NNPC = xc->readPC() + disp;
- else
- handle_annul
- }});
- }
- }
- //SETHI (or NOP if rd == 0 and imm == 0)
- 0x4: SetHi::sethi({{Rd = imm;}});
- 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
- 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
- }
- 0x1: Branch30::call({{
- R15 = xc->readPC();
- NNPC = R15 + disp;
- }});
- 0x2: decode OP3 {
- format IntOp {
- 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
- 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}});
- 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}});
- 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}});
- 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
- 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}});
- 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}});
- 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}});
- 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + CcrIccC;}});
- 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}});
- 0x0A: umul({{
- Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
- YValue = Rd<63:32>;
- }});
- 0x0B: smul({{
- Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
- YValue = Rd.sdw;
- }});
- 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + CcrIccC;}});
- 0x0D: udivx({{
- if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
- else Rd.udw = Rs1.udw / Rs2_or_imm13;
- }});
- 0x0E: udiv({{
- if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
- else
- {
- Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
- if(Rd.udw >> 32 != 0)
- Rd.udw = 0xFFFFFFFF;
- }
- }});
- 0x0F: sdiv({{
- if(Rs2_or_imm13.sdw == 0)
- fault = new DivisionByZero;
- else
- {
- Rd.udw = ((int64_t)((YValue << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
- if(Rd.udw<63:31> != 0)
- Rd.udw = 0x7FFFFFFF;
- else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
- Rd.udw = 0xFFFFFFFF80000000ULL;
- }
- }});
- }
- format IntOpCc {
- 0x10: addcc({{
- int64_t resTemp, val2 = Rs2_or_imm13;
- Rd = resTemp = Rs1 + val2;}},
- {{(Rs1<31:0> + val2<31:0>)<32:>}},
- {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
- {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
- {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
- );
- 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
- 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
- 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
- 0x14: subcc({{
- int64_t val2 = Rs2_or_imm13;
- Rd = Rs1 - val2;}},
- {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
- {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
- {{(~(Rs1<63:1> + (~val2)<63:1> +
- (Rs1 | ~val2)<0:>))<63:>}},
- {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
- );
- 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
- 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
- 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
- 0x18: addccc({{
- int64_t resTemp, val2 = Rs2_or_imm13;
- int64_t carryin = CcrIccC;
- Rd = resTemp = Rs1 + val2 + carryin;}},
- {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
- {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
- {{(Rs1<63:1> + val2<63:1> +
- ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
- {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
- );
- 0x1A: umulcc({{
- uint64_t resTemp;
- Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
- YValue = resTemp<63:32>;}},
- {{0}},{{0}},{{0}},{{0}});
- 0x1B: smulcc({{
- int64_t resTemp;
- Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
- YValue = resTemp<63:32>;}},
- {{0}},{{0}},{{0}},{{0}});
- 0x1C: subccc({{
- int64_t resTemp, val2 = Rs2_or_imm13;
- int64_t carryin = CcrIccC;
- Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
- {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
- {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
- {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
- {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
- );
- 0x1D: udivxcc({{
- if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
- else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
- ,{{0}},{{0}},{{0}},{{0}});
- 0x1E: udivcc({{
- uint32_t resTemp, val2 = Rs2_or_imm13.udw;
- int32_t overflow;
- if(val2 == 0) fault = new DivisionByZero;
- else
- {
- resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2;
- overflow = (resTemp<63:32> != 0);
- if(overflow) Rd = resTemp = 0xFFFFFFFF;
- else Rd = resTemp;
- } }},
- {{0}},
- {{overflow}},
- {{0}},
- {{0}}
- );
- 0x1F: sdivcc({{
- int32_t resTemp, val2 = Rs2_or_imm13.sdw;
- int32_t overflow, underflow;
- if(val2 == 0) fault = new DivisionByZero;
- else
- {
- Rd = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2;
- overflow = (resTemp<63:31> != 0);
- underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
- if(overflow) Rd = resTemp = 0x7FFFFFFF;
- else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000ULL;
- else Rd = resTemp;
- } }},
- {{0}},
- {{overflow || underflow}},
- {{0}},
- {{0}}
- );
- 0x20: taddcc({{
- int64_t resTemp, val2 = Rs2_or_imm13;
- Rd = resTemp = Rs1 + val2;
- int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
- {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
- {{overflow}},
- {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
- {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
- );
- 0x21: tsubcc({{
- int64_t resTemp, val2 = Rs2_or_imm13;
- Rd = resTemp = Rs1 + val2;
- int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
- {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
- {{overflow}},
- {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
- {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
- );
- 0x22: taddcctv({{
- int64_t resTemp, val2 = Rs2_or_imm13;
- Rd = resTemp = Rs1 + val2;
- int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
- if(overflow) fault = new TagOverflow;}},
- {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
- {{overflow}},
- {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
- {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
- );
- 0x23: tsubcctv({{
- int64_t resTemp, val2 = Rs2_or_imm13;
- Rd = resTemp = Rs1 + val2;
- int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
- if(overflow) fault = new TagOverflow;}},
- {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
- {{overflow}},
- {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
- {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
- );
- 0x24: mulscc({{
- int64_t resTemp, multiplicand = Rs2_or_imm13;
- int32_t multiplier = Rs1<31:0>;
- int32_t savedLSB = Rs1<0:>;
- multiplier = multiplier<31:1> |
- ((CcrIccN
- ^ CcrIccV) << 32);
- if(!YValue<0:>)
- multiplicand = 0;
- Rd = resTemp = multiplicand + multiplier;
- YValue = YValue<31:1> | (savedLSB << 31);}},
- {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
- {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
- {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
- {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
- );
- }
- format IntOp
- {
- 0x25: decode X {
- 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
- 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
- }
- 0x26: decode X {
- 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
- 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
- }
- 0x27: decode X {
- 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
- 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
- }
- 0x28: decode RS1 {
- 0x0: rdy({{Rd = YValue;}});
- 0x2: rdccr({{Rd = Ccr;}});
- 0x3: rdasi({{Rd = Asi;}});
- 0x4: PrivTick::rdtick({{Rd = Tick;}});
- 0x5: rdpc({{Rd = xc->readPC();}});
- 0x6: rdfprs({{Rd = Fprs;}});
- 0xF: decode I {
- 0x0: Nop::membar({{/*Membar isn't needed yet*/}});
- 0x1: Nop::stbar({{/*Stbar isn't needed yet*/}});
- }
- }
- 0x2A: decode RS1 {
- format Priv
- {
- 0x0: rdprtpc({{
- Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
- }});
- 0x1: rdprtnpc({{
- Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
- }});
- 0x2: rdprtstate({{
- Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl);
- }});
- 0x3: rdprtt({{
- Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl);
- }});
- 0x4: rdprtick({{Rd = Tick;}});
- 0x5: rdprtba({{Rd = Tba;}});
- 0x6: rdprpstate({{Rd = Pstate;}});
- 0x7: rdprtl({{Rd = Tl;}});
- 0x8: rdprpil({{Rd = Pil;}});
- 0x9: rdprcwp({{Rd = Cwp;}});
- 0xA: rdprcansave({{Rd = Cansave;}});
- 0xB: rdprcanrestore({{Rd = Canrestore;}});
- 0xC: rdprcleanwin({{Rd = Cleanwin;}});
- 0xD: rdprotherwin({{Rd = Otherwin;}});
- 0xE: rdprwstate({{Rd = Wstate;}});
- }
- //The floating point queue isn't implemented right now.
- 0xF: Trap::rdprfq({{fault = new IllegalInstruction;}});
- 0x1F: Priv::rdprver({{Rd = Ver;}});
- }
- 0x2B: BasicOperate::flushw({{
- if(NWindows - 2 - Cansave == 0)
- {
- if(Otherwin)
- fault = new SpillNOther(WstateOther);
- else
- fault = new SpillNNormal(WstateNormal);
- }
- }});
- 0x2C: decode MOVCC3
- {
- 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
- 0x1: decode CC
- {
- 0x0: movcci({{
- if(passesCondition(CcrIcc, COND4))
- Rd = Rs2_or_imm11;
- else
- Rd = Rd;
- }});
- 0x2: movccx({{
- if(passesCondition(CcrXcc, COND4))
- Rd = Rs2_or_imm11;
- else
- Rd = Rd;
- }});
- }
- }
- 0x2D: sdivx({{
- if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
- else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
- }});
- 0x2E: decode RS1 {
- 0x0: IntOp::popc({{
- int64_t count = 0;
- uint64_t temp = Rs2_or_imm13;
- //Count the 1s in the front 4bits until none are left
- uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
- while(temp)
- {
- count += oneBits[temp & 0xF];
- temp = temp >> 4;
- }
- Rd = count;
- }});
- }
- 0x2F: decode RCOND3
- {
- 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
- 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
- 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
- 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
- 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
- 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
- }
- 0x30: decode RD {
- 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
- 0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
- 0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
- 0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}});
- 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
- }
- 0x31: decode FCN {
- 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
- 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
- }
- 0x32: decode RD {
- format Priv
- {
- 0x0: wrprtpc({{
- xc->setMiscReg(MISCREG_TPC_BASE + Tl,
- Rs1 ^ Rs2_or_imm13);
- }});
- 0x1: wrprtnpc({{
- xc->setMiscReg(MISCREG_TNPC_BASE + Tl,
- Rs1 ^ Rs2_or_imm13);
- }});
- 0x2: wrprtstate({{
- xc->setMiscReg(MISCREG_TSTATE_BASE + Tl,
- Rs1 ^ Rs2_or_imm13);
- }});
- 0x3: wrprtt({{
- xc->setMiscReg(MISCREG_TT_BASE + Tl,
- Rs1 ^ Rs2_or_imm13);
- }});
- 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
- 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
- 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
- 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}});
- 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
- 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
- 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
- 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
- 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
- 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
- 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
- }
- }
- 0x34: Trap::fpop1({{fault = new FpDisabled;}});
- 0x35: Trap::fpop2({{fault = new FpDisabled;}});
- 0x38: Branch::jmpl({{
- Addr target = Rs1 + Rs2_or_imm13;
- if(target & 0x3)
- fault = new MemAddressNotAligned;
- else
- {
- Rd = xc->readPC();
- NNPC = target;
- }
- }});
- 0x39: Branch::return({{
- //If both MemAddressNotAligned and
- //a fill trap happen, it's not clear
- //which one should be returned.
- Addr target = Rs1 + Rs2_or_imm13;
- if(target & 0x3)
- fault = new MemAddressNotAligned;
- else
- NNPC = target;
- if(fault == NoFault)
- {
- //CWP should be set directly so that it always happens
- //Also, this will allow writing to the new window and
- //reading from the old one
- Cwp = (Cwp - 1 + NWindows) % NWindows;
- if(Canrestore == 0)
- {
- if(Otherwin)
- fault = new FillNOther(WstateOther);
- else
- fault = new FillNNormal(WstateNormal);
- }
- else
- {
- Rd = Rs1 + Rs2_or_imm13;
- Cansave = Cansave + 1;
- Canrestore = Canrestore - 1;
- }
- //This is here to make sure the CWP is written
- //no matter what. This ensures that the results
- //are written in the new window as well.
- xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
- }
- }});
- 0x3A: decode CC
- {
- 0x0: Trap::tcci({{
- if(passesCondition(CcrIcc, COND2))
- {
- int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
- DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
-#if FULL_SYSTEM
- fault = new TrapInstruction(lTrapNum);
-#else
- DPRINTF(Sparc, "The syscall number is %d\n", R1);
- xc->syscall(R1);
-#endif
- }
- }});
- 0x2: Trap::tccx({{
- if(passesCondition(CcrXcc, COND2))
- {
- int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
- DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
-#if FULL_SYSTEM
- fault = new TrapInstruction(lTrapNum);
-#else
- DPRINTF(Sparc, "The syscall number is %d\n", R1);
- xc->syscall(R1);
-#endif
- }
- }});
- }
- 0x3B: Nop::flush({{/*Instruction memory flush*/}});
- 0x3C: save({{
- //CWP should be set directly so that it always happens
- //Also, this will allow writing to the new window and
- //reading from the old one
- if(Cansave == 0)
- {
- if(Otherwin)
- fault = new SpillNOther(WstateOther);
- else
- fault = new SpillNNormal(WstateNormal);
- Cwp = (Cwp + 2) % NWindows;
- }
- else if(Cleanwin - Canrestore == 0)
- {
- Cwp = (Cwp + 1) % NWindows;
- fault = new CleanWindow;
- }
- else
- {
- Cwp = (Cwp + 1) % NWindows;
- Rd = Rs1 + Rs2_or_imm13;
- Cansave = Cansave - 1;
- Canrestore = Canrestore + 1;
- }
- //This is here to make sure the CWP is written
- //no matter what. This ensures that the results
- //are written in the new window as well.
- xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
- }});
- 0x3D: restore({{
- //CWP should be set directly so that it always happens
- //Also, this will allow writing to the new window and
- //reading from the old one
- Cwp = (Cwp - 1 + NWindows) % NWindows;
- if(Canrestore == 0)
- {
- if(Otherwin)
- fault = new FillNOther(WstateOther);
- else
- fault = new FillNNormal(WstateNormal);
- }
- else
- {
- Rd = Rs1 + Rs2_or_imm13;
- Cansave = Cansave + 1;
- Canrestore = Canrestore - 1;
- }
- //This is here to make sure the CWP is written
- //no matter what. This ensures that the results
- //are written in the new window as well.
- xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
- }});
- 0x3E: decode FCN {
- 0x0: Priv::done({{
- if(Tl == 0)
- return new IllegalInstruction;
- Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl);
- Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl);
- Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl);
- Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl);
- NPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
- NNPC = NPC + 4;
- Tl = Tl - 1;
- }});
- 0x1: BasicOperate::retry({{
- if(Tl == 0)
- return new IllegalInstruction;
- Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl);
- Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl);
- Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl);
- Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl);
- NPC = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
- NNPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
- Tl = Tl - 1;
- }});
- }
- }
- }
- 0x3: decode OP3 {
- format Load {
- 0x00: lduw({{Rd = Mem;}}, {{32}});
- 0x01: ldub({{Rd = Mem;}}, {{8}});
- 0x02: lduh({{Rd = Mem;}}, {{16}});
- 0x03: ldd({{
- uint64_t val = Mem;
- RdLow = val<31:0>;
- RdHigh = val<63:32>;
- }}, {{64}});
- }
- format Store {
- 0x04: stw({{Mem = Rd.sw;}}, {{32}});
- 0x05: stb({{Mem = Rd.sb;}}, {{8}});
- 0x06: sth({{Mem = Rd.shw;}}, {{16}});
- 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
- }
- format Load {
- 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}});
- 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}});
- 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}});
- 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}});
- 0x0D: ldstub({{
- Rd = Mem;
- Mem = 0xFF;
- }}, {{8}});
- }
- 0x0E: Store::stx({{Mem = Rd}}, {{64}});
- 0x0F: LoadStore::swap({{
- uint32_t temp = Rd;
- Rd = Mem;
- Mem = temp;
- }}, {{32}});
- format Load {
- 0x10: lduwa({{Rd = Mem;}}, {{32}});
- 0x11: lduba({{Rd = Mem;}}, {{8}});
- 0x12: lduha({{Rd = Mem;}}, {{16}});
- 0x13: ldda({{
- uint64_t val = Mem;
- RdLow = val<31:0>;
- RdHigh = val<63:32>;
- }}, {{64}});
- }
- format Store {
- 0x14: stwa({{Mem = Rd;}}, {{32}});
- 0x15: stba({{Mem = Rd;}}, {{8}});
- 0x16: stha({{Mem = Rd;}}, {{16}});
- 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
- }
- format Load {
- 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}});
- 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}});
- 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}});
- 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}});
- }
- 0x1D: LoadStore::ldstuba({{
- Rd = Mem;
- Mem = 0xFF;
- }}, {{8}});
- 0x1E: Store::stxa({{Mem = Rd}}, {{64}});
- 0x1F: LoadStore::swapa({{
- uint32_t temp = Rd;
- Rd = Mem;
- Mem = temp;
- }}, {{32}});
- format Trap {
- 0x20: ldf({{fault = new FpDisabled;}});
- 0x21: decode X {
- 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}});
- 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}});
- }
- 0x22: ldqf({{fault = new FpDisabled;}});
- 0x23: lddf({{fault = new FpDisabled;}});
- 0x24: stf({{fault = new FpDisabled;}});
- 0x25: decode X {
- 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}});
- 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}});
- }
- 0x26: stqf({{fault = new FpDisabled;}});
- 0x27: stdf({{fault = new FpDisabled;}});
- 0x2D: Nop::prefetch({{ }});
- 0x30: ldfa({{return new FpDisabled;}});
- 0x32: ldqfa({{fault = new FpDisabled;}});
- 0x33: lddfa({{fault = new FpDisabled;}});
- 0x34: stfa({{fault = new FpDisabled;}});
- 0x35: stqfa({{fault = new FpDisabled;}});
- 0x36: stdfa({{fault = new FpDisabled;}});
- 0x3C: Cas::casa({{
- uint64_t val = Mem.uw;
- if(Rs2.uw == val)
- Mem.uw = Rd.uw;
- Rd.uw = val;
- }});
- 0x3D: Nop::prefetcha({{ }});
- 0x3E: Cas::casxa({{
- uint64_t val = Mem.udw;
- if(Rs2 == val)
- Mem.udw = Rd;
- Rd = val;
- }});
- }
- }
-}
diff --git a/arch/sparc/isa/formats.isa b/arch/sparc/isa/formats.isa
deleted file mode 100644
index 17d68061b..000000000
--- a/arch/sparc/isa/formats.isa
+++ /dev/null
@@ -1,28 +0,0 @@
-//Include the basic format
-//Templates from this format are used later
-##include "formats/basic.isa"
-
-//Include the noop format
-##include "formats/nop.isa"
-
-//Include the integerOp and integerOpCc format
-##include "formats/integerop.isa"
-
-//Include the memory format
-##include "formats/mem.isa"
-
-//Include the compare and swap format
-##include "formats/cas.isa"
-
-//Include the trap format
-##include "formats/trap.isa"
-
-//Include the "unknown" format
-##include "formats/unknown.isa"
-
-//Include the priveleged mode format
-##include "formats/priv.isa"
-
-//Include the branch format
-##include "formats/branch.isa"
-
diff --git a/arch/sparc/isa/formats/basic.isa b/arch/sparc/isa/formats/basic.isa
deleted file mode 100644
index 73df7617d..000000000
--- a/arch/sparc/isa/formats/basic.isa
+++ /dev/null
@@ -1,68 +0,0 @@
-
-// Declarations for execute() methods.
-def template BasicExecDeclare {{
- Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
-}};
-
-// Basic instruction class declaration template.
-def template BasicDeclare {{
- /**
- * Static instruction class for "%(mnemonic)s".
- */
- class %(class_name)s : public %(base_class)s
- {
- public:
- // Constructor.
- %(class_name)s(MachInst machInst);
- %(BasicExecDeclare)s
- };
-}};
-
-// Basic instruction class constructor template.
-def template BasicConstructor {{
- inline %(class_name)s::%(class_name)s(MachInst machInst)
- : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
- {
- %(constructor)s;
- }
-}};
-
-// Basic instruction class execute method template.
-def template BasicExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
-
- if(fault == NoFault)
- {
- %(op_wb)s;
- }
- return fault;
- }
-}};
-
-// Basic decode template.
-def template BasicDecode {{
- return new %(class_name)s(machInst);
-}};
-
-// Basic decode template, passing mnemonic in as string arg to constructor.
-def template BasicDecodeWithMnemonic {{
- return new %(class_name)s("%(mnemonic)s", machInst);
-}};
-
-// The most basic instruction format... used only for a few misc. insts
-def format BasicOperate(code, *flags) {{
- iop = InstObjParams(name, Name, 'SparcStaticInst',
- CodeBlock(code), flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa
deleted file mode 100644
index 37bdb9402..000000000
--- a/arch/sparc/isa/formats/branch.isa
+++ /dev/null
@@ -1,308 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Branch instructions
-//
-
-output header {{
- /**
- * Base class for branch operations.
- */
- class Branch : public SparcStaticInst
- {
- protected:
- // Constructor
- Branch(const char *mnem, MachInst _machInst, OpClass __opClass) :
- SparcStaticInst(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
- };
-
- /**
- * Base class for branch operations with an immediate displacement.
- */
- class BranchDisp : public Branch
- {
- protected:
- // Constructor
- BranchDisp(const char *mnem, MachInst _machInst,
- OpClass __opClass) :
- Branch(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
-
- int32_t disp;
- };
-
- /**
- * Base class for branches with 19 bit displacements.
- */
- class Branch19 : public BranchDisp
- {
- protected:
- // Constructor
- Branch19(const char *mnem, MachInst _machInst,
- OpClass __opClass) :
- BranchDisp(mnem, _machInst, __opClass)
- {
- disp = sign_ext(DISP19 << 2, 21);
- }
- };
-
- /**
- * Base class for branches with 22 bit displacements.
- */
- class Branch22 : public BranchDisp
- {
- protected:
- // Constructor
- Branch22(const char *mnem, MachInst _machInst,
- OpClass __opClass) :
- BranchDisp(mnem, _machInst, __opClass)
- {
- disp = sign_ext(DISP22 << 2, 24);
- }
- };
-
- /**
- * Base class for branches with 30 bit displacements.
- */
- class Branch30 : public BranchDisp
- {
- protected:
- // Constructor
- Branch30(const char *mnem, MachInst _machInst,
- OpClass __opClass) :
- BranchDisp(mnem, _machInst, __opClass)
- {
- disp = sign_ext(DISP30 << 2, 32);
- }
- };
-
- /**
- * Base class for 16bit split displacements.
- */
- class BranchSplit : public BranchDisp
- {
- protected:
- // Constructor
- BranchSplit(const char *mnem, MachInst _machInst,
- OpClass __opClass) :
- BranchDisp(mnem, _machInst, __opClass)
- {
- disp = sign_ext((D16HI << 16) | (D16LO << 2), 18);
- }
- };
-
- /**
- * Base class for branches that use an immediate and a register to
- * compute their displacements.
- */
- class BranchImm13 : public Branch
- {
- protected:
- // Constructor
- BranchImm13(const char *mnem, MachInst _machInst, OpClass __opClass) :
- Branch(mnem, _machInst, __opClass), imm(sign_ext(SIMM13, 13))
- {
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
-
- int32_t imm;
- };
-}};
-
-output decoder {{
- std::string Branch::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
-
- printMnemonic(response, mnemonic);
-
- if (_numSrcRegs > 0)
- {
- printReg(response, _srcRegIdx[0]);
- for(int x = 1; x < _numSrcRegs; x++)
- {
- response << ", ";
- printReg(response, _srcRegIdx[x]);
- }
- }
-
- if (_numDestRegs > 0)
- {
- if(_numSrcRegs > 0)
- response << ", ";
- printReg(response, _destRegIdx[0]);
- }
-
- return response.str();
- }
-
- std::string BranchImm13::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
-
- printMnemonic(response, mnemonic);
-
- if (_numSrcRegs > 0)
- {
- printReg(response, _srcRegIdx[0]);
- for(int x = 1; x < _numSrcRegs; x++)
- {
- response << ", ";
- printReg(response, _srcRegIdx[x]);
- }
- }
-
- if(_numSrcRegs > 0)
- response << ", ";
-
- ccprintf(response, "0x%x", imm);
-
- if (_numDestRegs > 0)
- {
- response << ", ";
- printReg(response, _destRegIdx[0]);
- }
-
- return response.str();
- }
-
- std::string BranchDisp::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
- std::string symbol;
- Addr symbolAddr;
-
- Addr target = disp + pc;
-
- printMnemonic(response, mnemonic);
- ccprintf(response, "0x%x", target);
-
- if(symtab->findNearestSymbol(target, symbol, symbolAddr))
- {
- ccprintf(response, " <%s", symbol);
- if(symbolAddr != target)
- ccprintf(response, "+%d>", target - symbolAddr);
- else
- ccprintf(response, ">");
- }
-
- return response.str();
- }
-}};
-
-def template BranchExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- //Attempt to execute the instruction
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
-
- NNPC = xc->readNextNPC();
- %(code)s;
-
- if(fault == NoFault)
- {
- //Write the resulting state to the execution context
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-let {{
- handle_annul = '''
- {
- if(A)
- {
- NPC = xc->readNextNPC();
- NNPC = NPC + 4;
- }
- else
- {
- NPC = xc->readNextPC();
- NNPC = xc->readNextNPC();
- }
- }'''
-}};
-
-// Primary format for branch instructions:
-def format Branch(code, *opt_flags) {{
- code = re.sub(r'handle_annul', handle_annul, code)
- (usesImm, code, immCode,
- rString, iString) = splitOutImm(code)
- iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = BranchExecute.subst(iop)
- if usesImm:
- imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString,
- immCode, opt_flags)
- header_output += BasicDeclare.subst(imm_iop)
- decoder_output += BasicConstructor.subst(imm_iop)
- exec_output += BranchExecute.subst(imm_iop)
- decode_block = ROrImmDecode.subst(iop)
- else:
- decode_block = BasicDecode.subst(iop)
-}};
-
-// Primary format for branch instructions:
-def format Branch19(code, *opt_flags) {{
- code = re.sub(r'handle_annul', handle_annul, code)
- codeBlk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = BranchExecute.subst(iop)
- decode_block = BasicDecode.subst(iop)
-}};
-
-// Primary format for branch instructions:
-def format Branch22(code, *opt_flags) {{
- code = re.sub(r'handle_annul', handle_annul, code)
- codeBlk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = BranchExecute.subst(iop)
- decode_block = BasicDecode.subst(iop)
-}};
-
-// Primary format for branch instructions:
-def format Branch30(code, *opt_flags) {{
- code = re.sub(r'handle_annul', handle_annul, code)
- codeBlk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = BranchExecute.subst(iop)
- decode_block = BasicDecode.subst(iop)
-}};
-
-// Primary format for branch instructions:
-def format BranchSplit(code, *opt_flags) {{
- code = re.sub(r'handle_annul', handle_annul, code)
- codeBlk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = BranchExecute.subst(iop)
- decode_block = BasicDecode.subst(iop)
-}};
-
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
deleted file mode 100644
index 881154b67..000000000
--- a/arch/sparc/isa/formats/integerop.isa
+++ /dev/null
@@ -1,349 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Integer operate instructions
-//
-
-output header {{
- /**
- * Base class for integer operations.
- */
- class IntOp : public SparcStaticInst
- {
- protected:
- // Constructor
- IntOp(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass) :
- SparcStaticInst(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
-
- virtual bool printPseudoOps(std::ostream &os, Addr pc,
- const SymbolTable *symtab) const;
- };
-
- /**
- * Base class for immediate integer operations.
- */
- class IntOpImm : public IntOp
- {
- protected:
- // Constructor
- IntOpImm(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass) :
- IntOp(mnem, _machInst, __opClass)
- {
- }
-
- int32_t imm;
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
-
- virtual bool printPseudoOps(std::ostream &os, Addr pc,
- const SymbolTable *symtab) const;
- };
-
- /**
- * Base class for 10 bit immediate integer operations.
- */
- class IntOpImm10 : public IntOpImm
- {
- protected:
- // Constructor
- IntOpImm10(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass) :
- IntOpImm(mnem, _machInst, __opClass)
- {
- imm = sign_ext(SIMM10, 10);
- }
- };
-
- /**
- * Base class for 11 bit immediate integer operations.
- */
- class IntOpImm11 : public IntOpImm
- {
- protected:
- // Constructor
- IntOpImm11(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass) :
- IntOpImm(mnem, _machInst, __opClass)
- {
- imm = sign_ext(SIMM11, 11);
- }
- };
-
- /**
- * Base class for 13 bit immediate integer operations.
- */
- class IntOpImm13 : public IntOpImm
- {
- protected:
- // Constructor
- IntOpImm13(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass) :
- IntOpImm(mnem, _machInst, __opClass)
- {
- imm = sign_ext(SIMM13, 13);
- }
- };
-
- /**
- * Base class for sethi.
- */
- class SetHi : public IntOpImm
- {
- protected:
- // Constructor
- SetHi(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass) :
- IntOpImm(mnem, _machInst, __opClass)
- {
- imm = (IMM22 << 10) & 0xFFFFFC00;
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
- };
-}};
-
-def template SetHiDecode {{
- {
- if(RD == 0 && IMM22 == 0)
- return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass));
- else
- return (SparcStaticInst *)(new %(class_name)s(machInst));
- }
-}};
-
-output decoder {{
-
- bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
- const SymbolTable *symbab) const
- {
- if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
- {
- printMnemonic(os, "mov");
- if(_numSrcRegs > 0)
- printReg(os, _srcRegIdx[1]);
- ccprintf(os, ", ");
- if(_numDestRegs > 0)
- printReg(os, _destRegIdx[0]);
-
- return true;
- }
- return false;
- }
-
- bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
- const SymbolTable *symbab) const
- {
- if(!strcmp(mnemonic, "or"))
- {
- if(_srcRegIdx[0] == 0)
- {
- if(imm == 0)
- {
- printMnemonic(os, "clr");
- if(_numDestRegs > 0)
- printReg(os, _destRegIdx[0]);
- return true;
- }
- else
- {
- printMnemonic(os, "mov");
- ccprintf(os, ", 0x%x, ", imm);
- if(_numDestRegs > 0)
- printReg(os, _destRegIdx[0]);
- return true;
- }
- }
- else if(imm == 0)
- {
- printMnemonic(os, "mov");
- if(_numSrcRegs > 0)
- printReg(os, _srcRegIdx[0]);
- ccprintf(os, ", ");
- if(_numDestRegs > 0)
- printReg(os, _destRegIdx[0]);
- return true;
- }
- }
- return false;
- }
-
- std::string IntOp::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
-
- if(!printPseudoOps(response, pc, symtab))
- {
- printMnemonic(response, mnemonic);
- if (_numSrcRegs > 0)
- {
- printReg(response, _srcRegIdx[0]);
- for(int x = 1; x < _numSrcRegs; x++)
- {
- response << ", ";
- printReg(response, _srcRegIdx[x]);
- }
- }
- if (_numDestRegs > 0)
- {
- if(_numSrcRegs > 0)
- response << ", ";
- printReg(response, _destRegIdx[0]);
- }
- }
- return response.str();
- }
-
- std::string IntOpImm::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
-
- if(!printPseudoOps(response, pc, symtab))
- {
- printMnemonic(response, mnemonic);
- if (_numSrcRegs > 0)
- {
- printReg(response, _srcRegIdx[0]);
- for(int x = 1; x < _numSrcRegs - 1; x++)
- {
- response << ", ";
- printReg(response, _srcRegIdx[x]);
- }
- }
- if(_numSrcRegs > 0)
- response << ", ";
- ccprintf(response, "0x%x", imm);
- if (_numDestRegs > 0)
- {
- response << ", ";
- printReg(response, _destRegIdx[0]);
- }
- }
- return response.str();
- }
-
- std::string SetHi::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
-
- printMnemonic(response, mnemonic);
- if(_numSrcRegs > 0)
- response << ", ";
- ccprintf(response, "%%hi(0x%x), ", imm);
- printReg(response, _destRegIdx[0]);
- return response.str();
- }
-}};
-
-def template IntOpExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
-
- //Write the resulting state to the execution context
- if(fault == NoFault)
- {
- %(cc_code)s;
- %(op_wb)s;
- }
- return fault;
- }
-}};
-
-let {{
- def doIntFormat(code, ccCode, name, Name, opt_flags):
- (usesImm, code, immCode,
- rString, iString) = splitOutImm(code)
- iop = InstObjParams(name, Name, 'IntOp', code,
- opt_flags, ("cc_code", ccCode))
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = IntOpExecute.subst(iop)
- if usesImm:
- imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
- immCode, opt_flags, ("cc_code", ccCode))
- header_output += BasicDeclare.subst(imm_iop)
- decoder_output += BasicConstructor.subst(imm_iop)
- exec_output += IntOpExecute.subst(imm_iop)
- decode_block = ROrImmDecode.subst(iop)
- else:
- decode_block = BasicDecode.subst(iop)
- return (header_output, decoder_output, exec_output, decode_block)
-
- calcCcCode = '''
- CcrIccN = (Rd >> 31) & 1;
- CcrIccZ = ((Rd & 0xFFFFFFFF) == 0);
- CcrXccN = (Rd >> 63) & 1;
- CcrXccZ = (Rd == 0);
- CcrIccV = %(ivValue)s;
- CcrIccC = %(icValue)s;
- CcrXccV = %(xvValue)s;
- CcrXccC = %(xcValue)s;
- DPRINTF(Sparc, "in = %%d\\n", CcrIccN);
- DPRINTF(Sparc, "iz = %%d\\n", CcrIccZ);
- DPRINTF(Sparc, "xn = %%d\\n", CcrXccN);
- DPRINTF(Sparc, "xz = %%d\\n", CcrXccZ);
- DPRINTF(Sparc, "iv = %%d\\n", CcrIccV);
- DPRINTF(Sparc, "ic = %%d\\n", CcrIccC);
- DPRINTF(Sparc, "xv = %%d\\n", CcrXccV);
- DPRINTF(Sparc, "xc = %%d\\n", CcrXccC);
- '''
-}};
-
-// Primary format for integer operate instructions:
-def format IntOp(code, *opt_flags) {{
- ccCode = ''
- (header_output,
- decoder_output,
- exec_output,
- decode_block) = doIntFormat(code, ccCode,
- name, Name, opt_flags)
-}};
-
-// Primary format for integer operate instructions:
-def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
- ccCode = calcCcCode % vars()
- (header_output,
- decoder_output,
- exec_output,
- decode_block) = doIntFormat(code, ccCode,
- name, Name, opt_flags)
-}};
-
-// Primary format for integer operate instructions:
-def format IntOpCcRes(code, *opt_flags) {{
- ccCode = calcCcCode % {"icValue":"0",
- "ivValue":"0",
- "xcValue":"0",
- "xvValue":"0"}
- (header_output,
- decoder_output,
- exec_output,
- decode_block) = doIntFormat(code, ccCode,
- name, Name, opt_flags)
-}};
-
-def format SetHi(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'SetHi',
- code, opt_flags, ("cc_code", ''))
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = IntOpExecute.subst(iop)
- decode_block = SetHiDecode.subst(iop)
-}};
-
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
deleted file mode 100644
index 12dae57e5..000000000
--- a/arch/sparc/isa/formats/mem.isa
+++ /dev/null
@@ -1,171 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Mem instructions
-//
-
-output header {{
- /**
- * Base class for memory operations.
- */
- class Mem : public SparcStaticInst
- {
- protected:
-
- // Constructor
- Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- SparcStaticInst(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
- };
-
- /**
- * Class for memory operations which use an immediate offset.
- */
- class MemImm : public Mem
- {
- protected:
-
- // Constructor
- MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- Mem(mnem, _machInst, __opClass)
- {
- imm = sign_ext(SIMM13, 13);
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
-
- int32_t imm;
- };
-}};
-
-output decoder {{
- std::string Mem::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
- bool load = flags[IsLoad];
- bool save = flags[IsStore];
-
- printMnemonic(response, mnemonic);
- if(save)
- {
- printReg(response, _srcRegIdx[0]);
- ccprintf(response, ", ");
- }
- ccprintf(response, "[ ");
- printReg(response, _srcRegIdx[!save ? 0 : 1]);
- ccprintf(response, " + ");
- printReg(response, _srcRegIdx[!save ? 1 : 2]);
- ccprintf(response, " ]");
- if(load)
- {
- ccprintf(response, ", ");
- printReg(response, _destRegIdx[0]);
- }
-
- return response.str();
- }
-
- std::string MemImm::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
- bool load = flags[IsLoad];
- bool save = flags[IsStore];
-
- printMnemonic(response, mnemonic);
- if(save)
- {
- printReg(response, _srcRegIdx[0]);
- ccprintf(response, ", ");
- }
- ccprintf(response, "[ ");
- printReg(response, _srcRegIdx[!save ? 0 : 1]);
- if(imm >= 0)
- ccprintf(response, " + 0x%x ]", imm);
- else
- ccprintf(response, " + -0x%x ]", -imm);
- if(load)
- {
- ccprintf(response, ", ");
- printReg(response, _destRegIdx[0]);
- }
-
- return response.str();
- }
-}};
-
-def template MemExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
- Addr EA;
- %(op_decl)s;
- %(op_rd)s;
- %(ea_code)s;
- DPRINTF(Sparc, "The address is 0x%x\n", EA);
- %(load)s;
- %(code)s;
- %(store)s;
-
- if(fault == NoFault)
- {
- //Write the resulting state to the execution context
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-let {{
- # Leave memAccessFlags at 0 for now
- loadString = "xc->read(EA, (uint%(width)s_t&)Mem, 0);"
- storeString = "uint64_t write_result = 0; \
- xc->write((uint%(width)s_t)Mem, EA, 0, &write_result);"
-
- def doMemFormat(code, load, store, name, Name, opt_flags):
- addrCalcReg = 'EA = Rs1 + Rs2;'
- addrCalcImm = 'EA = Rs1 + imm;'
- iop = InstObjParams(name, Name, 'Mem', code,
- opt_flags, ("ea_code", addrCalcReg),
- ("load", load), ("store", store))
- iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code,
- opt_flags, ("ea_code", addrCalcImm),
- ("load", load), ("store", store))
- header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
- decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
- decode_block = ROrImmDecode.subst(iop)
- exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
- return (header_output, decoder_output, exec_output, decode_block)
-}};
-
-def format Load(code, width, *opt_flags) {{
- (header_output,
- decoder_output,
- exec_output,
- decode_block) = doMemFormat(code,
- loadString % {"width":width}, '', name, Name, opt_flags)
-}};
-
-def format Store(code, width, *opt_flags) {{
- (header_output,
- decoder_output,
- exec_output,
- decode_block) = doMemFormat(code, '',
- storeString % {"width":width}, name, Name, opt_flags)
-}};
-
-def format LoadStore(code, width, *opt_flags) {{
- (header_output,
- decoder_output,
- exec_output,
- decode_block) = doMemFormat(code,
- loadString % {"width":width}, storeString % {"width":width},
- name, Name, opt_flags)
-}};
diff --git a/arch/sparc/isa/formats/nop.isa b/arch/sparc/isa/formats/nop.isa
deleted file mode 100644
index df7503eee..000000000
--- a/arch/sparc/isa/formats/nop.isa
+++ /dev/null
@@ -1,62 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Nop instruction
-//
-
-output header {{
- /**
- * Nop class.
- */
- class Nop : public SparcStaticInst
- {
- public:
- // Constructor
- Nop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- SparcStaticInst(mnem, _machInst, __opClass)
- {
- }
-
- // All Nop instructions do the same thing, so this can be
- // defined here. Nops can be defined directly, so there needs
- // to be a default implementation
- Fault execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- //Nothing to see here, move along
- return NoFault;
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
- };
-}};
-
-output decoder {{
- std::string Nop::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
- printMnemonic(response, mnemonic);
- return response.str();
- }
-}};
-
-def template NopExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- //Nothing to see here, move along
- return NoFault;
- }
-}};
-
-// Primary format for integer operate instructions:
-def format Nop(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'Nop', cblk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = NopExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa/formats/priv.isa b/arch/sparc/isa/formats/priv.isa
deleted file mode 100644
index f9fea01f2..000000000
--- a/arch/sparc/isa/formats/priv.isa
+++ /dev/null
@@ -1,139 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Privilege mode instructions
-//
-
-output header {{
- /**
- * Base class for privelege mode operations.
- */
- class Priv : public SparcStaticInst
- {
- protected:
- // Constructor
- Priv(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- SparcStaticInst(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
- };
-
- /**
- * Base class for user mode "tick" access.
- */
- class PrivTick : public SparcStaticInst
- {
- protected:
- // Constructor
- PrivTick(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass) :
- SparcStaticInst(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
- };
-
- /**
- * Base class for privelege mode operations with immediates.
- */
- class PrivImm : public Priv
- {
- protected:
- // Constructor
- PrivImm(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass) :
- Priv(mnem, _machInst, __opClass), imm(SIMM13)
- {
- }
-
- int32_t imm;
- };
-
- /**
- * Base class for user mode "tick" access with immediates.
- */
- class PrivTickImm : public PrivTick
- {
- protected:
- // Constructor
- PrivTickImm(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass) :
- PrivTick(mnem, _machInst, __opClass), imm(SIMM13)
- {
- }
-
- int32_t imm;
- };
-}};
-
-output decoder {{
- std::string Priv::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- return "Privileged Instruction";
- }
-
- std::string PrivTick::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- return "Regular access to Tick";
- }
-}};
-
-def template PrivExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- %(op_decl)s;
- %(op_rd)s;
-
- //If the processor isn't in privileged mode, fault out right away
- if(%(check)s)
- return new PrivilegedAction;
-
- %(code)s;
- %(op_wb)s;
- return NoFault;
- }
-}};
-
-let {{
- def doPrivFormat(code, checkCode, name, Name, opt_flags):
- (usesImm, code, immCode,
- rString, iString) = splitOutImm(code)
- iop = InstObjParams(name, Name, 'Priv', code,
- opt_flags, ("check", checkCode))
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = PrivExecute.subst(iop)
- if usesImm:
- imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm',
- immCode, opt_flags, ("check", checkCode))
- header_output += BasicDeclare.subst(imm_iop)
- decoder_output += BasicConstructor.subst(imm_iop)
- exec_output += PrivExecute.subst(imm_iop)
- decode_block = ROrImmDecode.subst(iop)
- else:
- decode_block = BasicDecode.subst(iop)
- return (header_output, decoder_output, exec_output, decode_block)
-}};
-
-// Primary format for integer operate instructions:
-def format Priv(code, *opt_flags) {{
- checkCode = "(!PstatePriv)"
- (header_output, decoder_output,
- exec_output, decode_block) = doPrivFormat(code,
- checkCode, name, Name, opt_flags)
-}};
-
-// Primary format for integer operate instructions:
-def format PrivTick(code, *opt_flags) {{
- checkCode = "(!PstatePriv && TickNpt)"
- (header_output, decoder_output,
- exec_output, decode_block) = doPrivFormat(code,
- checkCode, name, Name, opt_flags)
-}};
diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa
deleted file mode 100644
index f6a45ca48..000000000
--- a/arch/sparc/isa/formats/trap.isa
+++ /dev/null
@@ -1,64 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Trap instructions
-//
-
-output header {{
- /**
- * Base class for trap instructions,
- * or instructions that always fault.
- */
- class Trap : public SparcStaticInst
- {
- protected:
-
- // Constructor
- Trap(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- SparcStaticInst(mnem, _machInst, __opClass), trapNum(SW_TRAP)
- {
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
-
- int trapNum;
- };
-}};
-
-output decoder {{
- std::string Trap::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
-
- printMnemonic(response, mnemonic);
- ccprintf(response, " ");
- printReg(response, _srcRegIdx[0]);
- ccprintf(response, ", 0x%x", trapNum);
- ccprintf(response, ", or ");
- printReg(response, _srcRegIdx[1]);
- return response.str();
- }
-}};
-
-def template TrapExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
- %(op_decl)s;
- %(op_rd)s;
- %(code)s
- return fault;
- }
-}};
-
-def format Trap(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'Trap', cblk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = TrapExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa/formats/unknown.isa b/arch/sparc/isa/formats/unknown.isa
deleted file mode 100644
index 223111905..000000000
--- a/arch/sparc/isa/formats/unknown.isa
+++ /dev/null
@@ -1,46 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Unknown instructions
-//
-
-output header {{
- /**
- * Class for Unknown/Illegal instructions
- */
- class Unknown : public SparcStaticInst
- {
- public:
-
- // Constructor
- Unknown(ExtMachInst _machInst) :
- SparcStaticInst("unknown", _machInst, No_OpClass)
- {
- }
-
- %(BasicExecDeclare)s
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
-
- };
-}};
-
-output decoder {{
- std::string Unknown::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- return "Unknown instruction";
- }
-}};
-
-output exec {{
- Fault Unknown::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- return new IllegalInstruction;
- }
-}};
-
-def format Unknown() {{
- decode_block = 'return new Unknown(machInst);\n'
-}};
diff --git a/arch/sparc/isa/includes.isa b/arch/sparc/isa/includes.isa
deleted file mode 100644
index ff4174899..000000000
--- a/arch/sparc/isa/includes.isa
+++ /dev/null
@@ -1,46 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Output include file directives.
-//
-
-output header {{
-#include <sstream>
-#include <iostream>
-#include <iomanip>
-
-#include "cpu/static_inst.hh"
-#include "arch/sparc/faults.hh"
-#include "mem/request.hh" // some constructors use MemReq flags
-#include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/regfile.hh"
-}};
-
-output decoder {{
-#include "base/cprintf.hh"
-#include "base/loader/symtab.hh"
-#include "cpu/exec_context.hh" // for Jump::branchTarget()
-
-#include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
-
-using namespace SparcISA;
-}};
-
-output exec {{
-#include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
-
-#ifdef FULL_SYSTEM
-//#include "sim/pseudo_inst.hh"
-#endif
-#include "cpu/base.hh"
-#include "cpu/exetrace.hh"
-#include "sim/sim_exit.hh"
-
-using namespace SparcISA;
-}};
-
diff --git a/arch/sparc/isa/main.isa b/arch/sparc/isa/main.isa
deleted file mode 100644
index 35167d6b7..000000000
--- a/arch/sparc/isa/main.isa
+++ /dev/null
@@ -1,52 +0,0 @@
-// -*- mode:c++ -*-
-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-##include "includes.isa"
-
-////////////////////////////////////////////////////////////////////
-//
-// Namespace statement. Everything below this line will be in the
-// SparcISAInst namespace.
-//
-
-namespace SparcISA;
-
-//Include the bitfield definitions
-##include "bitfields.isa"
-
-//Include the operand_types and operand definitions
-##include "operands.isa"
-
-//Include the base class for sparc instructions, and some support code
-##include "base.isa"
-
-//Include the definitions for the instruction formats
-##include "formats.isa"
-
-//Include the decoder definition
-##include "decoder.isa"
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa
deleted file mode 100644
index 64a032eea..000000000
--- a/arch/sparc/isa/operands.isa
+++ /dev/null
@@ -1,115 +0,0 @@
-def operand_types {{
- 'sb' : ('signed int', 8),
- 'ub' : ('unsigned int', 8),
- 'shw' : ('signed int', 16),
- 'uhw' : ('unsigned int', 16),
- 'sw' : ('signed int', 32),
- 'uw' : ('unsigned int', 32),
- 'sdw' : ('signed int', 64),
- 'udw' : ('unsigned int', 64),
- 'sf' : ('float', 32),
- 'df' : ('float', 64),
- 'qf' : ('float', 128)
-}};
-
-def operands {{
- # Int regs default to unsigned, but code should not count on this.
- # For clarity, descriptions that depend on unsigned behavior should
- # explicitly specify '.uq'.
- 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
- 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
- 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
- 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
- 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
- #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
- #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
- #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
- 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
- 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 4),
- 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 4),
- #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
- #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
- 'R0': ('IntReg', 'udw', '0', None, 6),
- 'R1': ('IntReg', 'udw', '1', None, 7),
- 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
- 'R16': ('IntReg', 'udw', '16', None, 9),
- # Control registers
- 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
- 'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
- 'PstateIe': ('ControlReg', 'udw', 'MISCREG_PSTATE_IE', None, 3),
- 'PstatePriv': ('ControlReg', 'udw', 'MISCREG_PSTATE_PRIV', None, 4),
- 'PstateAm': ('ControlReg', 'udw', 'MISCREG_PSTATE_AM', None, 5),
- 'PstatePef': ('ControlReg', 'udw', 'MISCREG_PSTATE_PEF', None, 6),
- 'PstateRed': ('ControlReg', 'udw', 'MISCREG_PSTATE_RED', None, 7),
- 'PstateMm': ('ControlReg', 'udw', 'MISCREG_PSTATE_MM', None, 8),
- 'PstateTle': ('ControlReg', 'udw', 'MISCREG_PSTATE_TLE', None, 9),
- 'PstateCle': ('ControlReg', 'udw', 'MISCREG_PSTATE_CLE', None, 10),
- 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 11),
- 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 12),
- 'YValue': ('ControlReg', 'udw', 'MISCREG_Y_VALUE', None, 13),
- 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 14),
- 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
- #'Tt': ('ControlReg', 'udw', 'MISCREG_TT_BASE + tl', None, 16),
- 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 17),
- 'CcrIcc': ('ControlReg', 'udw', 'MISCREG_CCR_ICC', None, 18),
- 'CcrIccC': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_C', None, 19),
- 'CcrIccV': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_V', None, 20),
- 'CcrIccZ': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_Z', None, 21),
- 'CcrIccN': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_N', None, 22),
- 'CcrXcc': ('ControlReg', 'udw', 'MISCREG_CCR_XCC', None, 23),
- 'CcrXccC': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22),
- 'CcrXccV': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23),
- 'CcrXccZ': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24),
- 'CcrXccN': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_N', None, 25),
- 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
- 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27),
- #'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
- 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 29),
- 'TickCounter': ('ControlReg', 'udw', 'MISCREG_TICK_COUNTER', None, 32),
- 'TickNpt': ('ControlReg', 'udw', 'MISCREG_TICK_NPT', None, 33),
- 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34),
- 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35),
- 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
- 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37),
- 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38),
- 'WstateNormal': ('ControlReg', 'udw', 'MISCREG_WSTATE_NORMAL', None,39),
- 'WstateOther': ('ControlReg', 'udw', 'MISCREG_WSTATE_OTHER', None, 40),
- 'Ver': ('ControlReg', 'udw', 'MISCREG_VER', None, 41),
- 'VerMaxwin': ('ControlReg', 'udw', 'MISCREG_VER_MAXWIN', None, 42),
- 'VerMaxtl': ('ControlReg', 'udw', 'MISCREG_VER_MAXTL', None, 43),
- 'VerMask': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 44),
- 'VerImpl': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 45),
- 'VerManuf': ('ControlReg', 'udw', 'MISCREG_VER_MANUF', None, 46),
- 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 47),
- 'FsrCexc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC', None, 48),
- 'FsrCexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NXC', None, 49),
- 'FsrCexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_DZC', None, 50),
- 'FsrCexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_UFC', None, 51),
- 'FsrCexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_OFC', None, 52),
- 'FsrCexcNvc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NVC', None, 53),
- 'FsrAexc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC', None, 54),
- 'FsrAexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_NXC', None, 55),
- 'FsrAexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_DZC', None, 56),
- 'FsrAexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_UFC', None, 57),
- 'FsrAexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_OFC', None, 58),
- 'FsrAexcNvc': ('ControlReg', 'udw', 'MISCREC_FSR_AEXC_NVC', None, 59),
- 'FsrFcc0': ('ControlReg', 'udw', 'MISCREG_FSR_FCC0', None, 60),
- 'FsrQne': ('ControlReg', 'udw', 'MISCREG_FSR_QNE', None, 61),
- 'FsrFtt': ('ControlReg', 'udw', 'MISCREG_FSR_FTT', None, 62),
- 'FsrVer': ('ControlReg', 'udw', 'MISCREG_FSR_VER', None, 63),
- 'FsrNs': ('ControlReg', 'udw', 'MISCREG_FSR_NS', None, 64),
- 'FsrTem': ('ControlReg', 'udw', 'MISCREG_FSR_TEM', None, 65),
- 'FsrTemNxm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NXM', None, 66),
- 'FsrTemDzm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_DZM', None, 67),
- 'FsrTemUfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_UFM', None, 68),
- 'FsrTemOfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_OFM', None, 69),
- 'FsrTemNvm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NVM', None, 70),
- 'FsrRd': ('ControlReg', 'udw', 'MISCREG_FSR_RD', None, 71),
- 'FsrFcc1': ('ControlReg', 'udw', 'MISCREG_FSR_FCC1', None, 72),
- 'FsrFcc2': ('ControlReg', 'udw', 'MISCREG_FSR_FCC2', None, 73),
- 'FsrFcc3': ('ControlReg', 'udw', 'MISCREG_FSR_FCC3', None, 74),
- 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 75),
- 'FprsDl': ('ControlReg', 'udw', 'MISCREG_FPRS_DL', None, 76),
- 'FprsDu': ('ControlReg', 'udw', 'MISCREG_FPRS_DU', None, 77),
- 'FprsFef': ('ControlReg', 'udw', 'MISCREG_FPRS_FEF', None, 78)
-}};
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-30 16:48:13 +0000