summaryrefslogtreecommitdiff
path: root/arch/sparc/isa
diff options
context:
space:
mode:
Diffstat (limited to 'arch/sparc/isa')
-rw-r--r--arch/sparc/isa/decoder.isa47
-rw-r--r--arch/sparc/isa/formats/branch.isa23
-rw-r--r--arch/sparc/isa/formats/integerop.isa16
-rw-r--r--arch/sparc/isa/formats/mem.isa1
4 files changed, 67 insertions, 20 deletions
diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
index 823bf2626..792918267 100644
--- a/arch/sparc/isa/decoder.isa
+++ b/arch/sparc/isa/decoder.isa
@@ -16,16 +16,22 @@ decode OP default Unknown::unknown()
0x0: bpcci({{
if(passesCondition(CcrIcc, COND2))
NNPC = xc->readPC() + disp;
+ else
+ handle_annul
}});
0x2: bpccx({{
if(passesCondition(CcrXcc, COND2))
NNPC = xc->readPC() + disp;
+ else
+ handle_annul
}});
}
}
0x2: Branch22::bicc({{
if(passesCondition(CcrIcc, COND2))
NNPC = xc->readPC() + disp;
+ else
+ handle_annul
}});
0x3: decode RCOND2
{
@@ -34,26 +40,38 @@ decode OP default Unknown::unknown()
0x1: bpreq({{
if(Rs1 == 0)
NNPC = xc->readPC() + disp;
+ else
+ handle_annul
}});
0x2: bprle({{
if(Rs1 <= 0)
NNPC = xc->readPC() + disp;
+ else
+ handle_annul
}});
0x3: bprl({{
if(Rs1 < 0)
NNPC = xc->readPC() + disp;
+ else
+ handle_annul
}});
0x5: bprne({{
if(Rs1 != 0)
NNPC = xc->readPC() + disp;
+ else
+ handle_annul
}});
0x6: bprg({{
if(Rs1 > 0)
NNPC = xc->readPC() + disp;
+ else
+ handle_annul
}});
0x7: bprge({{
if(Rs1 >= 0)
NNPC = xc->readPC() + disp;
+ else
+ handle_annul
}});
}
}
@@ -117,22 +135,22 @@ decode OP default Unknown::unknown()
0x10: addcc({{
int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2;}},
- {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+ {{(Rs1<31:0> + val2<31:0>)<32:>}},
{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
- {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
+ {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);
0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
0x14: subcc({{
- int64_t resTemp, val2 = Rs2_or_imm13;
- Rd = resTemp = Rs1 - val2;}},
- {{((Rs1 & 0xFFFFFFFF - val2 & 0xFFFFFFFF) >> 31)}},
- {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
- {{(((Rs1 >> 1) + (~val2) >> 1) +
- ((Rs1 | ~val2) & 0x1))<63:>}},
- {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
+ int64_t val2 = Rs2_or_imm13;
+ Rd = Rs1 - val2;}},
+ {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
+ {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
+ {{(~(Rs1<63:1> + (~val2)<63:1> +
+ (Rs1 | ~val2)<0:>))<63:>}},
+ {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
);
0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
@@ -141,11 +159,10 @@ decode OP default Unknown::unknown()
int64_t resTemp, val2 = Rs2_or_imm13;
int64_t carryin = CcrIccC;
Rd = resTemp = Rs1 + val2 + carryin;}},
- {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
- + carryin)}},
+ {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
- {{((Rs1 >> 1) + (val2 >> 1) +
- ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
+ {{(Rs1<63:1> + val2<63:1> +
+ ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);
0x1A: umulcc({{
@@ -162,9 +179,9 @@ decode OP default Unknown::unknown()
int64_t resTemp, val2 = Rs2_or_imm13;
int64_t carryin = CcrIccC;
Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
- {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
+ {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
- {{(((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
+ {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
);
0x1D: udivxcc({{
diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa
index b76f7a9f6..37bdb9402 100644
--- a/arch/sparc/isa/formats/branch.isa
+++ b/arch/sparc/isa/formats/branch.isa
@@ -194,7 +194,7 @@ output decoder {{
{
ccprintf(response, " <%s", symbol);
if(symbolAddr != target)
- ccprintf(response, "+0x%x>", target - symbolAddr);
+ ccprintf(response, "+%d>", target - symbolAddr);
else
ccprintf(response, ">");
}
@@ -226,8 +226,25 @@ def template BranchExecute {{
}
}};
+let {{
+ handle_annul = '''
+ {
+ if(A)
+ {
+ NPC = xc->readNextNPC();
+ NNPC = NPC + 4;
+ }
+ else
+ {
+ NPC = xc->readNextPC();
+ NNPC = xc->readNextNPC();
+ }
+ }'''
+}};
+
// Primary format for branch instructions:
def format Branch(code, *opt_flags) {{
+ code = re.sub(r'handle_annul', handle_annul, code)
(usesImm, code, immCode,
rString, iString) = splitOutImm(code)
iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
@@ -247,6 +264,7 @@ def format Branch(code, *opt_flags) {{
// Primary format for branch instructions:
def format Branch19(code, *opt_flags) {{
+ code = re.sub(r'handle_annul', handle_annul, code)
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
@@ -257,6 +275,7 @@ def format Branch19(code, *opt_flags) {{
// Primary format for branch instructions:
def format Branch22(code, *opt_flags) {{
+ code = re.sub(r'handle_annul', handle_annul, code)
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
@@ -267,6 +286,7 @@ def format Branch22(code, *opt_flags) {{
// Primary format for branch instructions:
def format Branch30(code, *opt_flags) {{
+ code = re.sub(r'handle_annul', handle_annul, code)
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
@@ -277,6 +297,7 @@ def format Branch30(code, *opt_flags) {{
// Primary format for branch instructions:
def format BranchSplit(code, *opt_flags) {{
+ code = re.sub(r'handle_annul', handle_annul, code)
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
index 401af2e51..407a3e3cd 100644
--- a/arch/sparc/isa/formats/integerop.isa
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -271,14 +271,22 @@ let {{
return (header_output, decoder_output, exec_output, decode_block)
calcCcCode = '''
- CcrIccN = (Rd >> 63) & 1;
- CcrIccZ = (Rd == 0);
- CcrXccN = (Rd >> 31) & 1;
- CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
+ CcrIccN = (Rd >> 31) & 1;
+ CcrIccZ = ((Rd & 0xFFFFFFFF) == 0);
+ CcrXccN = (Rd >> 63) & 1;
+ CcrXccZ = (Rd == 0);
CcrIccV = %(ivValue)s;
CcrIccC = %(icValue)s;
CcrXccV = %(xvValue)s;
CcrXccC = %(xcValue)s;
+ DPRINTF(Sparc, "in = %%d\\n", CcrIccN);
+ DPRINTF(Sparc, "iz = %%d\\n", CcrIccZ);
+ DPRINTF(Sparc, "xn = %%d\\n", CcrXccN);
+ DPRINTF(Sparc, "xz = %%d\\n", CcrXccZ);
+ DPRINTF(Sparc, "iv = %%d\\n", CcrIccV);
+ DPRINTF(Sparc, "ic = %%d\\n", CcrIccC);
+ DPRINTF(Sparc, "xv = %%d\\n", CcrXccV);
+ DPRINTF(Sparc, "xc = %%d\\n", CcrXccC);
'''
}};
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
index e15349c7b..ab8b85a94 100644
--- a/arch/sparc/isa/formats/mem.isa
+++ b/arch/sparc/isa/formats/mem.isa
@@ -104,6 +104,7 @@ def template MemExecute {{
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
+ DPRINTF(Sparc, "The address is 0x%x\n", EA);
%(load)s;
%(code)s;
%(store)s;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 08:46:21 +0000