1 files changed, 10 insertions, 37 deletions

diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
index 4886da7cf..57206c5e5 100644
--- a/arch/sparc/isa_traits.hh
+++ b/arch/sparc/isa_traits.hh
@@ -90,6 +90,9 @@ namespace SparcISA
         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
         FP_Base_DepTag = 32,
         Ctrl_Base_DepTag = 96,
+        //XXX These are here solely to get compilation and won't work
+        Fpcr_DepTag = 0,
+        Uniq_DepTag = 0
     };
 
     //This makes sure the big endian versions of certain functions are used.
@@ -98,11 +101,6 @@ namespace SparcISA
     typedef uint32_t MachInst;
     typedef uint64_t ExtMachInst;
 
-    inline ExtMachInst
-    makeExtMI(MachInst inst, const Addr &pc) {
-        return ExtMachInst(inst);
-    }
-
     const int NumIntRegs = 32;
     const int NumFloatRegs = 64;
     const int NumMiscRegs = 32;
@@ -121,12 +119,12 @@ namespace SparcISA
     const int ArgumentReg4 = 12;
     const int ArgumentReg5 = 13;
     const int SyscallNumReg = 1;
-    // Some OS syscall sue a second register (o1) to return a second value
+    // Some OS syscall use a second register (o1) to return a second value
     const int SyscallPseudoReturnReg = ArgumentReg1;
 
     //XXX These numbers are bogus
-    const int MaxInstSrcRegs = 3;
-    const int MaxInstDestRegs = 2;
+    const int MaxInstSrcRegs = 8;
+    const int MaxInstDestRegs = 3;
 
     typedef uint64_t IntReg;
 
@@ -160,31 +158,6 @@ namespace SparcISA
 
     // return a no-op instruction... used for instruction fetch faults
     extern const MachInst NoopMachInst;
-
-    // Instruction address compression hooks
-    inline Addr realPCToFetchPC(const Addr &addr)
-    {
-        return addr;
-    }
-
-    inline Addr fetchPCToRealPC(const Addr &addr)
-    {
-        return addr;
-    }
-
-    // the size of "fetched" instructions (not necessarily the size
-    // of real instructions for PISA)
-    inline size_t fetchInstSize()
-    {
-        return sizeof(MachInst);
-    }
-
-    /**
-     * Function to insure ISA semantics about 0 registers.
-     * @param xc The execution context.
-     */
-    template <class XC>
-    void zeroRegisters(XC *xc);
 }
 
 #include "arch/sparc/regfile.hh"
@@ -201,12 +174,12 @@ namespace SparcISA
         // and put the return value itself in the standard return value reg ().
         if (return_value.successful()) {
             // no error
-            regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 0);
-            regs->intRegFile[ReturnValueReg] = return_value.value();
+            regs->setMiscReg(MISCREG_CCR_ICC_C, 0);
+            regs->setIntReg(ReturnValueReg, return_value.value());
         } else {
             // got an error, return details
-            regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 1);
-            regs->intRegFile[ReturnValueReg] = -return_value.value();
+            regs->setMiscReg(MISCREG_CCR_ICC_C, 1);
+            regs->setIntReg(ReturnValueReg, return_value.value());
         }
     }
 #endif