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-rw-r--r--arch/sparc/isa_traits.hh14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
index 6cf77eb0e..57206c5e5 100644
--- a/arch/sparc/isa_traits.hh
+++ b/arch/sparc/isa_traits.hh
@@ -119,12 +119,12 @@ namespace SparcISA
const int ArgumentReg4 = 12;
const int ArgumentReg5 = 13;
const int SyscallNumReg = 1;
- // Some OS syscall sue a second register (o1) to return a second value
+ // Some OS syscall use a second register (o1) to return a second value
const int SyscallPseudoReturnReg = ArgumentReg1;
//XXX These numbers are bogus
- const int MaxInstSrcRegs = 3;
- const int MaxInstDestRegs = 2;
+ const int MaxInstSrcRegs = 8;
+ const int MaxInstDestRegs = 3;
typedef uint64_t IntReg;
@@ -174,12 +174,12 @@ namespace SparcISA
// and put the return value itself in the standard return value reg ().
if (return_value.successful()) {
// no error
- regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 0);
- regs->intRegFile[ReturnValueReg] = return_value.value();
+ regs->setMiscReg(MISCREG_CCR_ICC_C, 0);
+ regs->setIntReg(ReturnValueReg, return_value.value());
} else {
// got an error, return details
- regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 1);
- regs->intRegFile[ReturnValueReg] = -return_value.value();
+ regs->setMiscReg(MISCREG_CCR_ICC_C, 1);
+ regs->setIntReg(ReturnValueReg, return_value.value());
}
}
#endif