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-rw-r--r--arch/sparc/isa/decoder.isa42
-rw-r--r--arch/sparc/isa/formats.isa18
-rw-r--r--arch/sparc/isa/formats/mem.isa16
-rw-r--r--arch/sparc/isa/formats/priv.isa20
-rw-r--r--arch/sparc/isa/formats/trap.isa2
-rw-r--r--arch/sparc/isa/main.isa12
-rw-r--r--arch/sparc/isa/operands.isa14
-rw-r--r--arch/sparc/isa_traits.hh33
-rw-r--r--arch/sparc/regfile.hh10
-rw-r--r--arch/sparc/utility.hh89
10 files changed, 170 insertions, 86 deletions
diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
index a1bbf8984..6c1356932 100644
--- a/arch/sparc/isa/decoder.isa
+++ b/arch/sparc/isa/decoder.isa
@@ -279,8 +279,8 @@ decode OP default Unknown::unknown()
0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS
0xF: decode I {
- 0x0: Noop::membar({{//Membar isn't needed yet}});
- 0x1: Noop::stbar({{//Stbar isn't needed yet}});
+ 0x0: Noop::membar({{/*Membar isn't needed yet*/}});
+ 0x1: Noop::stbar({{/*Stbar isn't needed yet*/}});
}
}
0x2A: decode RS1 {
@@ -305,19 +305,19 @@ decode OP default Unknown::unknown()
0x8: rdprpil({{Rd = Pil;}});
0x9: rdprcwp({{Rd = Cwp;}});
0xA: rdprcansave({{Rd = Cansave;}});
- 0xB: rdprcanrestore({{Rd = CanRestore;}});
+ 0xB: rdprcanrestore({{Rd = Canrestore;}});
0xC: rdprcleanwin({{Rd = Cleanwin;}});
0xD: rdprotherwin({{Rd = Otherwin;}});
0xE: rdprwstate({{Rd = Wstate;}});
}
//The floating point queue isn't implemented right now.
- 0xF: Trap::rdprfq({{fault = IllegalInstruction;}});
+ 0xF: Trap::rdprfq({{fault = new IllegalInstruction;}});
0x1F: Priv::rdprver({{Rd = Ver;}});
}
- 0x2B: BasicOperate::flushw({{//window toilet}}); //FLUSHW
+ 0x2B: BasicOperate::flushw({{/*window toilet*/}});
0x2C: decode MOVCC3
{
- 0x0: Trap::movccfcc({{fault = new FpDisabled}});
+ 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
0x1: decode CC
{
0x0: movcci({{
@@ -362,8 +362,8 @@ decode OP default Unknown::unknown()
0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
}
0x31: decode FCN {
- 0x0: BasicOperate::saved({{//Boogy Boogy}}); //SAVED
- 0x1: BasicOperate::restored({{//Boogy Boogy}}); //RESTORED
+ 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
+ 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
}
0x32: decode RD {
format Priv
@@ -401,8 +401,8 @@ decode OP default Unknown::unknown()
0x34: Trap::fpop1({{fault = new FpDisabled;}});
0x35: Trap::fpop2({{fault = new FpDisabled;}});
- 0x38: Branch::jmpl({{//Stuff}}); //JMPL
- 0x39: Branch::return({{//Other Stuff}}); //RETURN
+ 0x38: Branch::jmpl({{/*Stuff*/}});
+ 0x39: Branch::return({{/*Other Stuff*/}});
0x3A: decode CC
{
0x0: Trap::tcci({{
@@ -428,12 +428,12 @@ decode OP default Unknown::unknown()
#endif
}});
}
- 0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
- 0x3C: BasicOperate::save({{//leprechauns); //SAVE
- 0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
+ 0x3B: BasicOperate::flush({{/*Lala*/}});
+ 0x3C: BasicOperate::save({{/*leprechauns*/}});
+ 0x3D: BasicOperate::restore({{/*Eat my short int*/}});
0x3E: decode FCN {
- 0x1: BasicOperate::done({{//Done thing}}); //DONE
- 0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
+ 0x1: BasicOperate::done({{/*Done thing*/}});
+ 0x2: BasicOperate::retry({{/*Retry thing*/}});
}
}
}
@@ -444,14 +444,14 @@ decode OP default Unknown::unknown()
0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
0x03: ldd({{
uint64_t val = Mem.udw;
- setIntReg(RD & (~1), val<31:0>);
- setIntReg(RD | 1, val<63:32>);
+ RdLow = val<31:0>;
+ RdHigh = val<63:32>;
}});//LDD
0x04: stw({{Mem.sw = Rd.sw;}}); //STW
0x05: stb({{Mem.sb = Rd.sb;}}); //STB
0x06: sth({{Mem.shw = Rd.shw;}}); //STH
0x07: std({{
- Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
+ Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;
}});//STD
0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
@@ -473,14 +473,14 @@ decode OP default Unknown::unknown()
0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
0x13: ldda({{
uint64_t val = Mem.udw;
- setIntReg(RD & (~1), val<31:0>);
- setIntReg(RD | 1, val<63:32>);
+ RdLow = val<31:0>;
+ RdHigh = val<63:32>;
}}); //LDDA
0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
0x17: stda({{
- Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
+ Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;
}}); //STDA
0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
diff --git a/arch/sparc/isa/formats.isa b/arch/sparc/isa/formats.isa
index 9310ba3d3..8683f5e01 100644
--- a/arch/sparc/isa/formats.isa
+++ b/arch/sparc/isa/formats.isa
@@ -1,28 +1,28 @@
//Include the basic format
//Templates from this format are used later
-##include "m5/arch/sparc/isa/formats/basic.isa"
+##include "formats/basic.isa"
//Include the integerOp and integerOpCc format
-##include "m5/arch/sparc/isa/formats/integerop.isa"
+##include "formats/integerop.isa"
//Include the memory format
-##include "m5/arch/sparc/isa/formats/mem.isa"
+##include "formats/mem.isa"
//Include the compare and swap format
-##include "m5/arch/sparc/isa/formats/cas.isa"
+##include "formats/cas.isa"
//Include the trap format
-##include "m5/arch/sparc/isa/formats/trap.isa"
+##include "formats/trap.isa"
//Include the "unknown" format
-##include "m5/arch/sparc/isa/formats/unknown.isa"
+##include "formats/unknown.isa"
//Include the priveleged mode format
-##include "m5/arch/sparc/isa/formats/priv.isa"
+##include "formats/priv.isa"
//Include the branch format
-##include "m5/arch/sparc/isa/formats/branch.isa"
+##include "formats/branch.isa"
//Include the noop format
-##include "m5/arch/sparc/isa/formats/noop.isa"
+##include "formats/noop.isa"
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
index 06725eae8..f1162e24b 100644
--- a/arch/sparc/isa/formats/mem.isa
+++ b/arch/sparc/isa/formats/mem.isa
@@ -34,9 +34,10 @@ def template MemExecute {{
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
+ Addr EA;
%(op_decl)s;
%(op_rd)s;
- ea_code
+ %(ea_code)s;
%(code)s;
if(fault == NoFault)
@@ -51,12 +52,17 @@ def template MemExecute {{
// Primary format for integer operate instructions:
def format Mem(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+ addrCalc = 'EA = I ? (Rs1 + SIMM13) : Rs1 + Rs2;'
+ composite = code + '\n' + addrCalc
+ origCodeBlk = CodeBlock(code)
+ compositeBlk = CodeBlock(composite)
+ addrCalcBlk = CodeBlock(addrCalc)
+ iop = InstObjParams(name, Name, 'SparcStaticInst', compositeBlk, opt_flags)
+ iop.code = origCodeBlk.code
+ iop.orig_code = origCodeBlk.orig_code
+ iop.ea_code = addrCalcBlk.code
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = MemExecute.subst(iop)
- exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
}};
diff --git a/arch/sparc/isa/formats/priv.isa b/arch/sparc/isa/formats/priv.isa
index c89e769b4..162ad5ee0 100644
--- a/arch/sparc/isa/formats/priv.isa
+++ b/arch/sparc/isa/formats/priv.isa
@@ -91,12 +91,18 @@ def template PrivExecute {{
%(op_decl)s;
%(op_rd)s;
+ //Since these are processed inside templates and not in codeblocks,
+ //They aren't translated by the isa_parser. Their names begin with
+ //underscores so they don't cause conflicts.
+ uint32_t _PstatePriv = xc->readMiscReg(MISCREG_PSTATE_PRIV);
+
//If the processor isn't in privileged mode, fault out right away
- if(!PstatePriv)
- return new PrivilegedOpcode
+ if(!_PstatePriv)
+ return new PrivilegedOpcode;
%(code)s;
%(op_wb)s;
+ return NoFault;
}
}};
@@ -107,12 +113,18 @@ def template PrivTickExecute {{
%(op_decl)s;
%(op_rd)s;
+ //Since these are processed inside templates and not in codeblocks,
+ //They aren't translated by the isa_parser. Their names begin with
+ //underscores so they don't cause conflicts.
+ uint32_t _PstatePriv = xc->readMiscReg(MISCREG_PSTATE_PRIV);
+ uint32_t _TickNpt = xc->readMiscReg(MISCREG_TICK_NPT);
//If the processor isn't in privileged mode, fault out right away
- if(!PstatePriv && TickNpt)
- return new PrivilegedAction
+ if(!_PstatePriv && _TickNpt)
+ return new PrivilegedAction;
%(code)s;
%(op_wb)s;
+ return NoFault;
}
}};
diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa
index 935fbfe6b..db4494132 100644
--- a/arch/sparc/isa/formats/trap.isa
+++ b/arch/sparc/isa/formats/trap.isa
@@ -36,6 +36,8 @@ def template TrapExecute {{
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
+ %(op_decl)s;
+ %(op_rd)s;
%(code)s
return fault;
}
diff --git a/arch/sparc/isa/main.isa b/arch/sparc/isa/main.isa
index ab0290d58..35167d6b7 100644
--- a/arch/sparc/isa/main.isa
+++ b/arch/sparc/isa/main.isa
@@ -26,7 +26,7 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-##include "m5/arch/sparc/isa/includes.isa"
+##include "includes.isa"
////////////////////////////////////////////////////////////////////
//
@@ -37,16 +37,16 @@
namespace SparcISA;
//Include the bitfield definitions
-##include "m5/arch/sparc/isa/bitfields.isa"
+##include "bitfields.isa"
//Include the operand_types and operand definitions
-##include "m5/arch/sparc/isa/operands.isa"
+##include "operands.isa"
//Include the base class for sparc instructions, and some support code
-##include "m5/arch/sparc/isa/base.isa"
+##include "base.isa"
//Include the definitions for the instruction formats
-##include "m5/arch/sparc/isa/formats.isa"
+##include "formats.isa"
//Include the decoder definition
-##include "m5/arch/sparc/isa/decoder.isa"
+##include "decoder.isa"
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa
index abfdf7bcd..0d521fae0 100644
--- a/arch/sparc/isa/operands.isa
+++ b/arch/sparc/isa/operands.isa
@@ -16,18 +16,20 @@ def operands {{
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'.
- 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
- 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2),
- 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3),
+ 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
+ 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
+ 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
+ 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
+ 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
#'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
#'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
#'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
- 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
+ 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
- 'R0': ('IntReg', 'udw', '0', None, 1),
- 'R16': ('IntReg', 'udw', '16', None, 1),
+ 'R0': ('IntReg', 'udw', '0', None, 1),
+ 'R16': ('IntReg', 'udw', '16', None, 1),
# Control registers
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
index 4886da7cf..6cf77eb0e 100644
--- a/arch/sparc/isa_traits.hh
+++ b/arch/sparc/isa_traits.hh
@@ -90,6 +90,9 @@ namespace SparcISA
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 32,
Ctrl_Base_DepTag = 96,
+ //XXX These are here solely to get compilation and won't work
+ Fpcr_DepTag = 0,
+ Uniq_DepTag = 0
};
//This makes sure the big endian versions of certain functions are used.
@@ -98,11 +101,6 @@ namespace SparcISA
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
- inline ExtMachInst
- makeExtMI(MachInst inst, const Addr &pc) {
- return ExtMachInst(inst);
- }
-
const int NumIntRegs = 32;
const int NumFloatRegs = 64;
const int NumMiscRegs = 32;
@@ -160,31 +158,6 @@ namespace SparcISA
// return a no-op instruction... used for instruction fetch faults
extern const MachInst NoopMachInst;
-
- // Instruction address compression hooks
- inline Addr realPCToFetchPC(const Addr &addr)
- {
- return addr;
- }
-
- inline Addr fetchPCToRealPC(const Addr &addr)
- {
- return addr;
- }
-
- // the size of "fetched" instructions (not necessarily the size
- // of real instructions for PISA)
- inline size_t fetchInstSize()
- {
- return sizeof(MachInst);
- }
-
- /**
- * Function to insure ISA semantics about 0 registers.
- * @param xc The execution context.
- */
- template <class XC>
- void zeroRegisters(XC *xc);
}
#include "arch/sparc/regfile.hh"
diff --git a/arch/sparc/regfile.hh b/arch/sparc/regfile.hh
index 944fdfe80..09b8e49d7 100644
--- a/arch/sparc/regfile.hh
+++ b/arch/sparc/regfile.hh
@@ -55,15 +55,15 @@ namespace SparcISA
class FloatRegFile
{
protected:
- //Since the floating point registers overlap each other,
- //A generic storage space is used. The float to be returned is
- //pulled from the appropriate section of this region.
- char regSpace[32 * 64];
-
static const int SingleWidth = 32;
static const int DoubleWidth = 64;
static const int QuadWidth = 128;
+ //Since the floating point registers overlap each other,
+ //A generic storage space is used. The float to be returned is
+ //pulled from the appropriate section of this region.
+ char regSpace[SingleWidth / 8 * NumFloatRegs];
+
public:
FloatReg readReg(int floatReg, int width)
diff --git a/arch/sparc/utility.hh b/arch/sparc/utility.hh
new file mode 100644
index 000000000..1e67b3370
--- /dev/null
+++ b/arch/sparc/utility.hh
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_SPARC_UTILITY_HH__
+#define __ARCH_SPARC_UTILITY_HH__
+
+#include "arch/sparc/isa_traits.hh"
+#include "base/misc.hh"
+
+namespace SparcISA
+{
+ inline ExtMachInst
+ makeExtMI(MachInst inst, const Addr &pc) {
+ return ExtMachInst(inst);
+ }
+
+ inline bool isCallerSaveIntegerRegister(unsigned int reg) {
+ panic("register classification not implemented");
+ return false;
+ }
+
+ inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
+ panic("register classification not implemented");
+ return false;
+ }
+
+ inline bool isCallerSaveFloatRegister(unsigned int reg) {
+ panic("register classification not implemented");
+ return false;
+ }
+
+ inline bool isCalleeSaveFloatRegister(unsigned int reg) {
+ panic("register classification not implemented");
+ return false;
+ }
+
+ // Instruction address compression hooks
+ inline Addr realPCToFetchPC(const Addr &addr)
+ {
+ return addr;
+ }
+
+ inline Addr fetchPCToRealPC(const Addr &addr)
+ {
+ return addr;
+ }
+
+ // the size of "fetched" instructions (not necessarily the size
+ // of real instructions for PISA)
+ inline size_t fetchInstSize()
+ {
+ return sizeof(MachInst);
+ }
+
+ /**
+ * Function to insure ISA semantics about 0 registers.
+ * @param xc The execution context.
+ */
+ template <class XC>
+ void zeroRegisters(XC *xc);
+
+} // namespace SparcISA
+
+#endif
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