22 files changed, 0 insertions, 3498 deletions
diff --git a/arch/sparc/SConscript b/arch/sparc/SConscript
deleted file mode 100644
index edff5821e..000000000
--- a/arch/sparc/SConscript
+++ /dev/null
@@ -1,82 +0,0 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2004-2005 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import os
-import sys
-from os.path import isdir
-
-# Import build environment variable from SConstruct.
-Import('env')
-
-###################################################
-#
-# Define needed sources.
-#
-###################################################
-
-# Base sources used by all configurations.
-base_sources = Split('''
-	faults.cc
-	isa_traits.cc
-	''')
-
-# Full-system sources
-full_system_sources = Split('''
-	tlb.cc
-	arguments.cc
-	ev5.cc
-	osfpal.cc
-	stacktrace.cc
-	vtophys.cc
-	''')
-
-# Syscall emulation (non-full-system) sources
-syscall_emulation_sources = Split('''
-	common_syscall_emul.cc
-	linux_process.cc
-	process.cc
-	''')
-
-sources = base_sources
-
-if env['FULL_SYSTEM']:
-    sources += full_system_sources
-else:
-    sources += syscall_emulation_sources
-
-# Convert file names to SCons File objects.  This takes care of the
-# path relative to the top of the directory tree.
-sources = [File(s) for s in sources]
-
-# Add in files generated by the ISA description.
-isa_desc_files = env.ISADesc('isa/main.isa')
-# Only non-header files need to be compiled.
-isa_desc_sources = [f for f in isa_desc_files if not f.path.endswith('.hh')]
-sources += isa_desc_sources
-
-Return('sources')
diff --git a/arch/sparc/faults.cc b/arch/sparc/faults.cc
deleted file mode 100644
index b48fc600b..000000000
--- a/arch/sparc/faults.cc
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/sparc/faults.hh"
-#include "cpu/exec_context.hh"
-#include "cpu/base.hh"
-#include "base/trace.hh"
-
-namespace SparcISA
-{
-
-FaultName     InternalProcessorError::_name = "intprocerr";
-TrapType      InternalProcessorError::_trapType = 0x029;
-FaultPriority InternalProcessorError::_priority = 4;
-FaultStat     InternalProcessorError::_count;
-
-FaultName     MemAddressNotAligned::_name = "unalign";
-TrapType      MemAddressNotAligned::_trapType = 0x034;
-FaultPriority MemAddressNotAligned::_priority = 10;
-FaultStat     MemAddressNotAligned::_count;
-
-FaultName     PowerOnReset::_name = "pow_reset";
-TrapType      PowerOnReset::_trapType = 0x001;
-FaultPriority PowerOnReset::_priority = 0;
-FaultStat     PowerOnReset::_count;
-
-FaultName     WatchDogReset::_name = "watch_dog_reset";
-TrapType      WatchDogReset::_trapType = 0x002;
-FaultPriority WatchDogReset::_priority = 1;
-FaultStat     WatchDogReset::_count;
-
-FaultName     ExternallyInitiatedReset::_name = "extern_reset";
-TrapType      ExternallyInitiatedReset::_trapType = 0x003;
-FaultPriority ExternallyInitiatedReset::_priority = 1;
-FaultStat     ExternallyInitiatedReset::_count;
-
-FaultName     SoftwareInitiatedReset::_name = "software_reset";
-TrapType      SoftwareInitiatedReset::_trapType = 0x004;
-FaultPriority SoftwareInitiatedReset::_priority = 1;
-FaultStat     SoftwareInitiatedReset::_count;
-
-FaultName     REDStateException::_name = "red_counte";
-TrapType      REDStateException::_trapType = 0x005;
-FaultPriority REDStateException::_priority = 1;
-FaultStat     REDStateException::_count;
-
-FaultName     InstructionAccessException::_name = "inst_access";
-TrapType      InstructionAccessException::_trapType = 0x008;
-FaultPriority InstructionAccessException::_priority = 5;
-FaultStat     InstructionAccessException::_count;
-
-FaultName     InstructionAccessMMUMiss::_name = "inst_mmu";
-TrapType      InstructionAccessMMUMiss::_trapType = 0x009;
-FaultPriority InstructionAccessMMUMiss::_priority = 2;
-FaultStat     InstructionAccessMMUMiss::_count;
-
-FaultName     InstructionAccessError::_name = "inst_error";
-TrapType      InstructionAccessError::_trapType = 0x00A;
-FaultPriority InstructionAccessError::_priority = 3;
-FaultStat     InstructionAccessError::_count;
-
-FaultName     IllegalInstruction::_name = "illegal_inst";
-TrapType      IllegalInstruction::_trapType = 0x010;
-FaultPriority IllegalInstruction::_priority = 7;
-FaultStat     IllegalInstruction::_count;
-
-FaultName     PrivelegedOpcode::_name = "priv_opcode";
-TrapType      PrivelegedOpcode::_trapType = 0x011;
-FaultPriority PrivelegedOpcode::_priority = 6;
-FaultStat     PrivelegedOpcode::_count;
-
-FaultName     UnimplementedLDD::_name = "unimp_ldd";
-TrapType      UnimplementedLDD::_trapType = 0x012;
-FaultPriority UnimplementedLDD::_priority = 6;
-FaultStat     UnimplementedLDD::_count;
-
-FaultName     UnimplementedSTD::_name = "unimp_std";
-TrapType      UnimplementedSTD::_trapType = 0x013;
-FaultPriority UnimplementedSTD::_priority = 6;
-FaultStat     UnimplementedSTD::_count;
-
-FaultName     FpDisabled::_name = "fp_disabled";
-TrapType      FpDisabled::_trapType = 0x020;
-FaultPriority FpDisabled::_priority = 8;
-FaultStat     FpDisabled::_count;
-
-FaultName     FpExceptionIEEE754::_name = "fp_754";
-TrapType      FpExceptionIEEE754::_trapType = 0x021;
-FaultPriority FpExceptionIEEE754::_priority = 11;
-FaultStat     FpExceptionIEEE754::_count;
-
-FaultName     FpExceptionOther::_name = "fp_other";
-TrapType      FpExceptionOther::_trapType = 0x022;
-FaultPriority FpExceptionOther::_priority = 11;
-FaultStat     FpExceptionOther::_count;
-
-FaultName     TagOverflow::_name = "tag_overflow";
-TrapType      TagOverflow::_trapType = 0x023;
-FaultPriority TagOverflow::_priority = 14;
-FaultStat     TagOverflow::_count;
-
-FaultName     DivisionByZero::_name = "div_by_zero";
-TrapType      DivisionByZero::_trapType = 0x028;
-FaultPriority DivisionByZero::_priority = 15;
-FaultStat     DivisionByZero::_count;
-
-FaultName     DataAccessException::_name = "data_access";
-TrapType      DataAccessException::_trapType = 0x030;
-FaultPriority DataAccessException::_priority = 12;
-FaultStat     DataAccessException::_count;
-
-FaultName     DataAccessMMUMiss::_name = "data_mmu";
-TrapType      DataAccessMMUMiss::_trapType = 0x031;
-FaultPriority DataAccessMMUMiss::_priority = 12;
-FaultStat     DataAccessMMUMiss::_count;
-
-FaultName     DataAccessError::_name = "data_error";
-TrapType      DataAccessError::_trapType = 0x032;
-FaultPriority DataAccessError::_priority = 12;
-FaultStat     DataAccessError::_count;
-
-FaultName     DataAccessProtection::_name = "data_protection";
-TrapType      DataAccessProtection::_trapType = 0x033;
-FaultPriority DataAccessProtection::_priority = 12;
-FaultStat     DataAccessProtection::_count;
-
-FaultName     LDDFMemAddressNotAligned::_name = "unalign_lddf";
-TrapType      LDDFMemAddressNotAligned::_trapType = 0x035;
-FaultPriority LDDFMemAddressNotAligned::_priority = 10;
-FaultStat     LDDFMemAddressNotAligned::_count;
-
-FaultName     STDFMemAddressNotAligned::_name = "unalign_stdf";
-TrapType      STDFMemAddressNotAligned::_trapType = 0x036;
-FaultPriority STDFMemAddressNotAligned::_priority = 10;
-FaultStat     STDFMemAddressNotAligned::_count;
-
-FaultName     PrivelegedAction::_name = "priv_action";
-TrapType      PrivelegedAction::_trapType = 0x037;
-FaultPriority PrivelegedAction::_priority = 11;
-FaultStat     PrivelegedAction::_count;
-
-FaultName     LDQFMemAddressNotAligned::_name = "unalign_ldqf";
-TrapType      LDQFMemAddressNotAligned::_trapType = 0x038;
-FaultPriority LDQFMemAddressNotAligned::_priority = 10;
-FaultStat     LDQFMemAddressNotAligned::_count;
-
-FaultName     STQFMemAddressNotAligned::_name = "unalign_stqf";
-TrapType      STQFMemAddressNotAligned::_trapType = 0x039;
-FaultPriority STQFMemAddressNotAligned::_priority = 10;
-FaultStat     STQFMemAddressNotAligned::_count;
-
-FaultName     AsyncDataError::_name = "async_data";
-TrapType      AsyncDataError::_trapType = 0x040;
-FaultPriority AsyncDataError::_priority = 2;
-FaultStat     AsyncDataError::_count;
-
-//The enumerated faults
-
-FaultName     CleanWindow::_name = "clean_win";
-TrapType      CleanWindow::_baseTrapType = 0x024;
-FaultPriority CleanWindow::_priority = 10;
-FaultStat     CleanWindow::_count;
-
-FaultName     InterruptLevelN::_name = "interrupt_n";
-TrapType      InterruptLevelN::_baseTrapType = 0x041;
-FaultStat     InterruptLevelN::_count;
-
-FaultName     SpillNNormal::_name = "spill_n_normal";
-TrapType      SpillNNormal::_baseTrapType = 0x080;
-FaultPriority SpillNNormal::_priority = 9;
-FaultStat     SpillNNormal::_count;
-
-FaultName     SpillNOther::_name = "spill_n_other";
-TrapType      SpillNOther::_baseTrapType = 0x0A0;
-FaultPriority SpillNOther::_priority = 9;
-FaultStat     SpillNOther::_count;
-
-FaultName     FillNNormal::_name = "fill_n_normal";
-TrapType      FillNNormal::_baseTrapType = 0x0C0;
-FaultPriority FillNNormal::_priority = 9;
-FaultStat     FillNNormal::_count;
-
-FaultName     FillNOther::_name = "fill_n_other";
-TrapType      FillNOther::_baseTrapType = 0x0E0;
-FaultPriority FillNOther::_priority = 9;
-FaultStat     FillNOther::_count;
-
-FaultName     TrapInstruction::_name = "trap_inst_n";
-TrapType      TrapInstruction::_baseTrapType = 0x100;
-FaultPriority TrapInstruction::_priority = 16;
-FaultStat     TrapInstruction::_count;
-
-
-
-#if FULL_SYSTEM
-
-void SparcFault::invoke(ExecContext * xc)
-{
-    FaultBase::invoke(xc);
-    countStat()++;
-
-    //Use the SPARC trap state machine
-    /*// exception restart address
-    if (setRestartAddress() || !xc->inPalMode())
-        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
-
-    if (skipFaultingInstruction()) {
-        // traps...  skip faulting instruction.
-        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
-                   xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
-    }
-
-    if (!xc->inPalMode())
-        AlphaISA::swap_palshadow(&(xc->regs), true);
-
-    xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
-    xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/
-}
-
-#endif
-
-} // namespace SparcISA
-
diff --git a/arch/sparc/faults.hh b/arch/sparc/faults.hh
deleted file mode 100644
index 318b1ad5a..000000000
--- a/arch/sparc/faults.hh
+++ /dev/null
@@ -1,587 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ALPHA_FAULTS_HH__
-#define __ALPHA_FAULTS_HH__
-
-#include "sim/faults.hh"
-
-// The design of the "name" and "vect" functions is in sim/faults.hh
-
-namespace SparcISA
-{
-
-typedef const uint32_t TrapType;
-typedef const uint32_t FaultPriority;
-
-class SparcFault : public FaultBase
-{
-  public:
-#if FULL_SYSTEM
-    void invoke(ExecContext * xc);
-#endif
-    virtual TrapType trapType() = 0;
-    virtual FaultPriority priority() = 0;
-    virtual FaultStat & countStat() = 0;
-};
-
-class InternalProcessorError : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-    bool isMachineCheckFault() {return true;}
-};
-
-class MemAddressNotAligned : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-    bool isAlignmentFault() {return true;}
-};
-
-static inline Fault genMachineCheckFault()
-{
-    return new InternalProcessorError;
-}
-
-static inline Fault genAlignmentFault()
-{
-    return new MemAddressNotAligned;
-}
-
-class PowerOnReset : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class WatchDogReset : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class ExternallyInitiatedReset : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class SoftwareInitiatedReset : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class REDStateException : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class InstructionAccessException : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class InstructionAccessMMUMiss : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class InstructionAccessError : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class IllegalInstruction : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class PrivelegedOpcode : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class UnimplementedLDD : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class UnimplementedSTD : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class FpDisabled : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class FpExceptionIEEE754 : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class FpExceptionOther : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class TagOverflow : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class DivisionByZero : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class DataAccessException : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class DataAccessMMUMiss : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class DataAccessError : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class DataAccessProtection : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class LDDFMemAddressNotAligned : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class STDFMemAddressNotAligned : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class PrivelegedAction : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class LDQFMemAddressNotAligned : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class STQFMemAddressNotAligned : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class AsyncDataError : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-  public:
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class EnumeratedFault : public SparcFault
-{
-  protected:
-    uint32_t _n;
-    virtual TrapType baseTrapType() = 0;
-  public:
-    EnumeratedFault(uint32_t n) : SparcFault() {_n = n;}
-    TrapType trapType() {return baseTrapType() + _n;}
-};
-
-class CleanWindow : public EnumeratedFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _baseTrapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-    TrapType baseTrapType() {return _baseTrapType;}
-  public:
-    CleanWindow(uint32_t n) : EnumeratedFault(n) {;}
-    FaultName name() {return _name;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class InterruptLevelN : public EnumeratedFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _baseTrapType;
-    static FaultStat _count;
-    TrapType baseTrapType() {return _baseTrapType;}
-  public:
-    InterruptLevelN(uint32_t n) : EnumeratedFault(n) {;}
-    FaultName name() {return _name;}
-    FaultPriority priority() {return 32 - _n;}
-    FaultStat & countStat() {return _count;}
-};
-
-class SpillNNormal : public EnumeratedFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _baseTrapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-    TrapType baseTrapType() {return _baseTrapType;}
-  public:
-    SpillNNormal(uint32_t n) : EnumeratedFault(n) {;}
-    FaultName name() {return _name;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class SpillNOther : public EnumeratedFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _baseTrapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-    TrapType baseTrapType() {return _baseTrapType;}
-  public:
-    SpillNOther(uint32_t n) : EnumeratedFault(n) {;}
-    FaultName name() {return _name;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class FillNNormal : public EnumeratedFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _baseTrapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-    TrapType baseTrapType() {return _baseTrapType;}
-  public:
-    FillNNormal(uint32_t n) : EnumeratedFault(n) {;}
-    FaultName name() {return _name;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class FillNOther : public EnumeratedFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _baseTrapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-    TrapType baseTrapType() {return _baseTrapType;}
-  public:
-    FillNOther(uint32_t n) : EnumeratedFault(n) {;}
-    FaultName name() {return _name;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-class TrapInstruction : public EnumeratedFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _baseTrapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-    TrapType baseTrapType() {return _baseTrapType;}
-  public:
-    TrapInstruction(uint32_t n) : EnumeratedFault(n) {;}
-    FaultName name() {return _name;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-};
-
-} // SparcISA namespace
-
-#endif // __FAULTS_HH__
diff --git a/arch/sparc/isa/base.isa b/arch/sparc/isa/base.isa
deleted file mode 100644
index 992504369..000000000
--- a/arch/sparc/isa/base.isa
+++ /dev/null
@@ -1,129 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Base class for sparc instructions, and some support functions
-//
-
-output header {{
-
-        struct condCodes
-        {
-            uint8_t c:1;
-            uint8_t v:1;
-            uint8_t z:1;
-            uint8_t n:1;
-        }
-
-        enum condTest
-        {
-            Always=0x8,
-            Never=0x0,
-            NotEqual=0x9,
-            Equal=0x1,
-            Greater=0xA,
-            LessOrEqual=0x2,
-            GreaterOrEqual=0xB,
-            Less=0x3,
-            GreaterUnsigned=0xC,
-            LessOrEqualUnsigned=0x4,
-            CarryClear=0xD,
-            CarrySet=0x5,
-            Positive=0xE,
-            Negative=0x6,
-            OverflowClear=0xF,
-            OverflowSet=0x7
-        }
-
-        /**
-         * Base class for all SPARC static instructions.
-         */
-        class SparcStaticInst : public StaticInst
-        {
-          protected:
-            // Constructor.
-            SparcStaticInst(const char *mnem,
-                 MachInst _machInst, OpClass __opClass)
-                    : StaticInst(mnem, _machInst, __opClass)
-                {
-                }
-
-            std::string generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const;
-        };
-
-        bool passesCondition(condCodes codes, condTest condition);
-}};
-
-output decoder {{
-
-        std::string SparcStaticInst::generateDisassembly(Addr pc,
-            const SymbolTable *symtab) const
-        {
-            std::stringstream ss;
-
-            ccprintf(ss, "%-10s ", mnemonic);
-
-            // just print the first two source regs... if there's
-            // a third one, it's a read-modify-write dest (Rc),
-            // e.g. for CMOVxx
-            if(_numSrcRegs > 0)
-            {
-                printReg(ss, _srcRegIdx[0]);
-            }
-            if(_numSrcRegs > 1)
-            {
-                ss << ",";
-                printReg(ss, _srcRegIdx[1]);
-            }
-
-            // just print the first dest... if there's a second one,
-            // it's generally implicit
-            if(_numDestRegs > 0)
-            {
-                if(_numSrcRegs > 0)
-                    ss << ",";
-                    printReg(ss, _destRegIdx[0]);
-            }
-
-            return ss.str();
-        }
-
-        bool passesCondition(condCodes codes, condTest condition)
-        {
-            switch(condition)
-            {
-              case Always:
-                return true;
-              case Never:
-                return false;
-              case NotEqual:
-                return !codes.z;
-              case Equal:
-                return codes.z;
-              case Greater:
-                return !(codes.z | (codes.n ^ codes.v));
-              case LessOrEqual:
-                return codes.z | (codes.n ^ codes.v);
-              case GreaterOrEqual:
-                return !(codes.n ^ codes.v);
-              case Less:
-                return (codes.n ^ codes.v);
-              case GreaterUnsigned:
-                return !(codes.c | codes.z);
-              case LessOrEqualUnsigned:
-                return (codes.c | codes.z);
-              case CarryClear:
-                return !codes.c;
-              case CarrySet:
-                return codes.c;
-              case Positive:
-                return !codes.n;
-              case Negative:
-                return codes.n;
-              case OverflowClear:
-                return !codes.v;
-              case OverflowSet:
-                return codes.v;
-            }
-        }
-}};
-
diff --git a/arch/sparc/isa/bitfields.isa b/arch/sparc/isa/bitfields.isa
deleted file mode 100644
index b0ac57575..000000000
--- a/arch/sparc/isa/bitfields.isa
+++ /dev/null
@@ -1,50 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Bitfield definitions.
-//
-
-// Bitfields are shared liberally between instruction formats, so they are
-// simply defined alphabetically
-
-def bitfield A		<29>;
-def bitfield CC02	<20>;
-def bitfield CC03	<25>;
-def bitfield CC04	<11>;
-def bitfield CC12	<21>;
-def bitfield CC13	<26>;
-def bitfield CC14	<12>;
-def bitfield CC2	<18>;
-def bitfield CMASK	<6:4>;
-def bitfield COND2	<28:25>;
-def bitfield COND4	<17:14>;
-def bitfield D16HI	<21:20>;
-def bitfield D16LO	<13:0>;
-def bitfield DISP19	<18:0>;
-def bitfield DISP22	<21:0>;
-def bitfield DISP30	<29:0>;
-def bitfield FCN	<29:26>;
-def bitfield I		<13>;
-def bitfield IMM_ASI	<12:5>;
-def bitfield IMM22	<21:0>;
-def bitfield MMASK	<3:0>;
-def bitfield OP		<31:30>;
-def bitfield OP2	<24:22>;
-def bitfield OP3	<24:19>;
-def bitfield OPF	<13:5>;
-def bitfield OPF_CC	<13:11>;
-def bitfield OPF_LOW5	<9:5>;
-def bitfield OPF_LOW6	<10:5>;
-def bitfield P		<19>;
-def bitfield RCOND2	<27:25>;
-def bitfield RCOND3	<12:10>;
-def bitfield RCOND4	<12:10>;
-def bitfield RD		<29:25>;
-def bitfield RS1	<18:14>;
-def bitfield RS2	<4:0>;
-def bitfield SHCNT32	<4:0>;
-def bitfield SHCNT64	<5:0>;
-def bitfield SIMM10	<9:0>;
-def bitfield SIMM11	<10:0>;
-def bitfield SIMM13	<12:0>;
-def bitfield SW_TRAP	<6:0>;
-def bitfield X		<12>;
diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
deleted file mode 100644
index eb458211b..000000000
--- a/arch/sparc/isa/decoder.isa
+++ /dev/null
@@ -1,662 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// The actual decoder specification
-//
-
-decode OP default Trap::unknown({{IllegalInstruction}}) {
-
-        0x0: decode OP2 {
-            0x0: Trap::illtrap({{illegal_instruction}});  //ILLTRAP
-            0x1: Branch::bpcc({{
-                switch((CC12 << 1) | CC02)
-                {
-                  case 1:
-                  case 3:
-                    fault = new IllegalInstruction;
-                  case 0:
-                    if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
-                        ;//branchHere
-                    break;
-                  case 2:
-                    if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND2))
-                        ;//branchHere
-                    break;
-                }
-            }});//BPcc
-            0x2: Branch::bicc({{
-                if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
-                    ;//branchHere
-            }});//Bicc
-            0x3: Branch::bpr({{
-                switch(RCOND)
-                {
-                  case 0:
-                  case 4:
-                    fault = new IllegalInstruction;
-                  case 1:
-                    if(Rs1 == 0)
-                        ;//branchHere
-                    break;
-                  case 2:
-                    if(Rs1 <= 0)
-                        ;//branchHere
-                    break;
-                  case 3:
-                    if(Rs1 < 0)
-                        ;//branchHere
-                    break;
-                  case 5:
-                    if(Rs1 != 0)
-                        ;//branchHere
-                    break;
-                  case 6:
-                    if(Rs1 > 0)
-                        ;//branchHere
-                    break;
-                  case 7:
-                    if(Rs1 >= 0)
-                        ;//branchHere
-                    break;
-                }
-                }});    //BPr
-                //SETHI (or NOP if rd == 0 and imm == 0)
-                0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
-                0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc
-                0x6: Trap::fbfcc({{throw fp_disabled;}});  //FBfcc
-        }
-        0x1: Branch::call({{
-                //branch here
-                Rd = xc->pc;
-        }});
-        0x2: decode OP3 {
-            format IntegerOp {
-                0x00: add({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                    Rd = Rs1.sdw + val2;
-                }});//ADD
-                0x01: and({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = Rs1.udw & val2;
-                }});//AND
-                0x02: or({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = Rs1.udw | val2;
-                }});//OR
-                0x03: xor({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = Rs1.udw ^ val2;
-                }});//XOR
-                0x04: sub({{
-                    int64_t val2 = ~((uint64_t)(I ? SIMM13.sdw : Rs2.udw))+1;
-                    Rd = Rs1.sdw + val2;
-                }});//SUB
-                0x05: andn({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = Rs1.udw & ~val2;
-                }});//ANDN
-                0x06: orn({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = Rs1.udw | ~val2;
-                }});//ORN
-                0x07: xnor({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = ~(Rs1.udw ^ val2);
-                }});//XNOR
-                0x08: addc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                    int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
-                    Rd = Rs1.sdw + val2 + carryin;
-                }});//ADDC
-                0x09: mulx({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = Rs1 * val2;
-                }});//MULX
-                0x0A: umul({{
-                    uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
-                    xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
-                }});//UMUL
-                0x0B: smul({{
-                    int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                    rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
-                    xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
-                }});//SMUL
-                0x0C: subc({{
-                    int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1;
-                    int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
-                    Rd.sdw = Rs1.sdw + val2 + carryin;
-                }});//SUBC
-                0x0D: udivx({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    if(val2 == 0) throw division_by_zero;
-                    Rd.udw = Rs1.udw / val2;
-                }});//UDIVX
-                0x0E: udiv({{
-                    uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
-                    if(val2 == 0)
-                        fault = new DivisionByZero;
-                    resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32)
-                        | Rs1.udw<31:0>) / val2;
-                    int32_t overflow = (resTemp<63:32> != 0);
-                    if(overflow)
-                        rd.udw = resTemp = 0xFFFFFFFF;
-                    else
-                        rd.udw = resTemp;
-                }});   //UDIV
-                0x0F: sdiv({{
-                    int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
-                    if(val2 == 0)
-                        fault = new DivisionByZero;
-
-                    Rd.sdw = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) |
-                        Rs1.sdw<31:0>) / val2;
-                    resTemp = Rd.sdw;
-                    int32_t overflow = (resTemp<63:31> != 0);
-                    int32_t underflow =
-                        (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
-                    if(overflow)
-                        rd.udw = resTemp = 0x7FFFFFFF;
-                    else if(underflow)
-                        rd.udw = resTemp = 0xFFFFFFFF80000000;
-                    else
-                        rd.udw = resTemp;
-                }});//SDIV
-            }
-            format IntegerOpCc {
-                0x10: addcc({{
-                    int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = resTemp = Rs1 + val2;}},
-                    {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                    {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
-                    {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                    {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                    );//ADDcc
-                0x11: andcc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = Rs1 & val2;}},
-                    {{0}},{{0}},{{0}},{{0}});//ANDcc
-                0x12: orcc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = Rs1 | val2;}},
-                    {{0}},{{0}},{{0}},{{0}});//ORcc
-                0x13: xorcc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = Rs1 ^ val2;}},
-                    {{0}},{{0}},{{0}},{{0}});//XORcc
-                0x14: subcc({{
-                    int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
-                    Rd = resTemp = Rs1 - val2;}},
-                    {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
-                    {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
-                    {{((Rs1 >> 1) + (~val2) >> 1) +
-                        ((Rs1 | ~val2) & 0x1))<63:>}},
-                    {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
-                );//SUBcc
-                0x15: andncc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = Rs1 & ~val2;}},
-                    {{0}},{{0}},{{0}},{{0}});//ANDNcc
-                0x16: orncc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = Rs1 | ~val2;}},
-                    {{0}},{{0}},{{0}},{{0}});//ORNcc
-                0x17: xnorcc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = ~(Rs1 ^ val2);}},
-                    {{0}},{{0}},{{0}},{{0}});//XNORcc
-                0x18: addccc({{
-                    int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                    int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
-                    Rd = resTemp = Rs1 + val2 + carryin;}},
-                    {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
-                        + carryin)}},
-                    {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
-                    {{((Rs1 >> 1) + (val2 >> 1) +
-                        ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
-                    {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                );//ADDCcc
-                0x1A: umulcc({{
-                    uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
-                    xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}},
-                    {{0}},{{0}},{{0}},{{0}});//UMULcc
-                        0x1B: smulcc({{
-                                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
-                                xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
-                        ,{{0}},{{0}},{{0}},{{0}});//SMULcc
-                        0x1C: subccc({{
-                                int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
-                                int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
-                                Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
-                                {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
-                                {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
-                                {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
-                                {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
-                        );//SUBCcc
-                        0x1D: udivxcc({{
-                                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                                if(val2 == 0) throw division_by_zero;
-                                Rd.udw = Rs1.udw / val2;}}
-                        ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
-                        0x1E: udivcc({{
-                                uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
-                                if(val2 == 0) throw division_by_zero;
-                                resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
-                                int32_t overflow = (resTemp<63:32> != 0);
-                                if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
-                                else rd.udw = resTemp;}},
-                                {{0}},
-                                {{overflow}},
-                                {{0}},
-                                {{0}}
-                        );//UDIVcc
-                        0x1F: sdivcc({{
-                                int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
-                                if(val2 == 0) throw division_by_zero;
-                                Rd.sdw = resTemp = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
-                                int32_t overflow = (resTemp<63:31> != 0);
-                                int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
-                                if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
-                                else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
-                                else rd.udw = resTemp;}},
-                                {{0}},
-                                {{overflow || underflow}},
-                                {{0}},
-                                {{0}}
-                        );//SDIVcc
-                        0x20: taddcc({{
-                                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;
-                                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
-                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{overflow}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//TADDcc
-                        0x21: tsubcc({{
-                                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;
-                                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
-                                {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{overflow}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//TSUBcc
-                        0x22: taddcctv({{
-                                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;
-                                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
-                                if(overflow) throw tag_overflow;}},
-                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{overflow}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//TADDccTV
-                        0x23: tsubcctv({{
-                                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;
-                                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
-                                if(overflow) throw tag_overflow;}},
-                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{overflow}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//TSUBccTV
-                        0x24: mulscc({{
-                                int64_t resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
-                                int32_t multiplier = Rs1<31:0>;
-                                int32_t savedLSB = Rs1<0:>;
-                                multiplier = multipler<31:1> |
-                                        ((xc->regs.MiscRegs.ccrFields.iccFields.n
-                                        ^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32);
-                                if(!xc->regs.MiscRegs.yFields.value<0:>)
-                                        multiplicand = 0;
-                                Rd = resTemp = multiplicand + multiplier;
-                                xc->regs.MiscRegs.yFields.value = xc->regs.MiscRegs.yFields.value<31:1> | (savedLSB << 31);}},
-                                {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
-                                {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
-                                {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
-                                {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
-                        );//MULScc
-                }
-                format IntegerOp
-                {
-                        0x25: decode X {
-                                0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL
-                                0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX
-                        }
-                        0x26: decode X {
-                                0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL
-                                0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX
-                        }
-                        0x27: decode X {
-                                0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
-                                0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
-                        }
-                        0x28: decode RS1 {
-                                0x0: rdy({{Rd = xc->regs.MiscRegs.yFields.value;}}); //RDY
-                                0x2: rdccr({{Rd = xc->regs.MiscRegs.ccr;}}); //RDCCR
-                                0x3: rdasi({{Rd = xc->regs.MiscRegs.asi;}}); //RDASI
-                                0x4: rdtick({{
-                                        if(xc->regs.MiscRegs.pstateFields.priv == 0 &&
-                                                xc->regs.MiscRegs.tickFields.npt == 1)
-                                                throw privileged_action;
-                                        Rd = xc->regs.MiscRegs.tick;
-                                }});//RDTICK
-                                0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
-                                0x6: rdfprs({{Rd = xc->regs.MiscRegs.fprs;}}); //RDFPRS
-                                0xF: decode I {
-                                        0x0: Noop::membar({{//Membar isn't needed yet}}); //MEMBAR
-                                        0x1: Noop::stbar({{//Stbar isn/'t needed yet}}); //STBAR
-                                }
-                        }
-
-                        0x2A: decode RS1 {
-                                0x0: rdprtpc({{checkPriv Rd = xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl];}});
-                                0x1: rdprtnpc({{checkPriv Rd = xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl];}});
-                                0x2: rdprtstate({{checkPriv Rd = xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl];}});
-                                0x3: rdprtt({{checkPriv Rd = xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl];}});
-                                0x4: rdprtick({{checkPriv Rd = xc->regs.MiscRegs.tick;}});
-                                0x5: rdprtba({{checkPriv Rd = xc->regs.MiscRegs.tba;}});
-                                0x6: rdprpstate({{checkPriv Rd = xc->regs.MiscRegs.pstate;}});
-                                0x7: rdprtl({{checkPriv Rd = xc->regs.MiscRegs.tl;}});
-                                0x8: rdprpil({{checkPriv Rd = xc->regs.MiscRegs.pil;}});
-                                0x9: rdprcwp({{checkPriv Rd = xc->regs.MiscRegs.cwp;}});
-                                0xA: rdprcansave({{checkPriv Rd = xc->regs.MiscRegs.cansave;}});
-                                0xB: rdprcanrestore({{checkPriv Rd = xc->regs.MiscRegs.canrestore;}});
-                                0xC: rdprcleanwin({{checkPriv Rd = xc->regs.MiscRegs.cleanwin;}});
-                                0xD: rdprotherwin({{checkPriv Rd = xc->regs.MiscRegs.otherwin;}});
-                                0xE: rdprwstate({{checkPriv Rd = xc->regs.MiscRegs.wstate;}});
-                                0xF: rdprfq({{throw illegal_instruction;}}); //The floating point queue isn't implemented right now.
-                        }
-                        0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
-                        0x2C: movcc({{
-                                ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0);
-                                switch(ccBank)
-                                {
-                                        case 0: case 1: case 2: case 3:
-                                                throw fp_disabled;
-                                        break;
-                                        case 5: case 7:
-                                                throw illegal_instruction;
-                                        break;
-                                        case 4:
-                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND4))
-                                                        Rd = (I ? SIMM11.sdw : RS2);
-                                        break;
-                                        case 6:
-                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND4))
-                                                        Rd = (I ? SIMM11.sdw : RS2);
-                                        break;
-                                }
-                        }});//MOVcc
-                        0x2D: sdivx({{
-                                int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                if(val2 == 0) throw division_by_zero;
-                                Rd.sdw = Rs1.sdw / val2;
-                        }});//SDIVX
-                        0x2E: decode RS1 {
-                                0x0: IntegerOp::popc({{
-                                int64_t count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
-                                for(unsigned int x = 0; x < 16; x++)
-                                {
-                                        count += oneBits[val2 & 0xF];
-                                        val2 >> 4;
-                                }
-                                }});//POPC
-                        }
-                        0x2F: movr({{
-                                uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw);
-                                switch(RCOND)
-                                {
-                                        case 0: case 4:
-                                                throw illegal_instruction;
-                                        break;
-                                        case 1:
-                                                if(Rs1 == 0) Rd = val2;
-                                        break;
-                                        case 2:
-                                                if(Rs1 <= 0) Rd = val2;
-                                        break;
-                                        case 3:
-                                                if(Rs1 = 0) Rd = val2;
-                                        break;
-                                        case 5:
-                                                if(Rs1 != 0) Rd = val2;
-                                        break;
-                                        case 6:
-                                                if(Rs1 > 0) Rd = val2;
-                                        break;
-                                        case 7:
-                                                if(Rs1 >= 0) Rd = val2;
-                                        break;
-                                }
-                        }});//MOVR
-                        0x30: decode RD {
-                                0x0: wry({{
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.y = Rs1 ^ val2;
-                                }});//WRY
-                                0x2: wrccr({{
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.ccr = Rs1 ^ val2;
-                                }});//WRCCR
-                                0x3: wrasi({{
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.asi = Rs1 ^ val2;
-                                }});//WRASI
-                                0x6: wrfprs({{
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.asi = Rs1 ^ val2;
-                                }});//WRFPRS
-                                0xF: Trap::sir({{software_initiated_reset}}); //SIR
-                        }
-                        0x31: decode FCN {
-                                0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED
-                                0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED
-                        }
-                        0x32: decode RD {
-                                0x0: wrprtpc({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
-                                }});
-                                0x1: wrprtnpc({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
-                                }});
-                                0x2: wrprtstate({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
-                                }});
-                                0x3: wrprtt({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
-                                }});
-                                0x4: wrprtick({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tick = Rs1 ^ val2;
-                                }});
-                                0x5: wrprtba({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tba = Rs1 ^ val2;
-                                }});
-                                0x6: wrprpstate({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.pstate = Rs1 ^ val2;
-                                }});
-                                0x7: wrprtl({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tl = Rs1 ^ val2;
-                                }});
-                                0x8: wrprpil({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.pil = Rs1 ^ val2;
-                                }});
-                                0x9: wrprcwp({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.cwp = Rs1 ^ val2;
-                                }});
-                                0xA: wrprcansave({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.cansave = Rs1 ^ val2;
-                                }});
-                                0xB: wrprcanrestore({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.canrestore = Rs1 ^ val2;
-                                }});
-                                0xC: wrprcleanwin({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.cleanwin = Rs1 ^ val2;
-                                }});
-                                0xD: wrprotherwin({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.otherwin = Rs1 ^ val2;
-                                }});
-                                0xE: wrprwstate({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.wstate = Rs1 ^ val2;
-                                }});
-                        }
-
-                        0x34: Trap::fpop1({{Throw fp_disabled;}}); //FPOP1
-                        0x35: Trap::fpop2({{Throw fp_disabled;}}); //FPOP2
-
-
-                        0x38: Branch::jmpl({{//Stuff}}); //JMPL
-                        0x39: Branch::return({{//Other Stuff}}); //RETURN
-                        0x3A: Trap::tcc({{
-                                switch((CC14 << 1) | (CC04 << 0))
-                                {
-                                        case 1: case 3:
-                                                throw illegal_instruction;
-                                        case 0:
-                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>))
-                                                        throw trap_instruction;
-                                        break;
-                                        case 2:
-                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>))
-                                                        throw trap_instruction;
-                                        break;
-                                }
-                        }}); //Tcc
-                        0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
-                        0x3C: BasicOperate::save({{//leprechauns); //SAVE
-                        0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
-                        0x3E: decode FCN {
-                                0x1: BasicOperate::done({{//Done thing}}); //DONE
-                                0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
-                        }
-                }
-        }
-        0x3: decode OP3 {
-                format Mem {
-                        0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW
-                        0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
-                        0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
-                        0x03: ldd({{
-                                uint64_t val = Mem.udw;
-                                setIntReg(RD & (~1), val<31:0>);
-                                setIntReg(RD | 1, val<63:32>);
-                        }});//LDD
-                        0x04: stw({{Mem.sw = Rd.sw;}}); //STW
-                        0x05: stb({{Mem.sb = Rd.sb;}}); //STB
-                        0x06: sth({{Mem.shw = Rd.shw;}}); //STH
-                        0x07: std({{
-                                Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
-                        }});//STD
-                        0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
-                        0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
-                        0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH
-                        0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX
-
-                        0x0D: ldstub({{
-                                Rd.ub = Mem.ub;
-                                Mem.ub = 0xFF;
-                        }}); //LDSTUB
-                        0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
-                        0x0F: swap({{
-                                uint32_t temp = Rd.uw;
-                                Rd.uw = Mem.uw;
-                                Mem.uw = temp;
-                        }}); //SWAP
-                        0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA
-                        0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
-                        0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
-                        0x13: ldda({{
-                                uint64_t val = Mem.udw;
-                                setIntReg(RD & (~1), val<31:0>);
-                                setIntReg(RD | 1, val<63:32>);
-                        }}); //LDDA
-                        0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
-                        0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
-                        0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
-                        0x17: stda({{
-                                Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
-                        }}); //STDA
-                        0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
-                        0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
-                        0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA
-                        0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA
-
-                        0x1D: ldstuba({{
-                                Rd.ub = Mem.ub;
-                                Mem.ub = 0xFF;
-                        }}); //LDSTUBA
-                        0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
-                        0x1F: swapa({{
-                                uint32_t temp = Rd.uw;
-                                Rd.uw = Mem.uw;
-                                Mem.uw = temp;
-                        }}); //SWAPA
-                        0x20: Trap::ldf({{throw fp_disabled;}}); //LDF
-                        0x21: decode X {
-                                0x0: Trap::ldfsr({{throw fp_disabled;}}); //LDFSR
-                                0x1: Trap::ldxfsr({{throw fp_disabled;}}); //LDXFSR
-                        }
-                        0x22: Trap::ldqf({{throw fp_disabled;}}); //LDQF
-                        0x23: Trap::lddf({{throw fp_disabled;}}); //LDDF
-                        0x24: Trap::stf({{throw fp_disabled;}}); //STF
-                        0x25: decode X {
-                                0x0: Trap::stfsr({{throw fp_disabled;}}); //STFSR
-                                0x1: Trap::stxfsr({{throw fp_disabled;}}); //STXFSR
-                        }
-                        0x26: Trap::stqf({{throw fp_disabled;}}); //STQF
-                        0x27: Trap::stdf({{throw fp_disabled;}}); //STDF
-
-
-
-
-
-                        0x2D: Noop::prefetch({{ }}); //PREFETCH
-
-
-                        0x30: Trap::ldfa({{throw fp_disabled;}}); //LDFA
-
-                        0x32: Trap::ldqfa({{throw fp_disabled;}}); //LDQFA
-                        0x33: Trap::lddfa({{throw fp_disabled;}}); //LDDFA
-                        0x34: Trap::stfa({{throw fp_disabled;}}); //STFA
-                        0x35: Trap::stqfa({{throw fp_disabled;}}); //STQFA
-                        0x36: Trap::stdfa({{throw fp_disabled;}}); //STDFA
-
-
-
-
-
-                        0x3C: Cas::casa(
-                                {{uint64_t val = Mem.uw;
-                                if(Rs2.uw == val)
-                                        Mem.uw = Rd.uw;
-                                Rd.uw = val;
-                        }}); //CASA
-                        0x3D: Noop::prefetcha({{ }}); //PREFETCHA
-                        0x3E: Cas::casxa(
-                                {{uint64_t val = Mem.udw;
-                                if(Rs2 == val)
-                                        Mem.udw = Rd;
-                                Rd = val;
-                        }}); //CASXA
-                }
-        }
-}
diff --git a/arch/sparc/isa/formats.isa b/arch/sparc/isa/formats.isa
deleted file mode 100644
index 547f8be48..000000000
--- a/arch/sparc/isa/formats.isa
+++ /dev/null
@@ -1,19 +0,0 @@
-//Include the basic format
-//Templates from this format are used later
-##include "m5/arch/sparc/isa/formats/basic.isa"
-
-//Include the integerOp and integerOpCc format
-##include "m5/arch/sparc/isa/formats/integerop.isa"
-
-//Include the mem format
-##include "m5/arch/sparc/isa/formats/mem.isa"
-
-//Include the trap format
-##include "m5/arch/sparc/isa/formats/trap.isa"
-
-//Include the branch format
-##include "m5/arch/sparc/isa/formats/branch.isa"
-
-//Include the noop format
-##include "m5/arch/sparc/isa/formats/noop.isa"
-
diff --git a/arch/sparc/isa/formats/basic.isa b/arch/sparc/isa/formats/basic.isa
deleted file mode 100644
index 73df7617d..000000000
--- a/arch/sparc/isa/formats/basic.isa
+++ /dev/null
@@ -1,68 +0,0 @@
-
-// Declarations for execute() methods.
-def template BasicExecDeclare {{
-        Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
-}};
-
-// Basic instruction class declaration template.
-def template BasicDeclare {{
-        /**
-         * Static instruction class for "%(mnemonic)s".
-         */
-        class %(class_name)s : public %(base_class)s
-        {
-          public:
-            // Constructor.
-            %(class_name)s(MachInst machInst);
-            %(BasicExecDeclare)s
-        };
-}};
-
-// Basic instruction class constructor template.
-def template BasicConstructor {{
-        inline %(class_name)s::%(class_name)s(MachInst machInst)
-            : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
-        {
-                %(constructor)s;
-        }
-}};
-
-// Basic instruction class execute method template.
-def template BasicExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-        {
-            Fault fault = NoFault;
-
-            %(fp_enable_check)s;
-            %(op_decl)s;
-            %(op_rd)s;
-            %(code)s;
-
-            if(fault == NoFault)
-            {
-                %(op_wb)s;
-            }
-            return fault;
-        }
-}};
-
-// Basic decode template.
-def template BasicDecode {{
-        return new %(class_name)s(machInst);
-}};
-
-// Basic decode template, passing mnemonic in as string arg to constructor.
-def template BasicDecodeWithMnemonic {{
-        return new %(class_name)s("%(mnemonic)s", machInst);
-}};
-
-// The most basic instruction format... used only for a few misc. insts
-def format BasicOperate(code, *flags) {{
-        iop = InstObjParams(name, Name, 'SparcStaticInst',
-                CodeBlock(code), flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-        exec_output = BasicExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa
deleted file mode 100644
index 80101de1b..000000000
--- a/arch/sparc/isa/formats/branch.isa
+++ /dev/null
@@ -1,62 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Branch instructions
-//
-
-output header {{
-        /**
-         * Base class for integer operations.
-         */
-        class Branch : public SparcStaticInst
-        {
-          protected:
-            // Constructor
-            Branch(const char *mnem, MachInst _machInst, OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-}};
-
-output decoder {{
-        std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-        {
-                return "Branch instruction\n";
-        }
-}};
-
-def template BranchExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-        {
-            //Attempt to execute the instruction
-            Fault fault = NoFault;
-            checkPriv;
-
-            %(op_decl)s;
-            %(op_rd)s;
-            %(code)s;
-
-            if(fault == NoFault)
-            {
-                //Write the resulting state to the execution context
-                %(op_wb)s;
-            }
-
-            return fault;
-        }
-}};
-
-// Primary format for integer operate instructions:
-def format Branch(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = BranchExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
deleted file mode 100644
index 5a9e09896..000000000
--- a/arch/sparc/isa/formats/integerop.isa
+++ /dev/null
@@ -1,112 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Integer operate instructions
-//
-
-output header {{
-        /**
-         * Base class for integer operations.
-         */
-        class IntegerOp : public SparcStaticInst
-        {
-          protected:
-            // Constructor
-            IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-}};
-
-output decoder {{
-        std::string IntegerOp::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-                return "Integer instruction\n";
-        }
-}};
-
-def template IntegerExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
-        {
-                //These are set to constants when the execute method
-                //is generated
-                bool useCc = ;
-                bool checkPriv = ;
-
-                //Attempt to execute the instruction
-                try
-                {
-                        checkPriv;
-
-                        %(op_decl)s;
-                        %(op_rd)s;
-                        %(code)s;
-                }
-                //If we have an exception for some reason,
-                //deal with it
-                catch(SparcException except)
-                {
-                        //Deal with exception
-                        return No_Fault;
-                }
-
-                //Write the resulting state to the execution context
-                %(op_wb)s;
-                if(useCc)
-                {
-                        xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
-                        xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
-                        xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
-                        xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
-                        xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
-                        xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
-                        xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
-                        xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
-                }
-                return No_Fault;
-        }
-}};
-
-// Primary format for integer operate instructions:
-def format IntegerOp(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
-        for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
-                       ('xvValue', '0'), ('xcValue', '0')):
-                code.replace(marker, value)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = IntegerExecute.subst(iop)
-}};
-
-// Primary format for integer operate instructions:
-def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
-        for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
-                       ('xvValue', xvValue), ('xcValue', xcValue)):
-                code.replace(marker, value)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = IntegerExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
deleted file mode 100644
index d72de47d0..000000000
--- a/arch/sparc/isa/formats/mem.isa
+++ /dev/null
@@ -1,73 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Mem instructions
-//
-
-output header {{
-        /**
-         * Base class for integer operations.
-         */
-        class Mem : public SparcStaticInst
-        {
-          protected:
-
-            // Constructor
-            Mem(const char *mnem, MachInst _machInst, OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-}};
-
-output decoder {{
-        std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-        {
-            return "Memory instruction\n";
-        }
-}};
-
-def template MemExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-        {
-            Fault fault = NoFault;
-            %(op_decl)s;
-            %(op_rd)s;
-            ea_code
-            %(code)s;
-
-            if(fault == NoFault)
-            {
-                //Write the resulting state to the execution context
-                %(op_wb)s;
-            }
-
-            return fault;
-        }
-}};
-
-// Primary format for integer operate instructions:
-def format Mem(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = MemExecute.subst(iop)
-        exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
-}};
-
-def format Cas(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = MemExecute.subst(iop)
-        exec_output.replace('ea_code', 'EA = R1;');
-}};
diff --git a/arch/sparc/isa/formats/noop.isa b/arch/sparc/isa/formats/noop.isa
deleted file mode 100644
index fa4047f06..000000000
--- a/arch/sparc/isa/formats/noop.isa
+++ /dev/null
@@ -1,50 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Noop instruction
-//
-
-output header {{
-        /**
-         * Noop class.
-         */
-        class Noop : public SparcStaticInst
-        {
-          protected:
-            // Constructor
-            Noop(const char *mnem, MachInst _machInst, OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-}};
-
-output decoder {{
-        std::string Noop::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            return "Noop\n";
-        }
-}};
-
-def template NoopExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-        {
-            //Nothing to see here, move along
-            return NoFault;
-        }
-}};
-
-// Primary format for integer operate instructions:
-def format Noop(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = NoopExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa
deleted file mode 100644
index ff3aadf72..000000000
--- a/arch/sparc/isa/formats/trap.isa
+++ /dev/null
@@ -1,51 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Trap instructions
-//
-
-output header {{
-        /**
-         * Base class for integer operations.
-         */
-        class Trap : public SparcStaticInst
-        {
-          protected:
-
-            // Constructor
-            Trap(const char *mnem, MachInst _machInst, OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-}};
-
-output decoder {{
-        std::string Trap::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            return "Trap instruction\n";
-        }
-}};
-
-def template TrapExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-        {
-            //TODO: set up a software fault and return it.
-            return NoFault;
-        }
-}};
-
-// Primary format for integer operate instructions:
-def format Trap(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = TrapExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa/includes.isa b/arch/sparc/isa/includes.isa
deleted file mode 100644
index a99018b49..000000000
--- a/arch/sparc/isa/includes.isa
+++ /dev/null
@@ -1,43 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Output include file directives.
-//
-
-output header {{
-#include <sstream>
-#include <iostream>
-#include <iomanip>
-
-#include "cpu/static_inst.hh"
-#include "arch/sparc/faults.hh"
-#include "mem/mem_req.hh"  // some constructors use MemReq flags
-#include "arch/sparc/isa_traits.hh"
-}};
-
-output decoder {{
-#include "base/cprintf.hh"
-#include "base/loader/symtab.hh"
-#include "cpu/exec_context.hh"  // for Jump::branchTarget()
-
-#include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
-
-using namespace SparcISA;
-}};
-
-output exec {{
-#include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
-
-#ifdef FULL_SYSTEM
-//#include "arch/alpha/pseudo_inst.hh"
-#endif
-#include "cpu/base.hh"
-#include "cpu/exetrace.hh"
-#include "sim/sim_exit.hh"
-}};
-
diff --git a/arch/sparc/isa/main.isa b/arch/sparc/isa/main.isa
deleted file mode 100644
index ab0290d58..000000000
--- a/arch/sparc/isa/main.isa
+++ /dev/null
@@ -1,52 +0,0 @@
-// -*- mode:c++ -*-
-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-##include "m5/arch/sparc/isa/includes.isa"
-
-////////////////////////////////////////////////////////////////////
-//
-// Namespace statement.  Everything below this line will be in the
-// SparcISAInst namespace.
-//
-
-namespace SparcISA;
-
-//Include the bitfield definitions
-##include "m5/arch/sparc/isa/bitfields.isa"
-
-//Include the operand_types and operand definitions
-##include "m5/arch/sparc/isa/operands.isa"
-
-//Include the base class for sparc instructions, and some support code
-##include "m5/arch/sparc/isa/base.isa"
-
-//Include the definitions for the instruction formats
-##include "m5/arch/sparc/isa/formats.isa"
-
-//Include the decoder definition
-##include "m5/arch/sparc/isa/decoder.isa"
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa
deleted file mode 100644
index 64f5abd08..000000000
--- a/arch/sparc/isa/operands.isa
+++ /dev/null
@@ -1,31 +0,0 @@
-def operand_types {{
-    'sb' : ('signed int', 8),
-    'ub' : ('unsigned int', 8),
-    'shw' : ('signed int', 16),
-    'uhw' : ('unsigned int', 16),
-    'sw' : ('signed int', 32),
-    'uw' : ('unsigned int', 32),
-    'sdw' : ('signed int', 64),
-    'udw' : ('unsigned int', 64),
-    'sf' : ('float', 32),
-    'df' : ('float', 64),
-    'qf' : ('float', 128)
-}};
-
-def operands {{
-    # Int regs default to unsigned, but code should not count on this.
-    # For clarity, descriptions that depend on unsigned behavior should
-    # explicitly specify '.uq'.
-    'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
-    'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2),
-    'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3),
-    #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
-    #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
-    #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
-    'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
-    #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
-    #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
-    #'FPCR':  ('ControlReg', 'uq', 'Fpcr', None, 1),
-    'R0':  ('IntReg', 'udw', '0', None, 1),
-    'R16': ('IntReg', 'udw', '16', None, 1)
-}};
diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
deleted file mode 100644
index bd3c35beb..000000000
--- a/arch/sparc/isa_traits.hh
+++ /dev/null
@@ -1,527 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
-#define __ARCH_SPARC_ISA_TRAITS_HH__
-
-#include "arch/sparc/faults.hh"
-#include "base/misc.hh"
-#include "config/full_system.hh"
-#include "sim/host.hh"
-
-//This makes sure the big endian versions of certain functions are used.
-namespace BigEndianGuest {}
-using namespace BigEndianGuest;
-
-class ExecContext;
-class FastCPU;
-//class FullCPU;
-class Checkpoint;
-
-#define TARGET_SPARC
-
-class StaticInst;
-class StaticInstPtr;
-
-//namespace EV5
-//{
-//	int DTB_ASN_ASN(uint64_t reg);
-//	int ITB_ASN_ASN(uint64_t reg);
-//}
-
-namespace SparcISA
-{
-    typedef uint32_t MachInst;
-    typedef uint64_t ExtMachInst;
-    typedef uint8_t  RegIndex;
-
-    const int NumFloatRegs = 32;
-    const int NumMiscRegs = 32;
-
-    const int // Maximum trap level
-    const int MaxTL = 4;
-    const int
-    const int // semantically meaningful register indices
-    const int ZeroReg = 0;	// architecturally meaningful
-    const int // the rest of these depend on the ABI
-    const int StackPointerReg = 14;
-    const int ReturnAddressReg = 31; // post call, precall is 15
-    const int ReturnValueReg = 8; // Post return, 24 is pre-return.
-    const int FramePointerReg = 30;
-    const int ArgumentReg0 = 8;
-    const int ArgumentReg1 = 9;
-    const int ArgumentReg2 = 10;
-    const int ArgumentReg3 = 11;
-    const int ArgumentReg4 = 12;
-    const int ArgumentReg5 = 13;
-    // Some OS syscall sue a second register (o1) to return a second value
-    const int SyscallPseudoReturnReg = ArgumentReg1;
-
-
-    //8K. This value is implmentation specific; and should probably
-    //be somewhere else.
-    const int LogVMPageSize = 13;
-    const int VMPageSize = (1 << LogVMPageSize);
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-    typedef uint64_t IntReg;
-
-    class IntRegFile
-    {
-        private:
-          //For right now, let's pretend the register file is static
-          IntReg regs[32];
-        public:
-          IntReg & operator [] (RegIndex index)
-          {
-              //Don't allow indexes outside of the 32 registers
-              index &= 0x1F;
-              return regs[index];
-          }
-    };
-
-    void serialize(std::ostream & os);
-
-    void unserialize(Checkpoint *cp, const std::string &section);
-
-    typedef float float32_t;
-    typedef double float64_t;
-    //FIXME This actually usually refers to a 10 byte float, rather than a
-    //16 byte float as required. This data type may have to be emulated.
-    typedef long double float128_t;
-
-    class FloatRegFile
-    {
-      private:
-        //By using the largest data type, we ensure everything
-        //is aligned correctly in memory
-        union
-        {
-            float128_t rawRegs[16];
-            uint64_t regDump[32];
-        };
-        class QuadRegs
-        {
-          private:
-            FloatRegFile * parent;
-          public:
-            QuadRegs(FloatRegFile * p) : parent(p) {;}
-            float128_t & operator [] (RegIndex index)
-            {
-                //Quad floats are index by the single
-                //precision register the start on,
-                //and only 16 should be accessed
-                index = (index >> 2) & 0xF;
-                return parent->rawRegs[index];
-            }
-        };
-        class DoubleRegs
-        {
-          private:
-            FloatRegFile * parent;
-          public:
-            DoubleRegs(FloatRegFile * p) : parent(p) {;}
-            float64_t & operator [] (RegIndex index)
-            {
-                //Double floats are index by the single
-                //precision register the start on,
-                //and only 32 should be accessed
-                index = (index >> 1) & 0x1F;
-                return ((float64_t *)parent->rawRegs)[index];
-            }
-        };
-        class SingleRegs
-        {
-          private:
-            FloatRegFile * parent;
-          public:
-            SingleRegs(FloatRegFile * p) : parent(p) {;}
-            float32_t & operator [] (RegIndex index)
-            {
-                //Only 32 single floats should be accessed
-                index &= 0x1F;
-                return ((float32_t *)parent->rawRegs)[index];
-            }
-        };
-      public:
-        void serialize(std::ostream & os);
-
-        void unserialize(Checkpoint * cp, std::string & section);
-
-        QuadRegs quadRegs;
-        DoubleRegs doubleRegs;
-        SingleRegs singleRegs;
-        FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this)
-        {;}
-    };
-
-    // control register file contents
-    typedef uint64_t MiscReg;
-    // The control registers, broken out into fields
-    class MiscRegFile
-    {
-      private:
-        union
-        {
-            uint16_t pstate;		// Process State Register
-            struct
-            {
-                uint16_t ag:1;		// Alternate Globals
-                uint16_t ie:1;		// Interrupt enable
-                uint16_t priv:1;	// Privelege mode
-                uint16_t am:1;		// Address mask
-                uint16_t pef:1;		// PSTATE enable floating-point
-                uint16_t red:1;		// RED (reset, error, debug) state
-                uint16_t mm:2;		// Memory Model
-                uint16_t tle:1;		// Trap little-endian
-                uint16_t cle:1;		// Current little-endian
-            } pstateFields;
-        };
-        uint64_t tba;		// Trap Base Address
-        union
-        {
-            uint64_t y;		// Y (used in obsolete multiplication)
-            struct
-            {
-                uint64_t value:32;	// The actual value stored in y
-                uint64_t :32;	// reserved bits
-            } yFields;
-        };
-        uint8_t pil;		// Process Interrupt Register
-        uint8_t cwp;		// Current Window Pointer
-        uint16_t tt[MaxTL];	// Trap Type (Type of trap which occured
-                                // on the previous level)
-        union
-        {
-            uint8_t	ccr;		// Condition Code Register
-            struct
-            {
-                union
-                {
-                    uint8_t icc:4;	// 32-bit condition codes
-                    struct
-                    {
-                        uint8_t c:1;	// Carry
-                        uint8_t v:1;	// Overflow
-                        uint8_t z:1;	// Zero
-                        uint8_t n:1;	// Negative
-                    } iccFields;
-                };
-                union
-                {
-                    uint8_t xcc:4;	// 64-bit condition codes
-                    struct
-                    {
-                        uint8_t c:1;	// Carry
-                        uint8_t v:1;	// Overflow
-                        uint8_t z:1;	// Zero
-                        uint8_t n:1;	// Negative
-                    } xccFields;
-                };
-            } ccrFields;
-        };
-        uint8_t asi;		// Address Space Identifier
-        uint8_t tl;		// Trap Level
-        uint64_t tpc[MaxTL];	// Trap Program Counter (value from
-                                // previous trap level)
-        uint64_t tnpc[MaxTL];	// Trap Next Program Counter (value from
-                                // previous trap level)
-        union
-        {
-            uint64_t tstate[MaxTL];	// Trap State
-            struct
-            {
-                //Values are from previous trap level
-                uint64_t cwp:5;		// Current Window Pointer
-                uint64_t :2;	// Reserved bits
-                uint64_t pstate:10;	// Process State
-                uint64_t :6;	// Reserved bits
-                uint64_t asi:8;		// Address Space Identifier
-                uint64_t ccr:8;		// Condition Code Register
-            } tstateFields[MaxTL];
-        };
-        union
-        {
-            uint64_t tick;		// Hardware clock-tick counter
-            struct
-            {
-                uint64_t counter:63;	// Clock-tick count
-                uint64_t npt:1;		// Non-priveleged trap
-            } tickFields;
-        };
-        uint8_t cansave;	// Savable windows
-        uint8_t canrestore;	// Restorable windows
-        uint8_t otherwin;	// Other windows
-        uint8_t cleanwin;	// Clean windows
-        union
-        {
-            uint8_t wstate;		// Window State
-            struct
-            {
-                uint8_t normal:3;	// Bits TT<4:2> are set to on a normal
-                                        // register window trap
-                uint8_t other:3;	// Bits TT<4:2> are set to on an "otherwin"
-                                        // register window trap
-            } wstateFields;
-        };
-        union
-        {
-            uint64_t ver;		// Version
-            struct
-            {
-                uint64_t maxwin:5;	// Max CWP value
-                uint64_t :2;	// Reserved bits
-                uint64_t maxtl:8;	// Maximum trap level
-                uint64_t :8;	// Reserved bits
-                uint64_t mask:8;	// Processor mask set revision number
-                uint64_t impl:16;	// Implementation identification number
-                uint64_t manuf:16;	// Manufacturer code
-            } verFields;
-        };
-        union
-        {
-            uint64_t	fsr;	// Floating-Point State Register
-            struct
-            {
-                union
-                {
-                    uint64_t cexc:5;	// Current excpetion
-                    struct
-                    {
-                        uint64_t nxc:1;		// Inexact
-                        uint64_t dzc:1;		// Divide by zero
-                        uint64_t ufc:1;		// Underflow
-                        uint64_t ofc:1;		// Overflow
-                        uint64_t nvc:1;		// Invalid operand
-                    } cexecFields;
-                };
-                union
-                {
-                    uint64_t aexc:5;		// Accrued exception
-                    struct
-                    {
-                        uint64_t nxc:1;		// Inexact
-                        uint64_t dzc:1;		// Divide by zero
-                        uint64_t ufc:1;		// Underflow
-                        uint64_t ofc:1;		// Overflow
-                        uint64_t nvc:1;		// Invalid operand
-                    } aexecFields;
-                };
-                uint64_t fcc0:2;		// Floating-Point condtion codes
-                uint64_t :1;		// Reserved bits
-                uint64_t qne:1;			// Deferred trap queue not empty
-                                                // with no queue, it should read 0
-                uint64_t ftt:3;			// Floating-Point trap type
-                uint64_t ver:3;			// Version (of the FPU)
-                uint64_t :2;		// Reserved bits
-                uint64_t ns:1;			// Nonstandard floating point
-                union
-                {
-                    uint64_t tem:5;			// Trap Enable Mask
-                    struct
-                    {
-                        uint64_t nxm:1;		// Inexact
-                        uint64_t dzm:1;		// Divide by zero
-                        uint64_t ufm:1;		// Underflow
-                        uint64_t ofm:1;		// Overflow
-                        uint64_t nvm:1;		// Invalid operand
-                    } temFields;
-                };
-                uint64_t :2;		// Reserved bits
-                uint64_t rd:2;			// Rounding direction
-                uint64_t fcc1:2;		// Floating-Point condition codes
-                uint64_t fcc2:2;		// Floating-Point condition codes
-                uint64_t fcc3:2;		// Floating-Point condition codes
-                uint64_t :26;		// Reserved bits
-            } fsrFields;
-        };
-        union
-        {
-            uint8_t		fprs;	// Floating-Point Register State
-            struct
-            {
-                uint8_t dl:1;		// Dirty lower
-                uint8_t du:1;		// Dirty upper
-                uint8_t fef:1;		// FPRS enable floating-Point
-            } fprsFields;
-        };
-
-      public:
-        MiscReg readReg(int misc_reg);
-
-        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
-
-        Fault setReg(int misc_reg, const MiscReg &val);
-
-        Fault setRegWithEffect(int misc_reg, const MiscReg &val,
-                               ExecContext *xc);
-
-        void serialize(std::ostream & os);
-
-        void unserialize(Checkpoint * cp, std::string & section);
-    };
-
-    typedef union
-    {
-        float32_t singReg;
-        float64_t doubReg;
-        float128_t quadReg;
-    } FloatReg;
-
-    typedef union
-    {
-        IntReg  intreg;
-        FloatReg   fpreg;
-        MiscReg ctrlreg;
-    } AnyReg;
-
-    struct RegFile
-    {
-        IntRegFile intRegFile;		// (signed) integer register file
-        FloatRegFile floatRegFile;	// floating point register file
-        MiscRegFile miscRegFile;	// control register file
-
-        Addr pc;		// Program Counter
-        Addr npc;		// Next Program Counter
-        Addr nnpc;
-
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
-    };
-
-    StaticInstPtr decodeInst(MachInst);
-
-    // return a no-op instruction... used for instruction fetch faults
-    extern const MachInst NoopMachInst;
-
-    // Instruction address compression hooks
-    inline Addr realPCToFetchPC(const Addr &addr)
-    {
-        return addr;
-    }
-
-    inline Addr fetchPCToRealPC(const Addr &addr)
-    {
-        return addr;
-    }
-
-    // the size of "fetched" instructions (not necessarily the size
-    // of real instructions for PISA)
-    inline size_t fetchInstSize()
-    {
-        return sizeof(MachInst);
-    }
-
-    /**
-     * Function to insure ISA semantics about 0 registers.
-     * @param xc The execution context.
-     */
-    template <class XC>
-
-    static inline setSyscallReturn(SyscallReturn return_value, RegFile *regs)
-    {
-        // check for error condition.  SPARC syscall convention is to
-        // indicate success/failure in reg the carry bit of the ccr
-        // and put the return value itself in the standard return value reg ().
-        if (return_value.successful()) {
-            // no error
-            regs->miscRegFile.ccrFields.iccFields.c = 0;
-            regs->intRegFile[ReturnValueReg] = return_value.value();
-        } else {
-            // got an error, return details
-            regs->miscRegFile.ccrFields.iccFields.c = 1;
-            regs->intRegFile[ReturnValueReg] = -return_value.value();
-        }
-    }
-};
-
-#if !FULL_SYSTEM
-class SyscallReturn
-{
-  public:
-    template <class T>
-    SyscallReturn(T v, bool s)
-    {
-        retval = (uint64_t)v;
-        success = s;
-    }
-
-    template <class T>
-    SyscallReturn(T v)
-    {
-        success = (v >= 0);
-        retval = (uint64_t)v;
-    }
-
-    ~SyscallReturn() {}
-
-    SyscallReturn& operator=(const SyscallReturn& s)
-    {
-        retval = s.retval;
-        success = s.success;
-        return *this;
-    }
-
-    bool successful() { return success; }
-    uint64_t value() { return retval; }
-
-    private:
-    uint64_t retval;
-    bool success;
-};
-
-#endif
-
-
-#if FULL_SYSTEM
-
-#include "arch/alpha/ev5.hh"
-#endif
-
-#endif // __ARCH_SPARC_ISA_TRAITS_HH__
diff --git a/arch/sparc/linux/process.cc b/arch/sparc/linux/process.cc
deleted file mode 100644
index fa2a7b9f5..000000000
--- a/arch/sparc/linux/process.cc
+++ /dev/null
@@ -1,374 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/sparc/common_syscall_emul.hh"
-#include "arch/sparc/linux/process.hh"
-#include "arch/sparc/isa_traits.hh"
-
-#include "base/trace.hh"
-#include "cpu/exec_context.hh"
-#include "kern/linux/linux.hh"
-#include "mem/functional/functional.hh"
-
-#include "sim/process.hh"
-#include "sim/syscall_emul.hh"
-
-using namespace std;
-using namespace SparcISA;
-
-
-/// Target uname() handler.
-static SyscallReturn
-unameFunc(SyscallDesc *desc, int callnum, Process *process,
-          ExecContext *xc)
-{
-    TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
-
-    strcpy(name->sysname, "Linux");
-    strcpy(name->nodename, "m5.eecs.umich.edu");
-    strcpy(name->release, "2.4.20");
-    strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
-    strcpy(name->machine, "sparc");
-
-    name.copyOut(xc->mem);
-    return 0;
-}
-
-SyscallDesc SparcLinuxProcess::syscallDescs[] = {
-    /*  0 */ SyscallDesc("restart_syscall", unimplementedFunc);
-    /*  1 */ SyscallDesc("exit", exitFunc);
-    /*  2 */ SyscallDesc("fork", unimplementedFunc);
-    /*  3 */ SyscallDesc("read", readFunc);
-    /*  4 */ SyscallDesc("write", writeFunc);
-    /*  5 */ SyscallDesc("open", openFunc<Linux>);
-    /*  6 */ SyscallDesc("close", closeFinc);
-    /*  7 */ SyscallDesc("wait4", unimplementedFunc);
-    /*  8 */ SyscallDesc("creat", unimplementedFunc);
-    /*  9 */ SyscallDesc("link", unimplementedFunc);
-    /* 10 */ SyscallDesc("unlink", unlinkFunc);
-    /* 11 */ SyscallDesc("execv", unimplementedFunc);
-    /* 12 */ SyscallDesc("chdir", unimplementedFunc);
-    /* 13 */ SyscallDesc("chown", chownFunc);
-    /* 14 */ SyscallDesc("mknod", unimplementedFunc);
-    /* 15 */ SyscallDesc("chmod", chmodFunc<Linux>);
-    /* 16 */ SyscallDesc("lchown", unimplementedFunc);
-    /* 17 */ SyscallDesc("brk", obreakFunc);
-    /* 18 */ SyscallDesc("perfctr", unimplementedFunc);
-    /* 19 */ SyscallDesc("lseek", lseekFunc);
-    /* 20 */ SyscallDesc("getpid", getpidFunc);
-    /* 21 */ SyscallDesc("capget", unimplementedFunc);
-    /* 22 */ SyscallDesc("capset", unimplementedFunc);
-    /* 23 */ SyscallDesc("setuid", setuidFunc);
-    /* 24 */ SyscallDesc("getuid", getuidFunc);
-    /* 25 */ SyscallDesc("time", unimplementedFunc);
-    /* 26 */ SyscallDesc("ptrace", unimplementedFunc);
-    /* 27 */ SyscallDesc("alarm", unimplementedFunc);
-    /* 28 */ SyscallDesc("sigaltstack", unimplementedFunc);
-    /* 29 */ SyscallDesc("pause", unimplementedFunc);
-    /* 30 */ SyscallDesc("utime", unimplementedFunc);
-    /* 31 */ SyscallDesc("lchown32", unimplementedFunc);
-    /* 32 */ SyscallDesc("fchown32", unimplementedFunc);
-    /* 33 */ SyscallDesc("access", unimplementedFunc);
-    /* 34 */ SyscallDesc("nice", unimplementedFunc);
-    /* 35 */ SyscallDesc("chown32", unimplementedFunc);
-    /* 36 */ SyscallDesc("sync", unimplementedFunc);
-    /* 37 */ SyscallDesc("kill", unimplementedFunc);
-    /* 38 */ SyscallDesc("stat", unimplementedFunc);
-    /* 39 */ SyscallDesc("sendfile", unimplementedFunc);
-    /* 40 */ SyscallDesc("lstat", unimplementedFunc);
-    /* 41 */ SyscallDesc("dup", unimplementedFunc);
-    /* 42 */ SyscallDesc("pipe", pipePseudoFunc);
-    /* 43 */ SyscallDesc("times", unimplementedFunc);
-    /* 44 */ SyscallDesc("getuid32", unimplementedFunc);
-    /* 45 */ SyscallDesc("umount2", unimplementedFunc);
-    /* 46 */ SyscallDesc("setgid", unimplementedFunc);
-    /* 47 */ SyscallDesc("getgid", getgidFunc);
-    /* 48 */ SyscallDesc("signal", unimplementedFunc);
-    /* 49 */ SyscallDesc("geteuid", geteuidFunc);
-    /* 50 */ SyscallDesc("getegid", getegidFunc);
-    /* 51 */ SyscallDesc("acct", unimplementedFunc);
-    /* 52 */ SyscallDesc("memory_ordering", unimplementedFunc);
-    /* 53 */ SyscallDesc("getgid32", unimplementedFunc);
-    /* 54 */ SyscallDesc("ioctl", unimplementedFunc);
-    /* 55 */ SyscallDesc("reboot", unimplementedFunc);
-    /* 56 */ SyscallDesc("mmap2", unimplementedFunc);
-    /* 57 */ SyscallDesc("symlink", unimplementedFunc);
-    /* 58 */ SyscallDesc("readlink", unimplementedFunc);
-    /* 59 */ SyscallDesc("execve", unimplementedFunc);
-    /* 60 */ SyscallDesc("umask", unimplementedFunc);
-    /* 61 */ SyscallDesc("chroot", unimplementedFunc);
-    /* 62 */ SyscallDesc("fstat", unimplementedFunc);
-    /* 63 */ SyscallDesc("fstat64", unimplementedFunc);
-    /* 64 */ SyscallDesc("getpagesize", unimplementedFunc);
-    /* 65 */ SyscallDesc("msync", unimplementedFunc);
-    /* 66 */ SyscallDesc("vfork", unimplementedFunc);
-    /* 67 */ SyscallDesc("pread64", unimplementedFunc);
-    /* 68 */ SyscallDesc("pwrite64", unimplementedFunc);
-    /* 69 */ SyscallDesc("geteuid32", unimplementedFunc);
-    /* 70 */ SyscallDesc("getdgid32", unimplementedFunc);
-    /* 71 */ SyscallDesc("mmap", unimplementedFunc);
-    /* 72 */ SyscallDesc("setreuid32", unimplementedFunc);
-    /* 73 */ SyscallDesc("munmap", unimplementedFunc);
-    /* 74 */ SyscallDesc("mprotect", unimplementedFunc);
-    /* 75 */ SyscallDesc("madvise", unimplementedFunc);
-    /* 76 */ SyscallDesc("vhangup", unimplementedFunc);
-    /* 77 */ SyscallDesc("truncate64", unimplementedFunc);
-    /* 78 */ SyscallDesc("mincore", unimplementedFunc);
-    /* 79 */ SyscallDesc("getgroups", unimplementedFunc);
-    /* 80 */ SyscallDesc("setgroups", unimplementedFunc);
-    /* 81 */ SyscallDesc("getpgrp", unimplementedFunc);
-    /* 82 */ SyscallDesc("setgroups32", unimplementedFunc);
-    /* 83 */ SyscallDesc("setitimer", unimplementedFunc);
-    /* 84 */ SyscallDesc("ftruncate64", unimplementedFunc);
-    /* 85 */ SyscallDesc("swapon", unimplementedFunc);
-    /* 86 */ SyscallDesc("getitimer", unimplementedFunc);
-    /* 87 */ SyscallDesc("setuid32", unimplementedFunc);
-    /* 88 */ SyscallDesc("sethostname", unimplementedFunc);
-    /* 89 */ SyscallDesc("setgid32", unimplementedFunc);
-    /* 90 */ SyscallDesc("dup2", unimplementedFunc);
-    /* 91 */ SyscallDesc("setfsuid32", unimplementedFunc);
-    /* 92 */ SyscallDesc("fcntl", unimplementedFunc);
-    /* 93 */ SyscallDesc("select", unimplementedFunc);
-    /* 94 */ SyscallDesc("setfsgid32", unimplementedFunc);
-    /* 95 */ SyscallDesc("fsync", unimplementedFunc);
-    /* 96 */ SyscallDesc("setpriority", unimplementedFunc);
-    /* 97 */ SyscallDesc("socket", unimplementedFunc);
-    /* 98 */ SyscallDesc("connect", unimplementedFunc);
-    /* 99 */ SyscallDesc("accept", unimplementedFunc);
-    /* 100 */ SyscallDesc("getpriority", unimplementedFunc);
-    /* 101 */ SyscallDesc("rt_sigreturn", unimplementedFunc);
-    /* 102 */ SyscallDesc("rt_sigaction", unimplementedFunc);
-    /* 103 */ SyscallDesc("rt_sigprocmask", unimplementedFunc);
-    /* 104 */ SyscallDesc("rt_sigpending", unimplementedFunc);
-    /* 105 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc);
-    /* 106 */ SyscallDesc("rt_sigqueueinfo", unimplementedFunc);
-    /* 107 */ SyscallDesc("rt_sigsuspend", unimplementedFunc);
-    /* 108 */ SyscallDesc("setresuid", unimplementedFunc);
-    /* 109 */ SyscallDesc("getresuid", unimplementedFunc);
-    /* 110 */ SyscallDesc("setresgid", unimplementedFunc);
-    /* 111 */ SyscallDesc("getresgid", unimplementedFunc);
-    /* 112 */ SyscallDesc("setregid32", unimplementedFunc);
-    /* 113 */ SyscallDesc("recvmsg", unimplementedFunc);
-    /* 114 */ SyscallDesc("sendmsg", unimplementedFunc);
-    /* 115 */ SyscallDesc("getgroups32", unimplementedFunc);
-    /* 116 */ SyscallDesc("gettimeofday", unimplementedFunc);
-    /* 117 */ SyscallDesc("getrusage", unimplementedFunc);
-    /* 118 */ SyscallDesc("getsockopt", unimplementedFunc);
-    /* 119 */ SyscallDesc("getcwd", unimplementedFunc);
-    /* 120 */ SyscallDesc("readv", unimplementedFunc);
-    /* 121 */ SyscallDesc("writev", unimplementedFunc);
-    /* 122 */ SyscallDesc("settimeofday", unimplementedFunc);
-    /* 123 */ SyscallDesc("fchown", unimplementedFunc);
-    /* 124 */ SyscallDesc("fchmod", unimplementedFunc);
-    /* 125 */ SyscallDesc("recvfrom", unimplementedFunc);
-    /* 126 */ SyscallDesc("setreuid", unimplementedFunc);
-    /* 127 */ SyscallDesc("setregid", unimplementedFunc);
-    /* 128 */ SyscallDesc("rename", unimplementedFunc);
-    /* 129 */ SyscallDesc("truncate", unimplementedFunc);
-    /* 130 */ SyscallDesc("ftruncate", unimplementedFunc);
-    /* 131 */ SyscallDesc("flock", unimplementedFunc);
-    /* 132 */ SyscallDesc("lstat64", unimplementedFunc);
-    /* 133 */ SyscallDesc("sendto", unimplementedFunc);
-    /* 134 */ SyscallDesc("shutdown", unimplementedFunc);
-    /* 135 */ SyscallDesc("socketpair", unimplementedFunc);
-    /* 136 */ SyscallDesc("mkdir", unimplementedFunc);
-    /* 137 */ SyscallDesc("rmdir", unimplementedFunc);
-    /* 138 */ SyscallDesc("utimes", unimplementedFunc);
-    /* 139 */ SyscallDesc("stat64", unimplementedFunc);
-    /* 140 */ SyscallDesc("sendfile64", unimplementedFunc);
-    /* 141 */ SyscallDesc("getpeername", unimplementedFunc);
-    /* 142 */ SyscallDesc("futex", unimplementedFunc);
-    /* 143 */ SyscallDesc("gettid", unimplementedFunc);
-    /* 144 */ SyscallDesc("getrlimit", unimplementedFunc);
-    /* 145 */ SyscallDesc("setrlimit", unimplementedFunc);
-    /* 146 */ SyscallDesc("pivot_root", unimplementedFunc);
-    /* 147 */ SyscallDesc("prctl", unimplementedFunc);
-    /* 148 */ SyscallDesc("pciconfig_read", unimplementedFunc);
-    /* 149 */ SyscallDesc("pciconfig_write", unimplementedFunc);
-    /* 150 */ SyscallDesc("getsockname", unimplementedFunc);
-    /* 151 */ SyscallDesc("inotify_init", unimplementedFunc);
-    /* 152 */ SyscallDesc("inotify_add_watch", unimplementedFunc);
-    /* 153 */ SyscallDesc("poll", unimplementedFunc);
-    /* 154 */ SyscallDesc("getdents64", unimplementedFunc);
-    /* 155 */ SyscallDesc("fcntl64", unimplementedFunc);
-    /* 156 */ SyscallDesc("inotify_rm_watch", unimplementedFunc);
-    /* 157 */ SyscallDesc("statfs", unimplementedFunc);
-    /* 158 */ SyscallDesc("fstatfs", unimplementedFunc);
-    /* 159 */ SyscallDesc("umount", unimplementedFunc);
-    /* 160 */ SyscallDesc("sched_set_affinity", unimplementedFunc);
-    /* 161 */ SyscallDesc("sched_get_affinity", unimplementedFunc);
-    /* 162 */ SyscallDesc("getdomainname", unimplementedFunc);
-    /* 163 */ SyscallDesc("setdomainname", unimplementedFunc);
-    /* 164 */ SyscallDesc("utrap_install", unimplementedFunc);
-    /* 165 */ SyscallDesc("quotactl", unimplementedFunc);
-    /* 166 */ SyscallDesc("set_tid_address", unimplementedFunc);
-    /* 167 */ SyscallDesc("mount", unimplementedFunc);
-    /* 168 */ SyscallDesc("ustat", unimplementedFunc);
-    /* 169 */ SyscallDesc("setxattr", unimplementedFunc);
-    /* 170 */ SyscallDesc("lsetxattr", unimplementedFunc);
-    /* 171 */ SyscallDesc("fsetxattr", unimplementedFunc);
-    /* 172 */ SyscallDesc("getxattr", unimplementedFunc);
-    /* 173 */ SyscallDesc("lgetxattr", unimplementedFunc);
-    /* 174 */ SyscallDesc("getdents", unimplementedFunc);
-    /* 175 */ SyscallDesc("setsid", unimplementedFunc);
-    /* 176 */ SyscallDesc("fchdir", unimplementedFunc);
-    /* 177 */ SyscallDesc("fgetxattr", unimplementedFunc);
-    /* 178 */ SyscallDesc("listxattr", unimplementedFunc);
-    /* 179 */ SyscallDesc("llistxattr", unimplementedFunc);
-    /* 180 */ SyscallDesc("flistxattr", unimplementedFunc);
-    /* 181 */ SyscallDesc("removexattr", unimplementedFunc);
-    /* 182 */ SyscallDesc("lremovexattr", unimplementedFunc);
-    /* 183 */ SyscallDesc("sigpending", unimplementedFunc);
-    /* 184 */ SyscallDesc("query_module", unimplementedFunc);
-    /* 185 */ SyscallDesc("setpgid", unimplementedFunc);
-    /* 186 */ SyscallDesc("fremovexattr", unimplementedFunc);
-    /* 187 */ SyscallDesc("tkill", unimplementedFunc);
-    /* 188 */ SyscallDesc("exit_group", unimplementedFunc);
-    /* 189 */ SyscallDesc("uname", unameFunc);
-    /* 190 */ SyscallDesc("init_module", unimplementedFunc);
-    /* 191 */ SyscallDesc("personality", unimplementedFunc);
-    /* 192 */ SyscallDesc("remap_file_pages", unimplementedFunc);
-    /* 193 */ SyscallDesc("epoll_create", unimplementedFunc);
-    /* 194 */ SyscallDesc("epoll_ctl", unimplementedFunc);
-    /* 195 */ SyscallDesc("epoll_wait", unimplementedFunc);
-    /* 196 */ SyscallDesc("ioprio_set", unimplementedFunc);
-    /* 197 */ SyscallDesc("getppid", getppidFunc);
-    /* 198 */ SyscallDesc("sigaction", unimplementedFunc);
-    /* 199 */ SyscallDesc("sgetmask", unimplementedFunc);
-    /* 200 */ SyscallDesc("ssetmask", unimplementedFunc);
-    /* 201 */ SyscallDesc("sigsuspend", unimplementedFunc);
-    /* 202 */ SyscallDesc("oldlstat", unimplementedFunc);
-    /* 203 */ SyscallDesc("uselib", unimplementedFunc);
-    /* 204 */ SyscallDesc("readdir", unimplementedFunc);
-    /* 205 */ SyscallDesc("readahead", unimplementedFunc);
-    /* 206 */ SyscallDesc("socketcall", unimplementedFunc);
-    /* 207 */ SyscallDesc("syslog", unimplementedFunc);
-    /* 208 */ SyscallDesc("lookup_dcookie", unimplementedFunc);
-    /* 209 */ SyscallDesc("fadvise64", unimplementedFunc);
-    /* 210 */ SyscallDesc("fadvise64_64", unimplementedFunc);
-    /* 211 */ SyscallDesc("tgkill", unimplementedFunc);
-    /* 212 */ SyscallDesc("waitpid", unimplementedFunc);
-    /* 213 */ SyscallDesc("swapoff", unimplementedFunc);
-    /* 214 */ SyscallDesc("sysinfo", unimplementedFunc);
-    /* 215 */ SyscallDesc("ipc", unimplementedFunc);
-    /* 216 */ SyscallDesc("sigreturn", unimplementedFunc);
-    /* 217 */ SyscallDesc("clone", unimplementedFunc);
-    /* 218 */ SyscallDesc("ioprio_get", unimplementedFunc);
-    /* 219 */ SyscallDesc("adjtimex", unimplementedFunc);
-    /* 220 */ SyscallDesc("sigprocmask", unimplementedFunc);
-    /* 221 */ SyscallDesc("create_module", unimplementedFunc);
-    /* 222 */ SyscallDesc("delete_module", unimplementedFunc);
-    /* 223 */ SyscallDesc("get_kernel_syms", unimplementedFunc);
-    /* 224 */ SyscallDesc("getpgid", unimplementedFunc);
-    /* 225 */ SyscallDesc("bdflush", unimplementedFunc);
-    /* 226 */ SyscallDesc("sysfs", unimplementedFunc);
-    /* 227 */ SyscallDesc("afs_syscall", unimplementedFunc);
-    /* 228 */ SyscallDesc("setfsuid", unimplementedFunc);
-    /* 229 */ SyscallDesc("setfsgid", unimplementedFunc);
-    /* 230 */ SyscallDesc("_newselect", unimplementedFunc);
-    /* 231 */ SyscallDesc("time", unimplementedFunc);
-    /* 232 */ SyscallDesc("oldstat", unimplementedFunc);
-    /* 233 */ SyscallDesc("stime", unimplementedFunc);
-    /* 234 */ SyscallDesc("statfs64", unimplementedFunc);
-    /* 235 */ SyscallDesc("fstatfs64", unimplementedFunc);
-    /* 236 */ SyscallDesc("_llseek", unimplementedFunc);
-    /* 237 */ SyscallDesc("mlock", unimplementedFunc);
-    /* 238 */ SyscallDesc("munlock", unimplementedFunc);
-    /* 239 */ SyscallDesc("mlockall", unimplementedFunc);
-    /* 240 */ SyscallDesc("munlockall", unimplementedFunc);
-    /* 241 */ SyscallDesc("sched_setparam", unimplementedFunc);
-    /* 242 */ SyscallDesc("sched_getparam", unimplementedFunc);
-    /* 243 */ SyscallDesc("sched_setscheduler", unimplementedFunc);
-    /* 244 */ SyscallDesc("sched_getscheduler", unimplementedFunc);
-    /* 245 */ SyscallDesc("sched_yield", unimplementedFunc);
-    /* 246 */ SyscallDesc("sched_get_priority_max", unimplimented);
-    /* 247 */ SyscallDesc("sched_get_priority_min", unimplimented);
-    /* 248 */ SyscallDesc("sched_rr_get_interval", unimplimented);
-    /* 249 */ SyscallDesc("nanosleep", unimplementedFunc);
-    /* 250 */ SyscallDesc("mremap", unimplementedFunc);
-    /* 251 */ SyscallDesc("_sysctl", unimplementedFunc);
-    /* 252 */ SyscallDesc("getsid", unimplementedFunc);
-    /* 253 */ SyscallDesc("fdatasync", unimplementedFunc);
-    /* 254 */ SyscallDesc("nfsservctl", unimplementedFunc);
-    /* 255 */ SyscallDesc("aplib", unimplementedFunc);
-    /* 256 */ SyscallDesc("clock_settime", unimplementedFunc);
-    /* 257 */ SyscallDesc("clock_gettime", unimplementedFunc);
-    /* 258 */ SyscallDesc("clock_getres", unimplementedFunc);
-    /* 259 */ SyscallDesc("clock_nanosleep", unimplementedFunc);
-    /* 260 */ SyscallDesc("sched_getaffinity", unimplementedFunc);
-    /* 261 */ SyscallDesc("sched_setaffinity", unimplementedFunc);
-    /* 262 */ SyscallDesc("timer_settime", unimplementedFunc);
-    /* 263 */ SyscallDesc("timer_gettime", unimplementedFunc);
-    /* 264 */ SyscallDesc("timer_getoverrun", unimplementedFunc);
-    /* 265 */ SyscallDesc("timer_delete", unimplementedFunc);
-    /* 266 */ SyscallDesc("timer_create", unimplementedFunc);
-    /* 267 */ SyscallDesc("vserver", unimplementedFunc);
-    /* 268 */ SyscallDesc("io_setup", unimplementedFunc);
-    /* 269 */ SyscallDesc("io_destroy", unimplementedFunc);
-    /* 270 */ SyscallDesc("io_submit", unimplementedFunc);
-    /* 271 */ SyscallDesc("io_cancel", unimplementedFunc);
-    /* 272 */ SyscallDesc("io_getevents", unimplementedFunc);
-    /* 273 */ SyscallDesc("mq_open", unimplementedFunc);
-    /* 274 */ SyscallDesc("mq_unlink", unimplementedFunc);
-    /* 275 */ SyscallDesc("mq_timedsend", unimplementedFunc);
-    /* 276 */ SyscallDesc("mq_timedreceive", unimplementedFunc);
-    /* 277 */ SyscallDesc("mq_notify", unimplementedFunc);
-    /* 278 */ SyscallDesc("mq_getsetattr", unimplementedFunc);
-    /* 279 */ SyscallDesc("waitid", unimplementedFunc);
-    /* 280 */ SyscallDesc("sys_setaltroot", unimplementedFunc);
-    /* 281 */ SyscallDesc("add_key", unimplementedFunc);
-    /* 282 */ SyscallDesc("request_key", unimplementedFunc);
-    /* 283 */ SyscallDesc("keyctl", unimplementedFunc);
-};
-
-SparcLinuxProcess::SparcLinuxProcess(const std::string &name,
-                                     ObjectFile *objFile,
-                                     int stdin_fd,
-                                     int stdout_fd,
-                                     int stderr_fd,
-                                     std::vector<std::string> &argv,
-                                     std::vector<std::string> &envp)
-    : LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp),
-     Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc))
-{
-    // The sparc syscall table must be <= 283 entries because that is all there
-    // is space for.
-    assert(Num_Syscall_Descs <= 283);
-
-    init_regs->intRegFile[0] = 0;
-}
-
-
-
-SyscallDesc*
-AlphaLinuxProcess::getDesc(int callnum)
-{
-    if (callnum < 0 || callnum > Num_Syscall_Descs)
-        return NULL;
-    return &syscallDescs[callnum];
-}
diff --git a/arch/sparc/linux/process.hh b/arch/sparc/linux/process.hh
deleted file mode 100644
index c41406b4b..000000000
--- a/arch/sparc/linux/process.hh
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __SPARC_LINUX_PROCESS_HH__
-#define __SPARC_LINUX_PROCESS_HH__
-
-#include "sim/process.hh"
-
-
-/// A process with emulated SPARC/Linux syscalls.
-class SparcLinuxProcess : public LiveProcess
-{
-  public:
-    /// Constructor.
-    SparcLinuxProcess(const std::string &name,
-                      ObjectFile *objFile,
-                      int stdin_fd, int stdout_fd, int stderr_fd,
-                      std::vector<std::string> &argv,
-                      std::vector<std::string> &envp);
-
-    virtual SyscallDesc* getDesc(int callnum);
-
-    /// The target system's hostname.
-    static const char *hostname;
-
-     /// Array of syscall descriptors, indexed by call number.
-    static SyscallDesc syscallDescs[];
-
-    const int Num_Syscall_Descs;
-};
-
-
-#endif // __ALPHA_LINUX_PROCESS_HH__
diff --git a/arch/sparc/process.cc b/arch/sparc/process.cc
deleted file mode 100644
index 53a215379..000000000
--- a/arch/sparc/process.cc
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/sparc/process.hh"
-
-namespace SparcISA
-{
-
-LiveProcess *
-createProcess(const string &nm, ObjectFile * objFile,
-        int stdin_fd, int stdout_fd, int stderr_fd,
-        vector<string> &argv, vector<string> &envp)
-{
-    LiveProcess * process = NULL;
-    if (objFile->getArch() != ObjectFile::SPARC)
-        fatal("Object file does not match architecture.");
-    switch (objFile->getOpSys()) {
-      case ObjectFile::Linux:
-        process = new SparcLinuxProcess(nm, objFile,
-                                        stdin_fd, stdout_fd, stderr_fd,
-                                        argv, envp);
-        break;
-
-      case ObjectFile::Solaris:
-      default:
-        fatal("Unknown/unsupported operating system.");
-    }
-    return process;
-}
-
-} // namespace SparcISA
diff --git a/arch/sparc/process.hh b/arch/sparc/process.hh
deleted file mode 100644
index 48041a316..000000000
--- a/arch/sparc/process.hh
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __SPARC_PROCESS_HH__
-#define __SPARC_PROCESS_HH__
-
-#include "arch/sparc/linux/process.hh"
-#include "base/loader/object_file.hh"
-
-namespace SparcISA
-{
-
-LiveProcess *
-createProcess(const string &nm, ObjectFile * objFile,
-        int stdin_fd, int stdout_fd, int stderr_fd,
-        vector<string> &argv, vector<string> &envp);
-
-} // namespace SparcISA
-
-#endif // __SPARC_PROCESS_HH__
diff --git a/arch/sparc/stacktrace.hh b/arch/sparc/stacktrace.hh
deleted file mode 100644
index 1d8d97a79..000000000
--- a/arch/sparc/stacktrace.hh
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (c) 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_ALPHA_STACKTRACE_HH__
-#define __ARCH_ALPHA_STACKTRACE_HH__
-
-#include "base/trace.hh"
-#include "cpu/static_inst.hh"
-
-class ExecContext;
-class StackTrace;
-
-class ProcessInfo
-{
-  private:
-    ExecContext *xc;
-
-    int thread_info_size;
-    int task_struct_size;
-    int task_off;
-    int pid_off;
-    int name_off;
-
-  public:
-    ProcessInfo(ExecContext *_xc);
-
-    Addr task(Addr ksp) const;
-    int pid(Addr ksp) const;
-    std::string name(Addr ksp) const;
-};
-
-class StackTrace
-{
-  protected:
-    typedef TheISA::MachInst MachInst;
-  private:
-    ExecContext *xc;
-    std::vector<Addr> stack;
-
-  private:
-    bool isEntry(Addr addr);
-    bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra);
-    bool decodeSave(MachInst inst, int &reg, int &disp);
-    bool decodeStack(MachInst inst, int &disp);
-
-    void trace(ExecContext *xc, bool is_call);
-
-  public:
-    StackTrace();
-    StackTrace(ExecContext *xc, StaticInstPtr inst);
-    ~StackTrace();
-
-    void clear()
-    {
-        xc = 0;
-        stack.clear();
-    }
-
-    bool valid() const { return xc != NULL; }
-    bool trace(ExecContext *xc, StaticInstPtr inst);
-
-  public:
-    const std::vector<Addr> &getstack() const { return stack; }
-
-    static const int user = 1;
-    static const int console = 2;
-    static const int unknown = 3;
-
-#if TRACING_ON
-  private:
-    void dump();
-
-  public:
-    void dprintf() { if (DTRACE(Stack)) dump(); }
-#else
-  public:
-    void dprintf() {}
-#endif
-};
-
-inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
-{
-    if (!inst->isCall() && !inst->isReturn())
-        return false;
-
-    if (valid())
-        clear();
-
-    trace(xc, !inst->isReturn());
-    return true;
-}
-
-#endif // __ARCH_ALPHA_STACKTRACE_HH__