diff options
Diffstat (limited to 'arch/sparc')
| -rw-r--r-- | arch/sparc/isa/formats.isa | 12 | ||||
| -rw-r--r-- | arch/sparc/isa/main.isa | 12 | ||||
| -rw-r--r-- | arch/sparc/isa/operands.isa | 25 |
3 files changed, 24 insertions, 25 deletions
diff --git a/arch/sparc/isa/formats.isa b/arch/sparc/isa/formats.isa index a21e1c110..547f8be48 100644 --- a/arch/sparc/isa/formats.isa +++ b/arch/sparc/isa/formats.isa @@ -1,19 +1,19 @@ //Include the basic format //Templates from this format are used later -##include "m5/arch/sparc/isa_desc/formats/basic.isa" +##include "m5/arch/sparc/isa/formats/basic.isa" //Include the integerOp and integerOpCc format -##include "m5/arch/sparc/isa_desc/formats/integerop.isa" +##include "m5/arch/sparc/isa/formats/integerop.isa" //Include the mem format -##include "m5/arch/sparc/isa_desc/formats/mem.isa" +##include "m5/arch/sparc/isa/formats/mem.isa" //Include the trap format -##include "m5/arch/sparc/isa_desc/formats/trap.isa" +##include "m5/arch/sparc/isa/formats/trap.isa" //Include the branch format -##include "m5/arch/sparc/isa_desc/formats/branch.isa" +##include "m5/arch/sparc/isa/formats/branch.isa" //Include the noop format -##include "m5/arch/sparc/isa_desc/formats/noop.isa" +##include "m5/arch/sparc/isa/formats/noop.isa" diff --git a/arch/sparc/isa/main.isa b/arch/sparc/isa/main.isa index 8b6166d34..ab0290d58 100644 --- a/arch/sparc/isa/main.isa +++ b/arch/sparc/isa/main.isa @@ -26,7 +26,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -##include "m5/arch/sparc/isa_desc/includes.isa" +##include "m5/arch/sparc/isa/includes.isa" //////////////////////////////////////////////////////////////////// // @@ -37,16 +37,16 @@ namespace SparcISA; //Include the bitfield definitions -##include "m5/arch/sparc/isa_desc/bitfields.isa" +##include "m5/arch/sparc/isa/bitfields.isa" //Include the operand_types and operand definitions -##include "m5/arch/sparc/isa_desc/operands.isa" +##include "m5/arch/sparc/isa/operands.isa" //Include the base class for sparc instructions, and some support code -##include "m5/arch/sparc/isa_desc/base.isa" +##include "m5/arch/sparc/isa/base.isa" //Include the definitions for the instruction formats -##include "m5/arch/sparc/isa_desc/formats.isa" +##include "m5/arch/sparc/isa/formats.isa" //Include the decoder definition -##include "m5/arch/sparc/isa_desc/decoder.isa" +##include "m5/arch/sparc/isa/decoder.isa" diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa index 77de6c9c4..c5ba263d6 100644 --- a/arch/sparc/isa/operands.isa +++ b/arch/sparc/isa/operands.isa @@ -16,18 +16,17 @@ def operands {{ # Int regs default to unsigned, but code should not count on this. # For clarity, descriptions that depend on unsigned behavior should # explicitly specify '.uq'. - 'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1), - 'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2), - 'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3), - #'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1), - #'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2), - #'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3), - 'Mem': MemOperandTraits('udw', None, - ('IsMemRef', 'IsLoad', 'IsStore'), 4) - #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4), - #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1), - #'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1), + 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), + 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2), + 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3), + #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), + #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), + #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), + 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4) + #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), + #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), + #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), # The next two are hacks for non-full-system call-pal emulation - #'R0': IntRegOperandTraits('uq', '0', None, 1), - #'R16': IntRegOperandTraits('uq', '16', None, 1) + #'R0': ('IntReg', 'uq', '0', None, 1), + #'R16': ('IntReg', 'uq', '16', None, 1) }}; |