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-rw-r--r--arch/sparc/isa_traits.hh234
-rw-r--r--arch/sparc/linux/process.cc1
-rw-r--r--arch/sparc/stacktrace.hh119
3 files changed, 230 insertions, 124 deletions
diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
index 7f654e33b..bd3c35beb 100644
--- a/arch/sparc/isa_traits.hh
+++ b/arch/sparc/isa_traits.hh
@@ -57,42 +57,59 @@ class StaticInstPtr;
namespace SparcISA
{
typedef uint32_t MachInst;
- typedef uint64_t Addr;
+ typedef uint64_t ExtMachInst;
typedef uint8_t RegIndex;
- enum
- {
- MemoryEnd = 0xffffffffffffffffULL,
-
- NumFloatRegs = 32,
- NumMiscRegs = 32,
-
- MaxRegsOfAnyType = 32,
- // Static instruction parameters
- MaxInstSrcRegs = 3,
- MaxInstDestRegs = 2,
-
- // Maximum trap level
- MaxTL = 4,
-
- // semantically meaningful register indices
- ZeroReg = 0 // architecturally meaningful
- // the rest of these depend on the ABI
- SyscallNumReg = 1,
- ArgumentReg0 = 8,
- ArgumentReg1 = 9,
- ArgumentReg2 = 10,
- ArgumentReg3 = 11,
- ArgumentReg4 = 12,
- ArgumentReg5 = 13,
- StackPoniterReg = 14,
- ReturnAddressReg = 31, // Post Call, precall, 15
- ReturnValueReg = 8, // Post return, 24 is pre-return.
- // Some OS use a second register (o1) to return a second value
- // for some syscalls
- SyscallPseudoReturnReg = 9,
- FramePointerReg = 30
-};
+ const int NumFloatRegs = 32;
+ const int NumMiscRegs = 32;
+
+ const int // Maximum trap level
+ const int MaxTL = 4;
+ const int
+ const int // semantically meaningful register indices
+ const int ZeroReg = 0; // architecturally meaningful
+ const int // the rest of these depend on the ABI
+ const int StackPointerReg = 14;
+ const int ReturnAddressReg = 31; // post call, precall is 15
+ const int ReturnValueReg = 8; // Post return, 24 is pre-return.
+ const int FramePointerReg = 30;
+ const int ArgumentReg0 = 8;
+ const int ArgumentReg1 = 9;
+ const int ArgumentReg2 = 10;
+ const int ArgumentReg3 = 11;
+ const int ArgumentReg4 = 12;
+ const int ArgumentReg5 = 13;
+ // Some OS syscall sue a second register (o1) to return a second value
+ const int SyscallPseudoReturnReg = ArgumentReg1;
+
+
+ //8K. This value is implmentation specific; and should probably
+ //be somewhere else.
+ const int LogVMPageSize = 13;
+ const int VMPageSize = (1 << LogVMPageSize);
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
typedef uint64_t IntReg;
class IntRegFile
@@ -113,6 +130,12 @@ namespace SparcISA
void unserialize(Checkpoint *cp, const std::string &section);
+ typedef float float32_t;
+ typedef double float64_t;
+ //FIXME This actually usually refers to a 10 byte float, rather than a
+ //16 byte float as required. This data type may have to be emulated.
+ typedef long double float128_t;
+
class FloatRegFile
{
private:
@@ -120,7 +143,7 @@ namespace SparcISA
//is aligned correctly in memory
union
{
- long double rawRegs[16];
+ float128_t rawRegs[16];
uint64_t regDump[32];
};
class QuadRegs
@@ -129,7 +152,7 @@ namespace SparcISA
FloatRegFile * parent;
public:
QuadRegs(FloatRegFile * p) : parent(p) {;}
- long double & operator [] (RegIndex index)
+ float128_t & operator [] (RegIndex index)
{
//Quad floats are index by the single
//precision register the start on,
@@ -144,13 +167,13 @@ namespace SparcISA
FloatRegFile * parent;
public:
DoubleRegs(FloatRegFile * p) : parent(p) {;}
- double & operator [] (RegIndex index)
+ float64_t & operator [] (RegIndex index)
{
//Double floats are index by the single
//precision register the start on,
//and only 32 should be accessed
index = (index >> 1) & 0x1F;
- return ((double *)parent->rawRegs)[index];
+ return ((float64_t *)parent->rawRegs)[index];
}
};
class SingleRegs
@@ -159,11 +182,11 @@ namespace SparcISA
FloatRegFile * parent;
public:
SingleRegs(FloatRegFile * p) : parent(p) {;}
- float & operator [] (RegIndex index)
+ float32_t & operator [] (RegIndex index)
{
//Only 32 single floats should be accessed
index &= 0x1F;
- return ((float *)parent->rawRegs)[index];
+ return ((float32_t *)parent->rawRegs)[index];
}
};
public:
@@ -183,7 +206,7 @@ namespace SparcISA
// The control registers, broken out into fields
class MiscRegFile
{
- public:
+ private:
union
{
uint16_t pstate; // Process State Register
@@ -207,7 +230,7 @@ namespace SparcISA
struct
{
uint64_t value:32; // The actual value stored in y
- const uint64_t :32; // reserved bits
+ uint64_t :32; // reserved bits
} yFields;
};
uint8_t pil; // Process Interrupt Register
@@ -228,8 +251,8 @@ namespace SparcISA
uint8_t v:1; // Overflow
uint8_t z:1; // Zero
uint8_t n:1; // Negative
- } iccFields:4;
- } :4;
+ } iccFields;
+ };
union
{
uint8_t xcc:4; // 64-bit condition codes
@@ -239,8 +262,8 @@ namespace SparcISA
uint8_t v:1; // Overflow
uint8_t z:1; // Zero
uint8_t n:1; // Negative
- } xccFields:4;
- } :4;
+ } xccFields;
+ };
} ccrFields;
};
uint8_t asi; // Address Space Identifier
@@ -256,9 +279,9 @@ namespace SparcISA
{
//Values are from previous trap level
uint64_t cwp:5; // Current Window Pointer
- const uint64_t :2; // Reserved bits
+ uint64_t :2; // Reserved bits
uint64_t pstate:10; // Process State
- const uint64_t :6; // Reserved bits
+ uint64_t :6; // Reserved bits
uint64_t asi:8; // Address Space Identifier
uint64_t ccr:8; // Condition Code Register
} tstateFields[MaxTL];
@@ -271,7 +294,7 @@ namespace SparcISA
uint64_t counter:63; // Clock-tick count
uint64_t npt:1; // Non-priveleged trap
} tickFields;
- }
+ };
uint8_t cansave; // Savable windows
uint8_t canrestore; // Restorable windows
uint8_t otherwin; // Other windows
@@ -293,9 +316,9 @@ namespace SparcISA
struct
{
uint64_t maxwin:5; // Max CWP value
- const uint64_t :2; // Reserved bits
+ uint64_t :2; // Reserved bits
uint64_t maxtl:8; // Maximum trap level
- const uint64_t :8; // Reserved bits
+ uint64_t :8; // Reserved bits
uint64_t mask:8; // Processor mask set revision number
uint64_t impl:16; // Implementation identification number
uint64_t manuf:16; // Manufacturer code
@@ -316,8 +339,8 @@ namespace SparcISA
uint64_t ufc:1; // Underflow
uint64_t ofc:1; // Overflow
uint64_t nvc:1; // Invalid operand
- } cexecFields:5;
- } :5;
+ } cexecFields;
+ };
union
{
uint64_t aexc:5; // Accrued exception
@@ -328,15 +351,15 @@ namespace SparcISA
uint64_t ufc:1; // Underflow
uint64_t ofc:1; // Overflow
uint64_t nvc:1; // Invalid operand
- } aexecFields:5;
- } :5;
+ } aexecFields;
+ };
uint64_t fcc0:2; // Floating-Point condtion codes
- const uint64_t :1; // Reserved bits
+ uint64_t :1; // Reserved bits
uint64_t qne:1; // Deferred trap queue not empty
// with no queue, it should read 0
uint64_t ftt:3; // Floating-Point trap type
uint64_t ver:3; // Version (of the FPU)
- const uint64_t :2; // Reserved bits
+ uint64_t :2; // Reserved bits
uint64_t ns:1; // Nonstandard floating point
union
{
@@ -348,16 +371,16 @@ namespace SparcISA
uint64_t ufm:1; // Underflow
uint64_t ofm:1; // Overflow
uint64_t nvm:1; // Invalid operand
- } temFields:5;
- } :5;
- const uint64_t :2; // Reserved bits
+ } temFields;
+ };
+ uint64_t :2; // Reserved bits
uint64_t rd:2; // Rounding direction
uint64_t fcc1:2; // Floating-Point condition codes
uint64_t fcc2:2; // Floating-Point condition codes
uint64_t fcc3:2; // Floating-Point condition codes
- const uint64_t :26; // Reserved bits
+ uint64_t :26; // Reserved bits
} fsrFields;
- }
+ };
union
{
uint8_t fprs; // Floating-Point Register State
@@ -365,63 +388,34 @@ namespace SparcISA
{
uint8_t dl:1; // Dirty lower
uint8_t du:1; // Dirty upper
- fef:1; // FPRS enable floating-Point
+ uint8_t fef:1; // FPRS enable floating-Point
} fprsFields;
};
- void serialize(std::ostream & os)
- {
- SERIALIZE_SCALAR(pstate);
- SERIAlIZE_SCALAR(tba);
- SERIALIZE_SCALAR(y);
- SERIALIZE_SCALAR(pil);
- SERIALIZE_SCALAR(cwp);
- SERIALIZE_ARRAY(tt, MaxTL);
- SERIALIZE_SCALAR(ccr);
- SERIALIZE_SCALAR(asi);
- SERIALIZE_SCALAR(tl);
- SERIALIZE_SCALAR(tpc);
- SERIALIZE_SCALAR(tnpc);
- SERIALIZE_ARRAY(tstate, MaxTL);
- SERIALIZE_SCALAR(tick);
- SERIALIZE_SCALAR(cansave);
- SERIALIZE_SCALAR(canrestore);
- SERIALIZE_SCALAR(otherwin);
- SERIALIZE_SCALAR(cleanwin);
- SERIALIZE_SCALAR(wstate);
- SERIALIZE_SCALAR(ver);
- SERIALIZE_SCALAR(fsr);
- SERIALIZE_SCALAR(fprs);
- }
+ public:
+ MiscReg readReg(int misc_reg);
- void unserialize(Checkpoint &* cp, std::string & section)
- {
- UNSERIALIZE_SCALAR(pstate);
- UNSERIAlIZE_SCALAR(tba);
- UNSERIALIZE_SCALAR(y);
- UNSERIALIZE_SCALAR(pil);
- UNSERIALIZE_SCALAR(cwp);
- UNSERIALIZE_ARRAY(tt, MaxTL);
- UNSERIALIZE_SCALAR(ccr);
- UNSERIALIZE_SCALAR(asi);
- UNSERIALIZE_SCALAR(tl);
- UNSERIALIZE_SCALAR(tpc);
- UNSERIALIZE_SCALAR(tnpc);
- UNSERIALIZE_ARRAY(tstate, MaxTL);
- UNSERIALIZE_SCALAR(tick);
- UNSERIALIZE_SCALAR(cansave);
- UNSERIALIZE_SCALAR(canrestore);
- UNSERIALIZE_SCALAR(otherwin);
- UNSERIALIZE_SCALAR(cleanwin);
- UNSERIALIZE_SCALAR(wstate);
- UNSERIALIZE_SCALAR(ver);
- UNSERIALIZE_SCALAR(fsr);
- UNSERIALIZE_SCALAR(fprs);
- }
+ MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
+
+ Fault setReg(int misc_reg, const MiscReg &val);
+
+ Fault setRegWithEffect(int misc_reg, const MiscReg &val,
+ ExecContext *xc);
+
+ void serialize(std::ostream & os);
+
+ void unserialize(Checkpoint * cp, std::string & section);
};
typedef union
{
+ float32_t singReg;
+ float64_t doubReg;
+ float128_t quadReg;
+ } FloatReg;
+
+ typedef union
+ {
IntReg intreg;
FloatReg fpreg;
MiscReg ctrlreg;
@@ -435,30 +429,31 @@ namespace SparcISA
Addr pc; // Program Counter
Addr npc; // Next Program Counter
+ Addr nnpc;
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
- static StaticInstPtr decodeInst(MachInst);
+ StaticInstPtr decodeInst(MachInst);
// return a no-op instruction... used for instruction fetch faults
- static const MachInst NoopMachInst;
+ extern const MachInst NoopMachInst;
// Instruction address compression hooks
- static inline Addr realPCToFetchPC(const Addr &addr)
+ inline Addr realPCToFetchPC(const Addr &addr)
{
return addr;
}
- static inline Addr fetchPCToRealPC(const Addr &addr)
+ inline Addr fetchPCToRealPC(const Addr &addr)
{
return addr;
}
// the size of "fetched" instructions (not necessarily the size
// of real instructions for PISA)
- static inline size_t fetchInstSize()
+ inline size_t fetchInstSize()
{
return sizeof(MachInst);
}
@@ -468,7 +463,6 @@ namespace SparcISA
* @param xc The execution context.
*/
template <class XC>
- static void zeroRegisters(XC *xc);
static inline setSyscallReturn(SyscallReturn return_value, RegFile *regs)
{
@@ -487,12 +481,6 @@ namespace SparcISA
}
};
-const int VMPageSize = TheISA::VMPageSize;
-const int LogVMPageSize = TheISA::LogVMPageSize;
-const int ZeroReg = TheISA::ZeroReg;
-const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
-const int MaxAddr = (Addr)-1;
-
#if !FULL_SYSTEM
class SyscallReturn
{
diff --git a/arch/sparc/linux/process.cc b/arch/sparc/linux/process.cc
index 456f99b32..5965e6da9 100644
--- a/arch/sparc/linux/process.cc
+++ b/arch/sparc/linux/process.cc
@@ -62,7 +62,6 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
SyscallDesc SparcLinuxProcess::syscallDescs[] = {
/* 0 */ SyscallDesc("restart_syscall", unimplimentedFunc);
/* 1 */ SyscallDesc("exit", exitFunc);
- /* 2 */ SyscallDesc("fork", unimplimentedFunc);
/* 3 */ SyscallDesc("read", readFunc);
/* 4 */ SyscallDesc("write", writeFunc);
/* 5 */ SyscallDesc("open", openFunc<Linux>);
diff --git a/arch/sparc/stacktrace.hh b/arch/sparc/stacktrace.hh
new file mode 100644
index 000000000..1d8d97a79
--- /dev/null
+++ b/arch/sparc/stacktrace.hh
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_ALPHA_STACKTRACE_HH__
+#define __ARCH_ALPHA_STACKTRACE_HH__
+
+#include "base/trace.hh"
+#include "cpu/static_inst.hh"
+
+class ExecContext;
+class StackTrace;
+
+class ProcessInfo
+{
+ private:
+ ExecContext *xc;
+
+ int thread_info_size;
+ int task_struct_size;
+ int task_off;
+ int pid_off;
+ int name_off;
+
+ public:
+ ProcessInfo(ExecContext *_xc);
+
+ Addr task(Addr ksp) const;
+ int pid(Addr ksp) const;
+ std::string name(Addr ksp) const;
+};
+
+class StackTrace
+{
+ protected:
+ typedef TheISA::MachInst MachInst;
+ private:
+ ExecContext *xc;
+ std::vector<Addr> stack;
+
+ private:
+ bool isEntry(Addr addr);
+ bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra);
+ bool decodeSave(MachInst inst, int &reg, int &disp);
+ bool decodeStack(MachInst inst, int &disp);
+
+ void trace(ExecContext *xc, bool is_call);
+
+ public:
+ StackTrace();
+ StackTrace(ExecContext *xc, StaticInstPtr inst);
+ ~StackTrace();
+
+ void clear()
+ {
+ xc = 0;
+ stack.clear();
+ }
+
+ bool valid() const { return xc != NULL; }
+ bool trace(ExecContext *xc, StaticInstPtr inst);
+
+ public:
+ const std::vector<Addr> &getstack() const { return stack; }
+
+ static const int user = 1;
+ static const int console = 2;
+ static const int unknown = 3;
+
+#if TRACING_ON
+ private:
+ void dump();
+
+ public:
+ void dprintf() { if (DTRACE(Stack)) dump(); }
+#else
+ public:
+ void dprintf() {}
+#endif
+};
+
+inline bool
+StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
+{
+ if (!inst->isCall() && !inst->isReturn())
+ return false;
+
+ if (valid())
+ clear();
+
+ trace(xc, !inst->isReturn());
+ return true;
+}
+
+#endif // __ARCH_ALPHA_STACKTRACE_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 18:23:55 +0000