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-rw-r--r--arch/alpha/SConscript8
-rw-r--r--arch/alpha/linux/process.cc (renamed from arch/alpha/linux_process.cc)2
-rw-r--r--arch/alpha/linux/process.hh (renamed from arch/alpha/linux_process.hh)0
-rw-r--r--arch/alpha/process.hh4
-rw-r--r--arch/alpha/tru64/process.cc (renamed from arch/alpha/tru64_process.cc)2
-rw-r--r--arch/alpha/tru64/process.hh (renamed from arch/alpha/tru64_process.hh)0
-rw-r--r--arch/sparc/faults.cc170
-rw-r--r--arch/sparc/faults.hh268
-rw-r--r--arch/sparc/linux/process.cc (renamed from arch/sparc/linux_process.cc)0
-rw-r--r--arch/sparc/linux/process.hh (renamed from arch/sparc/linux_process.hh)0
-rw-r--r--arch/sparc/process.hh2
11 files changed, 449 insertions, 7 deletions
diff --git a/arch/alpha/SConscript b/arch/alpha/SConscript
index 03d73eef7..6dec2d070 100644
--- a/arch/alpha/SConscript
+++ b/arch/alpha/SConscript
@@ -56,14 +56,18 @@ full_system_sources = Split('''
osfpal.cc
stacktrace.cc
vtophys.cc
+ system.cc
+ freebsd/system.cc
+ linux/system.cc
+ tru64/system.cc
''')
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
common_syscall_emul.cc
- linux_process.cc
- tru64_process.cc
+ linux/process.cc
+ tru64/process.cc
process.cc
''')
diff --git a/arch/alpha/linux_process.cc b/arch/alpha/linux/process.cc
index 0b193fb55..d78e6a4ee 100644
--- a/arch/alpha/linux_process.cc
+++ b/arch/alpha/linux/process.cc
@@ -27,7 +27,7 @@
*/
#include "arch/alpha/common_syscall_emul.hh"
-#include "arch/alpha/linux_process.hh"
+#include "arch/alpha/linux/process.hh"
#include "arch/alpha/isa_traits.hh"
#include "base/trace.hh"
diff --git a/arch/alpha/linux_process.hh b/arch/alpha/linux/process.hh
index 7de1b1ac1..7de1b1ac1 100644
--- a/arch/alpha/linux_process.hh
+++ b/arch/alpha/linux/process.hh
diff --git a/arch/alpha/process.hh b/arch/alpha/process.hh
index 7b660ddd0..4a2a4212e 100644
--- a/arch/alpha/process.hh
+++ b/arch/alpha/process.hh
@@ -31,8 +31,8 @@
#include <string>
-#include "arch/alpha/linux_process.hh"
-#include "arch/alpha/tru64_process.hh"
+#include "arch/alpha/linux/process.hh"
+#include "arch/alpha/tru64/process.hh"
#include "base/loader/object_file.hh"
namespace AlphaISA
diff --git a/arch/alpha/tru64_process.cc b/arch/alpha/tru64/process.cc
index 90e8b1139..58d41e3ef 100644
--- a/arch/alpha/tru64_process.cc
+++ b/arch/alpha/tru64/process.cc
@@ -28,7 +28,7 @@
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/common_syscall_emul.hh"
-#include "arch/alpha/tru64_process.hh"
+#include "arch/alpha/tru64/process.hh"
#include "cpu/exec_context.hh"
#include "kern/tru64/tru64.hh"
#include "mem/functional/functional.hh"
diff --git a/arch/alpha/tru64_process.hh b/arch/alpha/tru64/process.hh
index 051760702..051760702 100644
--- a/arch/alpha/tru64_process.hh
+++ b/arch/alpha/tru64/process.hh
diff --git a/arch/sparc/faults.cc b/arch/sparc/faults.cc
new file mode 100644
index 000000000..0a836363c
--- /dev/null
+++ b/arch/sparc/faults.cc
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/alpha/faults.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/base.hh"
+#include "base/trace.hh"
+#include "kern/kernel_stats.hh"
+
+namespace AlphaISA
+{
+
+FaultName MachineCheckFault::_name = "mchk";
+FaultVect MachineCheckFault::_vect = 0x0401;
+FaultStat MachineCheckFault::_stat;
+
+FaultName AlignmentFault::_name = "unalign";
+FaultVect AlignmentFault::_vect = 0x0301;
+FaultStat AlignmentFault::_stat;
+
+FaultName ResetFault::_name = "reset";
+FaultVect ResetFault::_vect = 0x0001;
+FaultStat ResetFault::_stat;
+
+FaultName ArithmeticFault::_name = "arith";
+FaultVect ArithmeticFault::_vect = 0x0501;
+FaultStat ArithmeticFault::_stat;
+
+FaultName InterruptFault::_name = "interrupt";
+FaultVect InterruptFault::_vect = 0x0101;
+FaultStat InterruptFault::_stat;
+
+FaultName NDtbMissFault::_name = "dtb_miss_single";
+FaultVect NDtbMissFault::_vect = 0x0201;
+FaultStat NDtbMissFault::_stat;
+
+FaultName PDtbMissFault::_name = "dtb_miss_double";
+FaultVect PDtbMissFault::_vect = 0x0281;
+FaultStat PDtbMissFault::_stat;
+
+FaultName DtbPageFault::_name = "dfault";
+FaultVect DtbPageFault::_vect = 0x0381;
+FaultStat DtbPageFault::_stat;
+
+FaultName DtbAcvFault::_name = "dfault";
+FaultVect DtbAcvFault::_vect = 0x0381;
+FaultStat DtbAcvFault::_stat;
+
+FaultName ItbMissFault::_name = "itbmiss";
+FaultVect ItbMissFault::_vect = 0x0181;
+FaultStat ItbMissFault::_stat;
+
+FaultName ItbPageFault::_name = "itbmiss";
+FaultVect ItbPageFault::_vect = 0x0181;
+FaultStat ItbPageFault::_stat;
+
+FaultName ItbAcvFault::_name = "iaccvio";
+FaultVect ItbAcvFault::_vect = 0x0081;
+FaultStat ItbAcvFault::_stat;
+
+FaultName UnimplementedOpcodeFault::_name = "opdec";
+FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
+FaultStat UnimplementedOpcodeFault::_stat;
+
+FaultName FloatEnableFault::_name = "fen";
+FaultVect FloatEnableFault::_vect = 0x0581;
+FaultStat FloatEnableFault::_stat;
+
+FaultName PalFault::_name = "pal";
+FaultVect PalFault::_vect = 0x2001;
+FaultStat PalFault::_stat;
+
+FaultName IntegerOverflowFault::_name = "intover";
+FaultVect IntegerOverflowFault::_vect = 0x0501;
+FaultStat IntegerOverflowFault::_stat;
+
+#if FULL_SYSTEM
+
+void AlphaFault::invoke(ExecContext * xc)
+{
+ DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
+ xc->cpu->recordEvent(csprintf("Fault %s", name()));
+
+ assert(!xc->misspeculating());
+ xc->kernelStats->fault(this);
+
+ // exception restart address
+ if (setRestartAddress() || !xc->inPalMode())
+ xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
+
+ if (skipFaultingInstruction()) {
+ // traps... skip faulting instruction.
+ xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
+ xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
+ }
+
+ if (!xc->inPalMode())
+ AlphaISA::swap_palshadow(&(xc->regs), true);
+
+ xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
+ xc->regs.npc = xc->regs.pc + sizeof(MachInst);
+}
+
+void ArithmeticFault::invoke(ExecContext * xc)
+{
+ DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
+ xc->cpu->recordEvent(csprintf("Fault %s", name()));
+
+ assert(!xc->misspeculating());
+ xc->kernelStats->fault(this);
+
+ panic("Arithmetic traps are unimplemented!");
+}
+
+
+/*void ArithmeticFault::invoke(ExecContext * xc)
+{
+ panic("Arithmetic traps are unimplemented!");
+}*/
+
+#endif
+
+} // namespace AlphaISA
+
+/*Fault * ListOfFaults[] = {
+ (Fault *)&NoFault,
+ (Fault *)&ResetFault,
+ (Fault *)&MachineCheckFault,
+ (Fault *)&ArithmeticFault,
+ (Fault *)&InterruptFault,
+ (Fault *)&NDtbMissFault,
+ (Fault *)&PDtbMissFault,
+ (Fault *)&AlignmentFault,
+ (Fault *)&DtbPageFault,
+ (Fault *)&DtbAcvFault,
+ (Fault *)&ItbMissFault,
+ (Fault *)&ItbPageFault,
+ (Fault *)&ItbAcvFault,
+ (Fault *)&UnimplementedOpcodeFault,
+ (Fault *)&FloatEnableFault,
+ (Fault *)&PalFault,
+ (Fault *)&IntegerOverflowFault,
+ };
+
+int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);*/
diff --git a/arch/sparc/faults.hh b/arch/sparc/faults.hh
new file mode 100644
index 000000000..c4a72e07c
--- /dev/null
+++ b/arch/sparc/faults.hh
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ALPHA_FAULTS_HH__
+#define __ALPHA_FAULTS_HH__
+
+#include "sim/faults.hh"
+
+// The design of the "name" and "vect" functions is in sim/faults.hh
+
+namespace AlphaISA
+{
+
+typedef const Addr FaultVect;
+
+class AlphaFault : public virtual FaultBase
+{
+ protected:
+ virtual bool skipFaultingInstruction() {return false;}
+ virtual bool setRestartAddress() {return true;}
+ public:
+#if FULL_SYSTEM
+ void invoke(ExecContext * xc);
+#endif
+ virtual FaultVect vect() = 0;
+};
+
+class MachineCheckFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+ bool isMachineCheckFault() {return true;}
+};
+
+class AlignmentFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+ bool isAlignmentFault() {return true;}
+};
+
+static inline Fault genMachineCheckFault()
+{
+ return new MachineCheckFault;
+}
+
+static inline Fault genAlignmentFault()
+{
+ return new AlignmentFault;
+}
+
+class ResetFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class ArithmeticFault : public AlphaFault
+{
+ protected:
+ bool skipFaultingInstruction() {return true;}
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+#if FULL_SYSTEM
+ void invoke(ExecContext * xc);
+#endif
+};
+
+class InterruptFault : public AlphaFault
+{
+ protected:
+ bool setRestartAddress() {return false;}
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class NDtbMissFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class PDtbMissFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class DtbPageFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class DtbAcvFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class ItbMissFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class ItbPageFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class ItbAcvFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class UnimplementedOpcodeFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class FloatEnableFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class PalFault : public AlphaFault
+{
+ protected:
+ bool skipFaultingInstruction() {return true;}
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class IntegerOverflowFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+} // AlphaISA namespace
+
+#endif // __FAULTS_HH__
diff --git a/arch/sparc/linux_process.cc b/arch/sparc/linux/process.cc
index d1c439d72..d1c439d72 100644
--- a/arch/sparc/linux_process.cc
+++ b/arch/sparc/linux/process.cc
diff --git a/arch/sparc/linux_process.hh b/arch/sparc/linux/process.hh
index c41406b4b..c41406b4b 100644
--- a/arch/sparc/linux_process.hh
+++ b/arch/sparc/linux/process.hh
diff --git a/arch/sparc/process.hh b/arch/sparc/process.hh
index 387649d47..48041a316 100644
--- a/arch/sparc/process.hh
+++ b/arch/sparc/process.hh
@@ -29,7 +29,7 @@
#ifndef __SPARC_PROCESS_HH__
#define __SPARC_PROCESS_HH__
-#include "arch/sparc/linux_process.hh"
+#include "arch/sparc/linux/process.hh"
#include "base/loader/object_file.hh"
namespace SparcISA
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 18:27:42 +0000