diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/alpha/isa_traits.hh | 51 | ||||
| -rw-r--r-- | arch/alpha/types.hh | 84 |
2 files changed, 89 insertions, 46 deletions
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 878193881..787546e43 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -32,7 +32,7 @@ namespace LittleEndianGuest {} using namespace LittleEndianGuest; -//#include "arch/alpha/faults.hh" +#include "arch/alpha/types.hh" #include "base/misc.hh" #include "config/full_system.hh" #include "sim/host.hh" @@ -43,8 +43,6 @@ class FastCPU; class FullCPU; class Checkpoint; -#define TARGET_ALPHA - class StaticInst; class StaticInstPtr; @@ -94,10 +92,6 @@ class SyscallReturn { namespace AlphaISA { - typedef uint32_t MachInst; - typedef uint64_t ExtMachInst; - typedef uint8_t RegIndex; - const int NumIntArchRegs = 32; const int NumPALShadowRegs = 8; const int NumFloatArchRegs = 32; @@ -143,28 +137,8 @@ namespace AlphaISA const int NumFloatRegs = NumFloatArchRegs; const int NumMiscRegs = NumMiscArchRegs; - // These enumerate all the registers for dependence tracking. - enum DependenceTags { - // 0..31 are the integer regs 0..31 - // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) - FP_Base_DepTag = 40, - Ctrl_Base_DepTag = 72, - Fpcr_DepTag = 72, // floating point control register - Uniq_DepTag = 73, - Lock_Flag_DepTag = 74, - Lock_Addr_DepTag = 75, - IPR_Base_DepTag = 76 - }; - - typedef uint64_t IntReg; typedef IntReg IntRegFile[NumIntRegs]; - // floating point register file entry type - typedef union { - uint64_t q; - double d; - } FloatReg; - typedef union { uint64_t q[NumFloatRegs]; // integer qword view double d[NumFloatRegs]; // double-precision floating point view @@ -180,16 +154,11 @@ extern const int reg_redir[NumIntRegs]; #if FULL_SYSTEM - typedef uint64_t InternalProcReg; - #include "arch/alpha/isa_fullsys_traits.hh" #else const int NumInternalProcRegs = 0; #endif - - // control register file contents - typedef uint64_t MiscReg; class MiscRegFile { protected: uint64_t fpcr; // floating point condition codes @@ -216,12 +185,14 @@ extern const int reg_redir[NumIntRegs]; #if FULL_SYSTEM protected: + typedef uint64_t InternalProcReg; + InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs private: - MiscReg readIpr(int idx, Fault &fault, ExecContext *xc); + InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc); - Fault setIpr(int idx, uint64_t val, ExecContext *xc); + Fault setIpr(int idx, InternalProcReg val, ExecContext *xc); void copyIprs(ExecContext *xc); #endif @@ -233,12 +204,6 @@ extern const int reg_redir[NumIntRegs]; const int TotalDataRegs = NumIntRegs + NumFloatRegs; - typedef union { - IntReg intreg; - FloatReg fpreg; - MiscReg ctrlreg; - } AnyReg; - struct RegFile { IntRegFile intRegFile; // (signed) integer register file FloatRegFile floatRegFile; // floating point register file @@ -266,12 +231,6 @@ extern const int reg_redir[NumIntRegs]; // return a no-op instruction... used for instruction fetch faults extern const ExtMachInst NoopMachInst; - enum annotes { - ANNOTE_NONE = 0, - // An impossible number for instruction annotations - ITOUCH_ANNOTE = 0xffffffff, - }; - static inline bool isCallerSaveIntegerRegister(unsigned int reg) { panic("register classification not implemented"); return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); diff --git a/arch/alpha/types.hh b/arch/alpha/types.hh new file mode 100644 index 000000000..17d1d262d --- /dev/null +++ b/arch/alpha/types.hh @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_ALPHA_TYPES_HH__ +#define __ARCH_ALPHA_TYPES_HH__ + +#include "config/full_system.hh" +#include "sim/host.hh" + +namespace AlphaISA +{ + + typedef uint32_t MachInst; + typedef uint64_t ExtMachInst; + typedef uint8_t RegIndex; + + // These enumerate all the registers for dependence tracking. + enum DependenceTags { + // 0..31 are the integer regs 0..31 + // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) + FP_Base_DepTag = 40, + Ctrl_Base_DepTag = 72, + Fpcr_DepTag = 72, // floating point control register + Uniq_DepTag = 73, + Lock_Flag_DepTag = 74, + Lock_Addr_DepTag = 75, + IPR_Base_DepTag = 76 + }; + + typedef uint64_t IntReg; + + // floating point register file entry type + typedef union { + uint64_t q; + double d; + } FloatReg; + +#if FULL_SYSTEM + typedef uint64_t InternalProcReg; +#endif + + // control register file contents + typedef uint64_t MiscReg; + + typedef union { + IntReg intreg; + FloatReg fpreg; + MiscReg ctrlreg; + } AnyReg; + + enum annotes { + ANNOTE_NONE = 0, + // An impossible number for instruction annotations + ITOUCH_ANNOTE = 0xffffffff, + }; + +} // namespace AlphaISA + +#endif |