diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/alpha/ev5.cc | 21 | ||||
| -rw-r--r-- | arch/alpha/isa_desc | 20 |
2 files changed, 33 insertions, 8 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index aaa81a58d..551cbdabf 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -237,6 +237,11 @@ ExecContext::readIpr(int idx, Fault &fault) retval = ipr[idx]; break; + case AlphaISA::IPR_CC: + retval |= ipr[idx] & ULL(0xffffffff00000000); + retval |= curTick & ULL(0x00000000ffffffff); + break; + case AlphaISA::IPR_VA: // SFX: unlocks interrupt status registers retval = ipr[idx]; @@ -329,13 +334,25 @@ ExecContext::setIpr(int idx, uint64_t val) case AlphaISA::IPR_PAL_BASE: case AlphaISA::IPR_IC_PERR_STAT: case AlphaISA::IPR_DC_PERR_STAT: - case AlphaISA::IPR_CC_CTL: - case AlphaISA::IPR_CC: case AlphaISA::IPR_PMCTR: // write entire quad w/ no side-effect ipr[idx] = val; break; + case AlphaISA::IPR_CC_CTL: + // This IPR resets the cycle counter. We assume this only + // happens once... let's verify that. + assert(ipr[idx] == 0); + ipr[idx] = 1; + break; + + case AlphaISA::IPR_CC: + // This IPR only writes the upper 64 bits. It's ok to write + // all 64 here since we mask out the lower 32 in rpcc (see + // isa_desc). + ipr[idx] = val; + break; + case AlphaISA::IPR_PALtemp23: // write entire quad w/ no side-effect ipr[idx] = val; diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 41f7388e0..56e7cb31c 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -5,7 +5,7 @@ let {{ global rcs_id - rcs_id = "$Id$" + rcs_id = "$Id: s.isa_desc 1.43 04/02/29 22:41:10-05:00 ehallnor@zazzer.eecs.umich.edu $" }}; @@ -1854,9 +1854,10 @@ decode OPCODE default Unknown::unknown() { 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }}); 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED); 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED); - 0x20: copy_load({{EA = Ra;}}, {{fault = memAccessObj->copySrcTranslate(EA);}}, - IsMemRef, IsLoad, IsCopy); + //0x20: copy_load({{EA = Ra;}}, + // {{memAccessObj->copySrcTranslate(EA);}}, + // IsMemRef, IsLoad, IsCopy); } format LoadOrPrefetch { @@ -1876,9 +1877,10 @@ decode OPCODE default Unknown::unknown() { 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }}); 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }}); 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }}); - 0x24: copy_store({{EA = Rb;}}, {{fault =memAccessObj->copy(EA);}}, - IsMemRef, IsStore, IsCopy); + //0x24: copy_store({{EA = Rb;}}, + // {{memAccessObj->copy(EA);}}, + // IsMemRef, IsStore, IsCopy); } format StoreCond { @@ -2388,7 +2390,13 @@ decode OPCODE default Unknown::unknown() { } format BasicOperate { - 0xc000: rpcc({{ Ra = curTick; }}); + 0xc000: rpcc({{ +#ifdef FULL_SYSTEM + Ra = xc->readIpr(AlphaISA::IPR_CC, fault); +#else + Ra = curTick; +#endif + }}); // All of the barrier instructions below do nothing in // their execute() methods (hence the empty code blocks). |