diff options
Diffstat (limited to 'arch')
50 files changed, 2421 insertions, 1254 deletions
diff --git a/arch/SConscript b/arch/SConscript index d88d10368..99c861568 100644 --- a/arch/SConscript +++ b/arch/SConscript @@ -100,18 +100,12 @@ for hdr in isa_switch_hdrs: # import SCons.Scanner -def ISAScan(): - return SCons.Scanner.Classic("ISAScan", - "$ISASUFFIXES", - "SRCDIR", - '^[ \t]*##[ \t]*include[ \t]*"([^>"]+)"') +isa_scanner = SCons.Scanner.Classic("ISAScan", + [".isa", ".ISA"], + "SRCDIR", + r'^\s*##include\s+"([\w/.-]*)"') -def ISAPath(env, dir, target=None, source=None, a=None): - return (Dir(env['SRCDIR']), Dir('.')) - -iscan = Scanner(function = ISAScan().scan, skeys = [".isa", ".ISA"], - path_function = ISAPath) -env.Append(SCANNERS = iscan) +env.Append(SCANNERS = isa_scanner) # # Now create a Builder object that uses isa_parser.py to generate C++ @@ -138,8 +132,7 @@ def isa_desc_emitter(target, source, env): return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source) # Pieces are in place, so create the builder. -isa_desc_builder = Builder(action='$SOURCES $TARGET.dir $CPU_MODELS', - source_scanner = iscan, +isa_desc_builder = Builder(action='python $SOURCES $TARGET.dir $CPU_MODELS', emitter = isa_desc_emitter) env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc index a782ea330..adc371682 100644 --- a/arch/alpha/arguments.cc +++ b/arch/alpha/arguments.cc @@ -29,7 +29,7 @@ #include "arch/alpha/arguments.hh" #include "arch/alpha/vtophys.hh" #include "cpu/exec_context.hh" -#include "mem/functional/physical.hh" +#include "mem/vport.hh" using namespace AlphaISA; @@ -59,8 +59,10 @@ AlphaArguments::getArg(bool fp) return xc->readIntReg(16 + number); } else { Addr sp = xc->readIntReg(30); - Addr paddr = vtophys(xc, sp + (number-6) * sizeof(uint64_t)); - return xc->getPhysMemPtr()->phys_read_qword(paddr); + VirtualPort *vp = xc->getVirtPort(xc); + uint64_t arg = vp->read<uint64_t>(sp + (number-6) * sizeof(uint64_t)); + xc->delVirtPort(vp); + return arg; } } diff --git a/arch/alpha/arguments.hh b/arch/alpha/arguments.hh index 75346bf58..bd1c6cb1d 100644 --- a/arch/alpha/arguments.hh +++ b/arch/alpha/arguments.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __ARGUMENTS_HH__ -#define __ARGUMENTS_HH__ +#ifndef __ARCH_ALPHA_ARGUMENTS_HH__ +#define __ARCH_ALPHA_ARGUMENTS_HH__ #include <assert.h> @@ -37,6 +37,8 @@ class ExecContext; +namespace AlphaISA { + class AlphaArguments { protected: @@ -135,9 +137,11 @@ class AlphaArguments operator char *() { char *buf = data->alloc(2048); - CopyString(xc, buf, getArg(), 2048); + CopyStringOut(xc, buf, getArg(), 2048); return buf; } }; -#endif // __ARGUMENTS_HH__ +}; // namespace AlphaISA + +#endif // __ARCH_ALPHA_ARGUMENTS_HH__ diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index a5a8851c2..12f7659e6 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -36,7 +36,6 @@ #include "cpu/base.hh" #include "cpu/cpu_exec_context.hh" #include "cpu/exec_context.hh" -#include "cpu/fast/cpu.hh" #include "kern/kernel_stats.hh" #include "sim/debug.hh" #include "sim/sim_events.hh" @@ -575,12 +574,4 @@ CPUExecContext::simPalCheck(int palFunc) return true; } -//Forward instantiation for FastCPU object -template -void AlphaISA::processInterrupts(FastCPU *xc); - -//Forward instantiation for FastCPU object -template -void AlphaISA::zeroRegisters(FastCPU *xc); - #endif // FULL_SYSTEM diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc index e0918da21..c8cb9124e 100644 --- a/arch/alpha/faults.cc +++ b/arch/alpha/faults.cc @@ -30,6 +30,9 @@ #include "cpu/exec_context.hh" #include "cpu/base.hh" #include "base/trace.hh" +#if FULL_SYSTEM +#include "arch/alpha/ev5.hh" +#endif namespace AlphaISA { @@ -70,6 +73,10 @@ FaultName DtbAcvFault::_name = "dfault"; FaultVect DtbAcvFault::_vect = 0x0381; FaultStat DtbAcvFault::_count; +FaultName DtbAlignmentFault::_name = "unalign"; +FaultVect DtbAlignmentFault::_vect = 0x0301; +FaultStat DtbAlignmentFault::_count; + FaultName ItbMissFault::_name = "itbmiss"; FaultVect ItbMissFault::_vect = 0x0181; FaultStat ItbMissFault::_count; @@ -98,6 +105,10 @@ FaultName IntegerOverflowFault::_name = "intover"; FaultVect IntegerOverflowFault::_vect = 0x0501; FaultStat IntegerOverflowFault::_count; +FaultName UnimpFault::_name = "Unimplemented Simulator feature"; +FaultVect UnimpFault::_vect = 0x0001; +FaultStat UnimpFault::_count; + #if FULL_SYSTEM void AlphaFault::invoke(ExecContext * xc) @@ -125,6 +136,50 @@ void ArithmeticFault::invoke(ExecContext * xc) panic("Arithmetic traps are unimplemented!"); } +void DtbFault::invoke(ExecContext * xc) +{ + // Set fault address and flags. Even though we're modeling an + // EV5, we use the EV6 technique of not latching fault registers + // on VPTE loads (instead of locking the registers until IPR_VA is + // read, like the EV5). The EV6 approach is cleaner and seems to + // work with EV5 PAL code, but not the other way around. + if (!xc->misspeculating() + && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { + // set VA register with faulting address + xc->setMiscReg(AlphaISA::IPR_VA, vaddr); + + // set MM_STAT register flags + xc->setMiscReg(AlphaISA::IPR_MM_STAT, + (((EV5::Opcode(xc->getInst()) & 0x3f) << 11) + | ((EV5::Ra(xc->getInst()) & 0x1f) << 6) + | (flags & 0x3f))); + + // set VA_FORM register with faulting formatted address + xc->setMiscReg(AlphaISA::IPR_VA_FORM, + xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); + } + + AlphaFault::invoke(xc); +} + +void ItbFault::invoke(ExecContext * xc) +{ + if (!xc->misspeculating()) { + xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc); + xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, + xc->readMiscReg(AlphaISA::IPR_IVPTBR) | + (AlphaISA::VAddr(pc).vpn() << 3)); + } + + AlphaFault::invoke(xc); +} + +void UnimpFault::invoke(ExecContext * xc) +{ + FaultBase::invoke(xc); + panic("Unimpfault: %s\n", panicStr.c_str()); +} + #endif } // namespace AlphaISA diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh index 1a196cc94..5024c124b 100644 --- a/arch/alpha/faults.hh +++ b/arch/alpha/faults.hh @@ -29,6 +29,7 @@ #ifndef __ALPHA_FAULTS_HH__ #define __ALPHA_FAULTS_HH__ +#include "arch/alpha/isa_traits.hh" #include "sim/faults.hh" // The design of the "name" and "vect" functions is in sim/faults.hh @@ -130,85 +131,167 @@ class InterruptFault : public AlphaFault FaultStat & countStat() {return _count;} }; -class NDtbMissFault : public AlphaFault +class DtbFault : public AlphaFault +{ +#if FULL_SYSTEM + private: + AlphaISA::VAddr vaddr; + uint32_t reqFlags; + uint64_t flags; + public: + DtbFault(AlphaISA::VAddr _vaddr, uint32_t _reqFlags, uint64_t _flags) + : vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags) + { } +#endif + FaultName name() = 0; + FaultVect vect() = 0; + FaultStat & countStat() = 0; +#if FULL_SYSTEM + void invoke(ExecContext * xc); +#endif +}; + +class NDtbMissFault : public DtbFault { private: static FaultName _name; static FaultVect _vect; static FaultStat _count; public: +#if FULL_SYSTEM + NDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags) + : DtbFault(vaddr, reqFlags, flags) + { } +#endif FaultName name() {return _name;} FaultVect vect() {return _vect;} FaultStat & countStat() {return _count;} }; -class PDtbMissFault : public AlphaFault +class PDtbMissFault : public DtbFault { private: static FaultName _name; static FaultVect _vect; static FaultStat _count; public: +#if FULL_SYSTEM + PDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags) + : DtbFault(vaddr, reqFlags, flags) + { } +#endif + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +}; + +class DtbPageFault : public DtbFault +{ + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; + public: +#if FULL_SYSTEM + DtbPageFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags) + : DtbFault(vaddr, reqFlags, flags) + { } +#endif FaultName name() {return _name;} FaultVect vect() {return _vect;} FaultStat & countStat() {return _count;} }; -class DtbPageFault : public AlphaFault +class DtbAcvFault : public DtbFault { private: static FaultName _name; static FaultVect _vect; static FaultStat _count; public: +#if FULL_SYSTEM + DtbAcvFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags) + : DtbFault(vaddr, reqFlags, flags) + { } +#endif FaultName name() {return _name;} FaultVect vect() {return _vect;} FaultStat & countStat() {return _count;} }; -class DtbAcvFault : public AlphaFault +class DtbAlignmentFault : public DtbFault { private: static FaultName _name; static FaultVect _vect; static FaultStat _count; public: +#if FULL_SYSTEM + DtbAlignmentFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags) + : DtbFault(vaddr, reqFlags, flags) + { } +#endif FaultName name() {return _name;} FaultVect vect() {return _vect;} FaultStat & countStat() {return _count;} }; -class ItbMissFault : public AlphaFault +class ItbFault : public AlphaFault +{ + private: + Addr pc; + public: + ItbFault(Addr _pc) + : pc(_pc) + { } + FaultName name() = 0; + FaultVect vect() = 0; + FaultStat & countStat() = 0; +#if FULL_SYSTEM + void invoke(ExecContext * xc); +#endif +}; + +class ItbMissFault : public ItbFault { private: static FaultName _name; static FaultVect _vect; static FaultStat _count; public: + ItbMissFault(Addr pc) + : ItbFault(pc) + { } FaultName name() {return _name;} FaultVect vect() {return _vect;} FaultStat & countStat() {return _count;} }; -class ItbPageFault : public AlphaFault +class ItbPageFault : public ItbFault { private: static FaultName _name; static FaultVect _vect; static FaultStat _count; public: + ItbPageFault(Addr pc) + : ItbFault(pc) + { } FaultName name() {return _name;} FaultVect vect() {return _vect;} FaultStat & countStat() {return _count;} }; -class ItbAcvFault : public AlphaFault +class ItbAcvFault : public ItbFault { private: static FaultName _name; static FaultVect _vect; static FaultStat _count; public: + ItbAcvFault(Addr pc) + : ItbFault(pc) + { } FaultName name() {return _name;} FaultVect vect() {return _vect;} FaultStat & countStat() {return _count;} @@ -264,6 +347,26 @@ class IntegerOverflowFault : public AlphaFault FaultStat & countStat() {return _count;} }; +class UnimpFault : public AlphaFault +{ + private: + std::string panicStr; + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; + public: + UnimpFault(std::string _str) + : panicStr(_str) + { } + + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +#if FULL_SYSTEM + void invoke(ExecContext * xc); +#endif +}; + } // AlphaISA namespace #endif // __FAULTS_HH__ diff --git a/arch/alpha/freebsd/system.cc b/arch/alpha/freebsd/system.cc index e32053afd..3e50fb9a5 100644 --- a/arch/alpha/freebsd/system.cc +++ b/arch/alpha/freebsd/system.cc @@ -37,8 +37,8 @@ #include "arch/alpha/freebsd/system.hh" #include "base/loader/symtab.hh" #include "cpu/exec_context.hh" -#include "mem/functional/memory_control.hh" -#include "mem/functional/physical.hh" +#include "mem/physical.hh" +#include "mem/port.hh" #include "arch/isa_traits.hh" #include "sim/builder.hh" #include "sim/byteswap.hh" @@ -74,20 +74,12 @@ FreebsdAlphaSystem::doCalibrateClocks(ExecContext *xc) { Addr ppc_vaddr = 0; Addr timer_vaddr = 0; - Addr ppc_paddr = 0; - Addr timer_paddr = 0; ppc_vaddr = (Addr)xc->readIntReg(ArgumentReg1); timer_vaddr = (Addr)xc->readIntReg(ArgumentReg2); - ppc_paddr = vtophys(physmem, ppc_vaddr); - timer_paddr = vtophys(physmem, timer_vaddr); - - uint8_t *ppc = physmem->dma_addr(ppc_paddr, sizeof(uint32_t)); - uint8_t *timer = physmem->dma_addr(timer_paddr, sizeof(uint32_t)); - - *(uint32_t *)ppc = htog((uint32_t)Clock::Frequency); - *(uint32_t *)timer = htog((uint32_t)TIMER_FREQUENCY); + virtPort.write(ppc_vaddr, (uint32_t)Clock::Frequency); + virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY); } @@ -102,7 +94,6 @@ FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ExecContext *xc) BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem) Param<Tick> boot_cpu_frequency; - SimObjectParam<MemoryController *> memctrl; SimObjectParam<PhysicalMemory *> physmem; Param<string> kernel; @@ -125,7 +116,6 @@ END_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem) BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem) INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"), - INIT_PARAM(memctrl, "memory controller"), INIT_PARAM(physmem, "phsyical memory"), INIT_PARAM(kernel, "file that contains the kernel code"), INIT_PARAM(console, "file that contains the console code"), @@ -147,7 +137,6 @@ CREATE_SIM_OBJECT(FreebsdAlphaSystem) AlphaSystem::Params *p = new AlphaSystem::Params; p->name = getInstanceName(); p->boot_cpu_frequency = boot_cpu_frequency; - p->memctrl = memctrl; p->physmem = physmem; p->kernel_path = kernel; p->console_path = console; diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa index d4c744fbc..746fe776d 100644 --- a/arch/alpha/isa/main.isa +++ b/arch/alpha/isa/main.isa @@ -418,31 +418,31 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{ }}; // Integer instruction templates, formats, etc. -##include "m5/arch/alpha/isa/int.isa" +##include "int.isa" // Floating-point instruction templates, formats, etc. -##include "m5/arch/alpha/isa/fp.isa" +##include "fp.isa" // Memory instruction templates, formats, etc. -##include "m5/arch/alpha/isa/mem.isa" +##include "mem.isa" // Branch/jump instruction templates, formats, etc. -##include "m5/arch/alpha/isa/branch.isa" +##include "branch.isa" // PAL instruction templates, formats, etc. -##include "m5/arch/alpha/isa/pal.isa" +##include "pal.isa" // Opcdec fault instruction templates, formats, etc. -##include "m5/arch/alpha/isa/opcdec.isa" +##include "opcdec.isa" // Unimplemented instruction templates, formats, etc. -##include "m5/arch/alpha/isa/unimp.isa" +##include "unimp.isa" // Unknown instruction templates, formats, etc. -##include "m5/arch/alpha/isa/unknown.isa" +##include "unknown.isa" // Execution utility functions -##include "m5/arch/alpha/isa/util.isa" +##include "util.isa" // The actual decoder -##include "m5/arch/alpha/isa/decoder.isa" +##include "decoder.isa" diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa index 3c8b4f755..8742d308f 100644 --- a/arch/alpha/isa/mem.isa +++ b/arch/alpha/isa/mem.isa @@ -311,8 +311,7 @@ def template LoadCompleteAcc {{ Fault fault = NoFault; %(fp_enable_check)s; - %(op_src_decl)s; - %(op_dest_decl)s; + %(op_decl)s; memcpy(&Mem, data, sizeof(Mem)); @@ -410,8 +409,7 @@ def template StoreInitiateAcc {{ uint64_t write_result = 0; %(fp_enable_check)s; - %(op_src_decl)s; - %(op_dest_decl)s; + %(op_decl)s; %(op_rd)s; %(ea_code)s; diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 5f8b00c40..65c72115b 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -75,6 +75,11 @@ class SyscallReturn { #endif +#if FULL_SYSTEM +#include "arch/alpha/isa_fullsys_traits.hh" +#endif + + namespace AlphaISA { @@ -83,12 +88,6 @@ using namespace LittleEndianGuest; // redirected register map, really only used for the full system case. extern const int reg_redir[NumIntRegs]; -#if FULL_SYSTEM - -#include "arch/alpha/isa_fullsys_traits.hh" - -#endif - StaticInstPtr decodeInst(ExtMachInst); #if !FULL_SYSTEM @@ -99,12 +98,12 @@ extern const int reg_redir[NumIntRegs]; // return value itself in the standard return value reg (v0). if (return_value.successful()) { // no error - regs->intRegFile[SyscallSuccessReg] = 0; - regs->intRegFile[ReturnValueReg] = return_value.value(); + regs->setIntReg(SyscallSuccessReg, 0); + regs->setIntReg(ReturnValueReg, return_value.value()); } else { // got an error, return details - regs->intRegFile[SyscallSuccessReg] = (IntReg) -1; - regs->intRegFile[ReturnValueReg] = -return_value.value(); + regs->setIntReg(SyscallSuccessReg, (IntReg)-1); + regs->setIntReg(ReturnValueReg, -return_value.value()); } } #endif diff --git a/arch/alpha/linux/system.cc b/arch/alpha/linux/system.cc index f9275d15e..edd2cdaf1 100644 --- a/arch/alpha/linux/system.cc +++ b/arch/alpha/linux/system.cc @@ -46,8 +46,8 @@ #include "dev/platform.hh" #include "kern/linux/printk.hh" #include "kern/linux/events.hh" -#include "mem/functional/memory_control.hh" -#include "mem/functional/physical.hh" +#include "mem/physical.hh" +#include "mem/port.hh" #include "sim/builder.hh" #include "sim/byteswap.hh" @@ -59,7 +59,6 @@ LinuxAlphaSystem::LinuxAlphaSystem(Params *p) : AlphaSystem(p) { Addr addr = 0; - Addr paddr = 0; /** * The symbol swapper_pg_dir marks the beginning of the kernel and @@ -73,25 +72,17 @@ LinuxAlphaSystem::LinuxAlphaSystem(Params *p) * Since we aren't using a bootloader, we have to copy the * kernel arguments directly into the kernel's memory. */ - paddr = vtophys(physmem, CommandLine()); - char *commandline = (char *)physmem->dma_addr(paddr, sizeof(uint64_t)); - if (commandline) - strncpy(commandline, params()->boot_osflags.c_str(), CommandLineSize); + virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(), + CommandLineSize); /** * find the address of the est_cycle_freq variable and insert it * so we don't through the lengthly process of trying to * calculated it by using the PIT, RTC, etc. */ - if (kernelSymtab->findAddress("est_cycle_freq", addr)) { - paddr = vtophys(physmem, addr); - uint8_t *est_cycle_frequency = - physmem->dma_addr(paddr, sizeof(uint64_t)); - - if (est_cycle_frequency) - *(uint64_t *)est_cycle_frequency = - Clock::Frequency / p->boot_cpu_frequency; - } + if (kernelSymtab->findAddress("est_cycle_freq", addr)) + virtPort.write(addr, (uint64_t)(Clock::Frequency / + p->boot_cpu_frequency)); /** @@ -100,16 +91,9 @@ LinuxAlphaSystem::LinuxAlphaSystem(Params *p) * @todo At some point we should change ev5.hh and the palcode to support * 255 ASNs. */ - if (kernelSymtab->findAddress("dp264_mv", addr)) { - paddr = vtophys(physmem, addr); - char *dp264_mv = (char *)physmem->dma_addr(paddr, sizeof(uint64_t)); - - if (dp264_mv) { - *(uint32_t*)(dp264_mv+0x18) = LittleEndianGuest::htog((uint32_t)127); - } else - panic("could not translate dp264_mv addr\n"); - - } else + if (kernelSymtab->findAddress("dp264_mv", addr)) + virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127)); + else panic("could not find dp264_mv\n"); #ifndef NDEBUG @@ -190,15 +174,10 @@ LinuxAlphaSystem::setDelayLoop(ExecContext *xc) { Addr addr = 0; if (kernelSymtab->findAddress("loops_per_jiffy", addr)) { - Addr paddr = vtophys(physmem, addr); - - uint8_t *loops_per_jiffy = - physmem->dma_addr(paddr, sizeof(uint32_t)); - Tick cpuFreq = xc->getCpuPtr()->frequency(); Tick intrFreq = platform->intrFrequency(); - *(uint32_t *)loops_per_jiffy = - (uint32_t)((cpuFreq / intrFreq) * 0.9988); + xc->getVirtPort(xc)->write(addr, + (uint32_t)((cpuFreq / intrFreq) * 0.9988)); } } @@ -224,7 +203,6 @@ LinuxAlphaSystem::PrintThreadInfo::process(ExecContext *xc) BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem) Param<Tick> boot_cpu_frequency; - SimObjectParam<MemoryController *> memctrl; SimObjectParam<PhysicalMemory *> physmem; Param<string> kernel; @@ -247,7 +225,6 @@ END_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem) BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem) INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"), - INIT_PARAM(memctrl, "memory controller"), INIT_PARAM(physmem, "phsyical memory"), INIT_PARAM(kernel, "file that contains the kernel code"), INIT_PARAM(console, "file that contains the console code"), @@ -269,7 +246,6 @@ CREATE_SIM_OBJECT(LinuxAlphaSystem) AlphaSystem::Params *p = new AlphaSystem::Params; p->name = getInstanceName(); p->boot_cpu_frequency = boot_cpu_frequency; - p->memctrl = memctrl; p->physmem = physmem; p->kernel_path = kernel; p->console_path = console; diff --git a/arch/alpha/linux/system.hh b/arch/alpha/linux/system.hh index 035e2a427..0c1fb037e 100644 --- a/arch/alpha/linux/system.hh +++ b/arch/alpha/linux/system.hh @@ -39,7 +39,6 @@ class IdleStartEvent; using namespace AlphaISA; using namespace Linux; -using namespace std; /** * This class contains linux specific system code (Loading, Events, Binning). diff --git a/arch/alpha/regfile.hh b/arch/alpha/regfile.hh index 8a11a8eb6..af01b7829 100644 --- a/arch/alpha/regfile.hh +++ b/arch/alpha/regfile.hh @@ -38,61 +38,38 @@ class ExecContext; namespace AlphaISA { - - typedef IntReg IntRegFile[NumIntRegs]; - - class FloatRegFile + class IntRegFile { protected: - - union { - uint64_t q[NumFloatRegs]; // integer qword view - double d[NumFloatRegs]; // double-precision floating point view - }; + IntReg regs[NumIntRegs]; public: - FloatReg readReg(int floatReg) + IntReg readReg(int intReg) { - return d[floatReg]; + return regs[intReg]; } - FloatReg readReg(int floatReg, int width) + Fault setReg(int intReg, const IntReg &val) { - return readReg(floatReg); - } - - FloatRegBits readRegBits(int floatReg) - { - return q[floatReg]; + regs[intReg] = val; + return NoFault; } - FloatRegBits readRegBits(int floatReg, int width) - { - return readRegBits(floatReg); - } + void serialize(std::ostream &os); - Fault setReg(int floatReg, const FloatReg &val) - { - d[floatReg] = val; - return NoFault; - } + void unserialize(Checkpoint *cp, const std::string §ion); - Fault setReg(int floatReg, const FloatReg &val, int width) - { - return setReg(floatReg, val); - } + }; - Fault setRegBits(int floatReg, const FloatRegBits &val) - { - q[floatReg] = val; - return NoFault; - } + class FloatRegFile + { + public: - Fault setRegBits(int floatReg, const FloatRegBits &val, int width) - { - return setRegBits(floatReg, val); - } + union { + uint64_t q[NumFloatRegs]; // integer qword view + double d[NumFloatRegs]; // double-precision floating point view + }; void serialize(std::ostream &os); @@ -110,17 +87,18 @@ namespace AlphaISA public: MiscReg readReg(int misc_reg); + MiscReg readRegWithEffect(int misc_reg, Fault &fault, + ExecContext *xc); + //These functions should be removed once the simplescalar cpu model //has been replaced. int getInstAsid(); int getDataAsid(); - MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); - Fault setReg(int misc_reg, const MiscReg &val); Fault setRegWithEffect(int misc_reg, const MiscReg &val, - ExecContext *xc); + ExecContext *xc); #if FULL_SYSTEM protected: @@ -136,24 +114,156 @@ namespace AlphaISA friend class RegFile; }; - struct RegFile { - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegs; // control register file + class RegFile { + + protected: Addr pc; // program counter Addr npc; // next-cycle program counter Addr nnpc; + public: + Addr readPC() + { + return pc; + } + + void setPC(Addr val) + { + pc = val; + } + + Addr readNextPC() + { + return npc; + } + + void setNextPC(Addr val) + { + npc = val; + } + + Addr readNextNPC() + { + return nnpc; + } + + void setNextNPC(Addr val) + { + nnpc = val; + } + + protected: + IntRegFile intRegFile; // (signed) integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegFile; // control register file + + public: + #if FULL_SYSTEM int intrflag; // interrupt flag inline int instAsid() - { return miscRegs.getInstAsid(); } + { return miscRegFile.getInstAsid(); } inline int dataAsid() - { return miscRegs.getDataAsid(); } + { return miscRegFile.getDataAsid(); } #endif // FULL_SYSTEM + void clear() + { + bzero(&intRegFile, sizeof(intRegFile)); + bzero(&floatRegFile, sizeof(floatRegFile)); + bzero(&miscRegFile, sizeof(miscRegFile)); + } + + MiscReg readMiscReg(int miscReg) + { + return miscRegFile.readReg(miscReg); + } + + MiscReg readMiscRegWithEffect(int miscReg, + Fault &fault, ExecContext *xc) + { + fault = NoFault; + return miscRegFile.readRegWithEffect(miscReg, fault, xc); + } + + Fault setMiscReg(int miscReg, const MiscReg &val) + { + return miscRegFile.setReg(miscReg, val); + } + + Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, + ExecContext * xc) + { + return miscRegFile.setRegWithEffect(miscReg, val, xc); + } + + FloatReg readFloatReg(int floatReg) + { + return floatRegFile.d[floatReg]; + } + + FloatReg readFloatReg(int floatReg, int width) + { + return readFloatReg(floatReg); + } + + FloatRegBits readFloatRegBits(int floatReg) + { + return floatRegFile.q[floatReg]; + } + + FloatRegBits readFloatRegBits(int floatReg, int width) + { + return readFloatRegBits(floatReg); + } + + Fault setFloatReg(int floatReg, const FloatReg &val) + { + floatRegFile.d[floatReg] = val; + return NoFault; + } + + Fault setFloatReg(int floatReg, const FloatReg &val, int width) + { + return setFloatReg(floatReg, val); + } + + Fault setFloatRegBits(int floatReg, const FloatRegBits &val) + { + floatRegFile.q[floatReg] = val; + return NoFault; + } + + Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width) + { + return setFloatRegBits(floatReg, val); + } + + IntReg readIntReg(int intReg) + { + return intRegFile.readReg(intReg); + } + + Fault setIntReg(int intReg, const IntReg &val) + { + return intRegFile.setReg(intReg, val); + } + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); + + enum ContextParam + { + CONTEXT_PALMODE + }; + + typedef bool ContextVal; + + void changeContext(ContextParam param, ContextVal val) + { + //This would be an alternative place to call/implement + //the swapPALShadow function + } }; void copyRegs(ExecContext *src, ExecContext *dest); diff --git a/arch/alpha/stacktrace.cc b/arch/alpha/stacktrace.cc index 26656ab5c..8691e12dc 100644 --- a/arch/alpha/stacktrace.cc +++ b/arch/alpha/stacktrace.cc @@ -47,23 +47,23 @@ ProcessInfo::ProcessInfo(ExecContext *_xc) if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr)) panic("thread info not compiled into kernel\n"); - thread_info_size = *(int32_t *)vtomem(xc, addr, sizeof(int32_t)); + thread_info_size = gtoh(xc->getVirtPort()->read<int32_t>(addr)); if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr)) panic("thread info not compiled into kernel\n"); - task_struct_size = *(int32_t *)vtomem(xc, addr, sizeof(int32_t)); + task_struct_size = gtoh(xc->getVirtPort()->read<int32_t>(addr)); if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr)) panic("thread info not compiled into kernel\n"); - task_off = *(int32_t *)vtomem(xc, addr, sizeof(int32_t)); + task_off = gtoh(xc->getVirtPort()->read<int32_t>(addr)); if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr)) panic("thread info not compiled into kernel\n"); - pid_off = *(int32_t *)vtomem(xc, addr, sizeof(int32_t)); + pid_off = gtoh(xc->getVirtPort()->read<int32_t>(addr)); if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr)) panic("thread info not compiled into kernel\n"); - name_off = *(int32_t *)vtomem(xc, addr, sizeof(int32_t)); + name_off = gtoh(xc->getVirtPort()->read<int32_t>(addr)); } Addr @@ -73,9 +73,7 @@ ProcessInfo::task(Addr ksp) const if (base == ULL(0xfffffc0000000000)) return 0; - Addr task; - CopyOut(xc, &task, base + task_off, sizeof(task)); - return task; + return gtoh(xc->getVirtPort()->read<Addr>(base + task_off)); } int @@ -85,9 +83,7 @@ ProcessInfo::pid(Addr ksp) const if (!task) return -1; - uint16_t pid; - CopyOut(xc, &pid, task + pid_off, sizeof(pid)); - return pid; + return gtoh(xc->getVirtPort()->read<uint16_t>(task + pid_off)); } string @@ -98,7 +94,7 @@ ProcessInfo::name(Addr ksp) const return "console"; char comm[256]; - CopyString(xc, comm, task + name_off, sizeof(comm)); + CopyStringOut(xc, comm, task + name_off, sizeof(comm)); if (!comm[0]) return "startup"; diff --git a/arch/alpha/system.cc b/arch/alpha/system.cc index 547e89cff..21ffa350b 100644 --- a/arch/alpha/system.cc +++ b/arch/alpha/system.cc @@ -33,8 +33,7 @@ #include "base/loader/object_file.hh" #include "base/loader/symtab.hh" #include "base/trace.hh" -#include "mem/functional/memory_control.hh" -#include "mem/functional/physical.hh" +#include "mem/physical.hh" #include "sim/byteswap.hh" #include "sim/builder.hh" @@ -63,8 +62,8 @@ AlphaSystem::AlphaSystem(Params *p) // Load program sections into memory - pal->loadSections(physmem, true); - console->loadSections(physmem, true); + pal->loadSections(&functionalPort, AlphaISA::LoadAddrMask); + console->loadSections(&functionalPort, AlphaISA::LoadAddrMask); // load symbols if (!console->loadGlobalSymbols(consoleSymtab)) @@ -97,11 +96,8 @@ AlphaSystem::AlphaSystem(Params *p) * others do.) */ if (consoleSymtab->findAddress("env_booted_osflags", addr)) { - Addr paddr = vtophys(physmem, addr); - char *osflags = (char *)physmem->dma_addr(paddr, sizeof(uint32_t)); - - if (osflags) - strcpy(osflags, params()->boot_osflags.c_str()); + virtPort.writeBlob(addr, (uint8_t*)params()->boot_osflags.c_str(), + strlen(params()->boot_osflags.c_str())); } /** @@ -109,14 +105,11 @@ AlphaSystem::AlphaSystem(Params *p) * information to Tsunami. */ if (consoleSymtab->findAddress("m5_rpb", addr)) { - Addr paddr = vtophys(physmem, addr); - char *hwrpb = (char *)physmem->dma_addr(paddr, sizeof(uint64_t)); - - if (!hwrpb) - panic("could not translate hwrpb addr\n"); - - *(uint64_t*)(hwrpb+0x50) = htog(params()->system_type); - *(uint64_t*)(hwrpb+0x58) = htog(params()->system_rev); + uint64_t data; + data = htog(params()->system_type); + virtPort.write(addr, data); + data = htog(params()->system_rev); + virtPort.write(addr, data); } else panic("could not find hwrpb\n"); @@ -172,16 +165,13 @@ AlphaSystem::fixFuncEventAddr(Addr addr) const uint32_t gp_ldah_pattern = (9 << 26) | (29 << 21) | (27 << 16); // lda gp,Y(gp): opcode 8, Ra = 29, rb = 29 const uint32_t gp_lda_pattern = (8 << 26) | (29 << 21) | (29 << 16); - // instruction size - const int sz = sizeof(uint32_t); - Addr paddr = vtophys(physmem, addr); - uint32_t i1 = *(uint32_t *)physmem->dma_addr(paddr, sz); - uint32_t i2 = *(uint32_t *)physmem->dma_addr(paddr+sz, sz); + uint32_t i1 = virtPort.read<uint32_t>(addr); + uint32_t i2 = virtPort.read<uint32_t>(addr + sizeof(AlphaISA::MachInst)); if ((i1 & inst_mask) == gp_ldah_pattern && (i2 & inst_mask) == gp_lda_pattern) { - Addr new_addr = addr + 2*sz; + Addr new_addr = addr + 2* sizeof(AlphaISA::MachInst); DPRINTF(Loader, "fixFuncEventAddr: %p -> %p", addr, new_addr); return new_addr; } else { @@ -195,14 +185,7 @@ AlphaSystem::setAlphaAccess(Addr access) { Addr addr = 0; if (consoleSymtab->findAddress("m5AlphaAccess", addr)) { - Addr paddr = vtophys(physmem, addr); - uint64_t *m5AlphaAccess = - (uint64_t *)physmem->dma_addr(paddr, sizeof(uint64_t)); - - if (!m5AlphaAccess) - panic("could not translate m5AlphaAccess addr\n"); - - *m5AlphaAccess = htog(EV5::Phys2K0Seg(access)); + virtPort.write(addr, htog(EV5::Phys2K0Seg(access))); } else panic("could not find m5AlphaAccess\n"); } @@ -234,7 +217,6 @@ AlphaSystem::unserialize(Checkpoint *cp, const std::string §ion) BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem) Param<Tick> boot_cpu_frequency; - SimObjectParam<MemoryController *> memctrl; SimObjectParam<PhysicalMemory *> physmem; Param<std::string> kernel; @@ -257,7 +239,6 @@ END_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem) BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaSystem) INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"), - INIT_PARAM(memctrl, "memory controller"), INIT_PARAM(physmem, "phsyical memory"), INIT_PARAM(kernel, "file that contains the kernel code"), INIT_PARAM(console, "file that contains the console code"), @@ -279,7 +260,6 @@ CREATE_SIM_OBJECT(AlphaSystem) AlphaSystem::Params *p = new AlphaSystem::Params; p->name = getInstanceName(); p->boot_cpu_frequency = boot_cpu_frequency; - p->memctrl = memctrl; p->physmem = physmem; p->kernel_path = kernel; p->console_path = console; diff --git a/arch/alpha/tlb.cc b/arch/alpha/tlb.cc index e30a8e595..877822c31 100644 --- a/arch/alpha/tlb.cc +++ b/arch/alpha/tlb.cc @@ -93,8 +93,8 @@ AlphaTLB::lookup(Addr vpn, uint8_t asn) const } -void -AlphaTLB::checkCacheability(MemReqPtr &req) +Fault +AlphaTLB::checkCacheability(RequestPtr &req) { // in Alpha, cacheability is controlled by upper-level bits of the // physical address @@ -109,33 +109,24 @@ AlphaTLB::checkCacheability(MemReqPtr &req) #if ALPHA_TLASER - if (req->paddr & PAddrUncachedBit39) { + if (req->getPaddr() & PAddrUncachedBit39) { #else - if (req->paddr & PAddrUncachedBit43) { + if (req->getPaddr() & PAddrUncachedBit43) { #endif // IPR memory space not implemented - if (PAddrIprSpace(req->paddr)) { - if (!req->xc->misspeculating()) { - switch (req->paddr) { - case ULL(0xFFFFF00188): - req->data = 0; - break; - - default: - panic("IPR memory space not implemented! PA=%x\n", - req->paddr); - } - } + if (PAddrIprSpace(req->getPaddr())) { + return new UnimpFault("IPR memory space not implemented!"); } else { // mark request as uncacheable - req->flags |= UNCACHEABLE; + req->setFlags(req->getFlags() | UNCACHEABLE); #if !ALPHA_TLASER // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) - req->paddr &= PAddrUncachedMask; + req->setPaddr(req->getPaddr() & PAddrUncachedMask); #endif } } + return NoFault; } @@ -290,38 +281,24 @@ AlphaITB::regStats() accesses = hits + misses; } -void -AlphaITB::fault(Addr pc, ExecContext *xc) const -{ - if (!xc->misspeculating()) { - xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc); - xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, - xc->readMiscReg(AlphaISA::IPR_IVPTBR) | - (AlphaISA::VAddr(pc).vpn() << 3)); - } -} - Fault -AlphaITB::translate(MemReqPtr &req) const +AlphaITB::translate(RequestPtr &req, ExecContext *xc) const { - ExecContext *xc = req->xc; - - if (AlphaISA::PcPAL(req->vaddr)) { + if (AlphaISA::PcPAL(req->getVaddr())) { // strip off PAL PC marker (lsb is 1) - req->paddr = (req->vaddr & ~3) & PAddrImplMask; + req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); hits++; return NoFault; } - if (req->flags & PHYSICAL) { - req->paddr = req->vaddr; + if (req->getFlags() & PHYSICAL) { + req->setPaddr(req->getVaddr()); } else { // verify that this is a good virtual address - if (!validVirtualAddress(req->vaddr)) { - fault(req->vaddr, req->xc); + if (!validVirtualAddress(req->getVaddr())) { acv++; - return new ItbAcvFault; + return new ItbAcvFault(req->getVaddr()); } @@ -329,50 +306,48 @@ AlphaITB::translate(MemReqPtr &req) const // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 #if ALPHA_TLASER if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && - VAddrSpaceEV5(req->vaddr) == 2) { + VAddrSpaceEV5(req->getVaddr()) == 2) { #else - if (VAddrSpaceEV6(req->vaddr) == 0x7e) { + if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { #endif // only valid in kernel mode if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) != AlphaISA::mode_kernel) { - fault(req->vaddr, req->xc); acv++; - return new ItbAcvFault; + return new ItbAcvFault(req->getVaddr()); } - req->paddr = req->vaddr & PAddrImplMask; + req->setPaddr(req->getVaddr() & PAddrImplMask); #if !ALPHA_TLASER // sign extend the physical address properly - if (req->paddr & PAddrUncachedBit40) - req->paddr |= ULL(0xf0000000000); + if (req->getPaddr() & PAddrUncachedBit40) + req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); else - req->paddr &= ULL(0xffffffffff); + req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); #endif } else { // not a physical address: need to look up pte int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN)); - AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), + AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(), asn); if (!pte) { - fault(req->vaddr, req->xc); misses++; - return new ItbPageFault; + return new ItbPageFault(req->getVaddr()); } - req->paddr = (pte->ppn << AlphaISA::PageShift) + - (AlphaISA::VAddr(req->vaddr).offset() & ~3); + req->setPaddr((pte->ppn << AlphaISA::PageShift) + + (AlphaISA::VAddr(req->getVaddr()).offset() + & ~3)); // check permissions for this access if (!(pte->xre & (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) { // instruction access fault - fault(req->vaddr, req->xc); acv++; - return new ItbAcvFault; + return new ItbAcvFault(req->getVaddr()); } hits++; @@ -380,12 +355,11 @@ AlphaITB::translate(MemReqPtr &req) const } // check that the physical address is ok (catch bad physical addresses) - if (req->paddr & ~PAddrImplMask) + if (req->getPaddr() & ~PAddrImplMask) return genMachineCheckFault(); - checkCacheability(req); + return checkCacheability(req); - return NoFault; } /////////////////////////////////////////////////////////////////////// @@ -465,38 +439,9 @@ AlphaDTB::regStats() accesses = read_accesses + write_accesses; } -void -AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const -{ - ExecContext *xc = req->xc; - AlphaISA::VAddr vaddr = req->vaddr; - - // Set fault address and flags. Even though we're modeling an - // EV5, we use the EV6 technique of not latching fault registers - // on VPTE loads (instead of locking the registers until IPR_VA is - // read, like the EV5). The EV6 approach is cleaner and seems to - // work with EV5 PAL code, but not the other way around. - if (!xc->misspeculating() - && !(req->flags & VPTE) && !(req->flags & NO_FAULT)) { - // set VA register with faulting address - xc->setMiscReg(AlphaISA::IPR_VA, req->vaddr); - - // set MM_STAT register flags - xc->setMiscReg(AlphaISA::IPR_MM_STAT, - (((Opcode(xc->getInst()) & 0x3f) << 11) - | ((Ra(xc->getInst()) & 0x1f) << 6) - | (flags & 0x3f))); - - // set VA_FORM register with faulting formatted address - xc->setMiscReg(AlphaISA::IPR_VA_FORM, - xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); - } -} - Fault -AlphaDTB::translate(MemReqPtr &req, bool write) const +AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const { - ExecContext *xc = req->xc; Addr pc = xc->readPC(); AlphaISA::mode_type mode = @@ -506,58 +451,57 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const /** * Check for alignment faults */ - if (req->vaddr & (req->size - 1)) { - fault(req, write ? MM_STAT_WR_MASK : 0); - DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr, - req->size); - return genAlignmentFault(); + if (req->getVaddr() & (req->getSize() - 1)) { + DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), + req->getSize()); + uint64_t flags = write ? MM_STAT_WR_MASK : 0; + return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); } if (pc & 0x1) { - mode = (req->flags & ALTMODE) ? + mode = (req->getFlags() & ALTMODE) ? (AlphaISA::mode_type)ALT_MODE_AM( xc->readMiscReg(AlphaISA::IPR_ALT_MODE)) : AlphaISA::mode_kernel; } - if (req->flags & PHYSICAL) { - req->paddr = req->vaddr; + if (req->getFlags() & PHYSICAL) { + req->setPaddr(req->getVaddr()); } else { // verify that this is a good virtual address - if (!validVirtualAddress(req->vaddr)) { - fault(req, (write ? MM_STAT_WR_MASK : 0) | - MM_STAT_BAD_VA_MASK | - MM_STAT_ACV_MASK); - + if (!validVirtualAddress(req->getVaddr())) { if (write) { write_acv++; } else { read_acv++; } - return new DtbPageFault; + uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | + MM_STAT_BAD_VA_MASK | + MM_STAT_ACV_MASK; + return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); } // Check for "superpage" mapping #if ALPHA_TLASER if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && - VAddrSpaceEV5(req->vaddr) == 2) { + VAddrSpaceEV5(req->getVaddr()) == 2) { #else - if (VAddrSpaceEV6(req->vaddr) == 0x7e) { + if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { #endif // only valid in kernel mode if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) != AlphaISA::mode_kernel) { - fault(req, ((write ? MM_STAT_WR_MASK : 0) | - MM_STAT_ACV_MASK)); if (write) { write_acv++; } else { read_acv++; } - return new DtbAcvFault; + uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | + MM_STAT_ACV_MASK); + return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); } - req->paddr = req->vaddr & PAddrImplMask; + req->setPaddr(req->getVaddr() & PAddrImplMask); #if !ALPHA_TLASER // sign extend the physical address properly - if (req->paddr & PAddrUncachedBit40) - req->paddr |= ULL(0xf0000000000); + if (req->getPaddr() & PAddrUncachedBit40) + req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); else - req->paddr &= ULL(0xffffffffff); + req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); #endif } else { @@ -569,48 +513,50 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN)); // not a physical address: need to look up pte - AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), + AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(), asn); if (!pte) { // page fault - fault(req, (write ? MM_STAT_WR_MASK : 0) | - MM_STAT_DTB_MISS_MASK); if (write) { write_misses++; } else { read_misses++; } - return (req->flags & VPTE) ? - (Fault)(new PDtbMissFault) : - (Fault)(new NDtbMissFault); + uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | + MM_STAT_DTB_MISS_MASK; + return (req->getFlags() & VPTE) ? + (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), + flags)) : + (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), + flags)); } - req->paddr = (pte->ppn << AlphaISA::PageShift) + - AlphaISA::VAddr(req->vaddr).offset(); + req->setPaddr((pte->ppn << AlphaISA::PageShift) + + AlphaISA::VAddr(req->getVaddr()).offset()); if (write) { if (!(pte->xwe & MODE2MASK(mode))) { // declare the instruction access fault - fault(req, MM_STAT_WR_MASK | - MM_STAT_ACV_MASK | - (pte->fonw ? MM_STAT_FONW_MASK : 0)); write_acv++; - return new DtbPageFault; + uint64_t flags = MM_STAT_WR_MASK | + MM_STAT_ACV_MASK | + (pte->fonw ? MM_STAT_FONW_MASK : 0); + return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); } if (pte->fonw) { - fault(req, MM_STAT_WR_MASK | - MM_STAT_FONW_MASK); write_acv++; - return new DtbPageFault; + uint64_t flags = MM_STAT_WR_MASK | + MM_STAT_FONW_MASK; + return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); } } else { if (!(pte->xre & MODE2MASK(mode))) { - fault(req, MM_STAT_ACV_MASK | - (pte->fonr ? MM_STAT_FONR_MASK : 0)); read_acv++; - return new DtbAcvFault; + uint64_t flags = MM_STAT_ACV_MASK | + (pte->fonr ? MM_STAT_FONR_MASK : 0); + return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); } if (pte->fonr) { - fault(req, MM_STAT_FONR_MASK); read_acv++; - return new DtbPageFault; + uint64_t flags = MM_STAT_FONR_MASK; + return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); } } } @@ -622,12 +568,10 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const } // check that the physical address is ok (catch bad physical addresses) - if (req->paddr & ~PAddrImplMask) + if (req->getPaddr() & ~PAddrImplMask) return genMachineCheckFault(); - checkCacheability(req); - - return NoFault; + return checkCacheability(req); } AlphaISA::PTE & diff --git a/arch/alpha/tlb.hh b/arch/alpha/tlb.hh index 1c299e8b9..f6256020e 100644 --- a/arch/alpha/tlb.hh +++ b/arch/alpha/tlb.hh @@ -35,7 +35,7 @@ #include "arch/alpha/isa_traits.hh" #include "arch/alpha/faults.hh" #include "base/statistics.hh" -#include "mem/mem_req.hh" +#include "mem/request.hh" #include "sim/sim_object.hh" class ExecContext; @@ -73,7 +73,7 @@ class AlphaTLB : public SimObject return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask); } - static void checkCacheability(MemReqPtr &req); + static Fault checkCacheability(RequestPtr &req); // Checkpointing virtual void serialize(std::ostream &os); @@ -88,14 +88,11 @@ class AlphaITB : public AlphaTLB mutable Stats::Scalar<> acv; mutable Stats::Formula accesses; - protected: - void fault(Addr pc, ExecContext *xc) const; - public: AlphaITB(const std::string &name, int size); virtual void regStats(); - Fault translate(MemReqPtr &req) const; + Fault translate(RequestPtr &req, ExecContext *xc) const; }; class AlphaDTB : public AlphaTLB @@ -114,14 +111,11 @@ class AlphaDTB : public AlphaTLB Stats::Formula acv; Stats::Formula accesses; - protected: - void fault(MemReqPtr &req, uint64_t flags) const; - public: AlphaDTB(const std::string &name, int size); virtual void regStats(); - Fault translate(MemReqPtr &req, bool write) const; + Fault translate(RequestPtr &req, ExecContext *xc, bool write) const; }; #endif // __ALPHA_MEMORY_HH__ diff --git a/arch/alpha/tru64/system.cc b/arch/alpha/tru64/system.cc index d09a0c85d..2ad06d679 100644 --- a/arch/alpha/tru64/system.cc +++ b/arch/alpha/tru64/system.cc @@ -35,8 +35,8 @@ #include "cpu/exec_context.hh" #include "kern/tru64/tru64_events.hh" #include "kern/system_events.hh" -#include "mem/functional/memory_control.hh" -#include "mem/functional/physical.hh" +#include "mem/physical.hh" +#include "mem/port.hh" #include "sim/builder.hh" using namespace std; @@ -46,12 +46,7 @@ Tru64AlphaSystem::Tru64AlphaSystem(Tru64AlphaSystem::Params *p) { Addr addr = 0; if (kernelSymtab->findAddress("enable_async_printf", addr)) { - Addr paddr = vtophys(physmem, addr); - uint8_t *enable_async_printf = - physmem->dma_addr(paddr, sizeof(uint32_t)); - - if (enable_async_printf) - *(uint32_t *)enable_async_printf = 0; + virtPort.write(addr, (uint32_t)0); } #ifdef DEBUG @@ -96,7 +91,6 @@ Tru64AlphaSystem::~Tru64AlphaSystem() BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem) Param<Tick> boot_cpu_frequency; - SimObjectParam<MemoryController *> memctrl; SimObjectParam<PhysicalMemory *> physmem; Param<string> kernel; @@ -118,7 +112,6 @@ END_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem) BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem) INIT_PARAM(boot_cpu_frequency, "frequency of the boot cpu"), - INIT_PARAM(memctrl, "memory controller"), INIT_PARAM(physmem, "phsyical memory"), INIT_PARAM(kernel, "file that contains the kernel code"), INIT_PARAM(console, "file that contains the console code"), @@ -139,7 +132,6 @@ CREATE_SIM_OBJECT(Tru64AlphaSystem) AlphaSystem::Params *p = new AlphaSystem::Params; p->name = getInstanceName(); p->boot_cpu_frequency = boot_cpu_frequency; - p->memctrl = memctrl; p->physmem = physmem; p->kernel_path = kernel; p->console_path = console; diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc index 40261426d..41e9b80a3 100644 --- a/arch/alpha/vtophys.cc +++ b/arch/alpha/vtophys.cc @@ -28,33 +28,35 @@ #include <string> +#include "arch/alpha/ev5.hh" #include "arch/alpha/vtophys.hh" +#include "base/chunk_generator.hh" #include "base/trace.hh" #include "cpu/exec_context.hh" -#include "mem/functional/physical.hh" +#include "mem/vport.hh" using namespace std; using namespace AlphaISA; AlphaISA::PageTableEntry -kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr) +AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr) { Addr level1_pte = ptbr + vaddr.level1(); - AlphaISA::PageTableEntry level1 = pmem->phys_read_qword(level1_pte); + AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte); if (!level1.valid()) { DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); return 0; } Addr level2_pte = level1.paddr() + vaddr.level2(); - AlphaISA::PageTableEntry level2 = pmem->phys_read_qword(level2_pte); + AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte); if (!level2.valid()) { DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); return 0; } Addr level3_pte = level2.paddr() + vaddr.level3(); - AlphaISA::PageTableEntry level3 = pmem->phys_read_qword(level3_pte); + AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte); if (!level3.valid()) { DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); return 0; @@ -63,7 +65,7 @@ kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr) } Addr -vtophys(PhysicalMemory *xc, Addr vaddr) +AlphaISA::vtophys(Addr vaddr) { Addr paddr = 0; if (AlphaISA::IsUSeg(vaddr)) @@ -79,7 +81,7 @@ vtophys(PhysicalMemory *xc, Addr vaddr) } Addr -vtophys(ExecContext *xc, Addr addr) +AlphaISA::vtophys(ExecContext *xc, Addr addr) { AlphaISA::VAddr vaddr = addr; Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20); @@ -95,7 +97,7 @@ vtophys(ExecContext *xc, Addr addr) paddr = vaddr; } else { AlphaISA::PageTableEntry pte = - kernel_pte_lookup(xc->getPhysMemPtr(), ptbr, vaddr); + kernel_pte_lookup(xc->getPhysPort(), ptbr, vaddr); if (pte.valid()) paddr = pte.paddr() | vaddr.offset(); } @@ -107,162 +109,54 @@ vtophys(ExecContext *xc, Addr addr) return paddr; } -uint8_t * -ptomem(ExecContext *xc, Addr paddr, size_t len) -{ - return xc->getPhysMemPtr()->dma_addr(paddr, len); -} - -uint8_t * -vtomem(ExecContext *xc, Addr vaddr, size_t len) -{ - Addr paddr = vtophys(xc, vaddr); - return xc->getPhysMemPtr()->dma_addr(paddr, len); -} void -CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen) +AlphaISA::CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen) { - Addr paddr; - char *dmaaddr; - char *dst = (char *)dest; - int len; + uint8_t *dst = (uint8_t *)dest; + VirtualPort *vp = xc->getVirtPort(xc); - paddr = vtophys(xc, src); - len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)), - (int)cplen); - dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, len); - assert(dmaaddr); + vp->readBlob(src, dst, cplen); - memcpy(dst, dmaaddr, len); - if (len == cplen) - return; - - cplen -= len; - dst += len; - src += len; - - while (cplen > AlphaISA::PageBytes) { - paddr = vtophys(xc, src); - dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, - AlphaISA::PageBytes); - assert(dmaaddr); - - memcpy(dst, dmaaddr, AlphaISA::PageBytes); - cplen -= AlphaISA::PageBytes; - dst += AlphaISA::PageBytes; - src += AlphaISA::PageBytes; - } + xc->delVirtPort(vp); - if (cplen > 0) { - paddr = vtophys(xc, src); - dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, cplen); - assert(dmaaddr); - - memcpy(dst, dmaaddr, cplen); - } } void -CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen) +AlphaISA::CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen) { - Addr paddr; - char *dmaaddr; - char *src = (char *)source; - int len; - - paddr = vtophys(xc, dest); - len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)), - (int)cplen); - dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, len); - assert(dmaaddr); - - memcpy(dmaaddr, src, len); - if (len == cplen) - return; - - cplen -= len; - src += len; - dest += len; - - while (cplen > AlphaISA::PageBytes) { - paddr = vtophys(xc, dest); - dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, - AlphaISA::PageBytes); - assert(dmaaddr); - - memcpy(dmaaddr, src, AlphaISA::PageBytes); - cplen -= AlphaISA::PageBytes; - src += AlphaISA::PageBytes; - dest += AlphaISA::PageBytes; - } + uint8_t *src = (uint8_t *)source; + VirtualPort *vp = xc->getVirtPort(xc); - if (cplen > 0) { - paddr = vtophys(xc, dest); - dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, cplen); - assert(dmaaddr); + vp->writeBlob(dest, src, cplen); - memcpy(dmaaddr, src, cplen); - } + xc->delVirtPort(vp); } void -CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen) +AlphaISA::CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen) { - Addr paddr; - char *dmaaddr; - int len; - - paddr = vtophys(xc, vaddr); - len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)), - (int)maxlen); - dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, len); - assert(dmaaddr); - - char *term = (char *)memchr(dmaaddr, 0, len); - if (term) - len = term - dmaaddr + 1; - - memcpy(dst, dmaaddr, len); - - if (term || len == maxlen) - return; - - maxlen -= len; - dst += len; - vaddr += len; - - while (maxlen > AlphaISA::PageBytes) { - paddr = vtophys(xc, vaddr); - dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, - AlphaISA::PageBytes); - assert(dmaaddr); - - char *term = (char *)memchr(dmaaddr, 0, AlphaISA::PageBytes); - len = term ? (term - dmaaddr + 1) : AlphaISA::PageBytes; + int len = 0; + VirtualPort *vp = xc->getVirtPort(xc); - memcpy(dst, dmaaddr, len); - if (term) - return; + do { + vp->readBlob(vaddr++, (uint8_t*)dst++, 1); + len++; + } while (len < maxlen && dst[len] != 0 ); - maxlen -= AlphaISA::PageBytes; - dst += AlphaISA::PageBytes; - vaddr += AlphaISA::PageBytes; - } - - if (maxlen > 0) { - paddr = vtophys(xc, vaddr); - dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, maxlen); - assert(dmaaddr); - - char *term = (char *)memchr(dmaaddr, 0, maxlen); - len = term ? (term - dmaaddr + 1) : maxlen; - - memcpy(dst, dmaaddr, len); + xc->delVirtPort(vp); + dst[len] = 0; +} - maxlen -= len; +void +AlphaISA::CopyStringIn(ExecContext *xc, char *src, Addr vaddr) +{ + VirtualPort *vp = xc->getVirtPort(xc); + for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done(); + gen.next()) + { + vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size()); + src += gen.size(); } - - if (maxlen == 0) - dst[maxlen] = '\0'; + xc->delVirtPort(vp); } diff --git a/arch/alpha/vtophys.hh b/arch/alpha/vtophys.hh index 95430ce77..7ab14bc5b 100644 --- a/arch/alpha/vtophys.hh +++ b/arch/alpha/vtophys.hh @@ -32,19 +32,21 @@ #include "arch/alpha/isa_traits.hh" class ExecContext; -class PhysicalMemory; +class FunctionalPort; -AlphaISA::PageTableEntry -kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr); +namespace AlphaISA { -Addr vtophys(PhysicalMemory *xc, Addr vaddr); +PageTableEntry +kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr); + +Addr vtophys(Addr vaddr); Addr vtophys(ExecContext *xc, Addr vaddr); -uint8_t *vtomem(ExecContext *xc, Addr vaddr, size_t len); -uint8_t *ptomem(ExecContext *xc, Addr paddr, size_t len); void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len); void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len); -void CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen); +void CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen); +void CopyStringIn(ExecContext *xc, char *src, Addr vaddr); +}; #endif // __ARCH_ALPHA_VTOPHYS_H__ diff --git a/arch/isa_parser.py b/arch/isa_parser.py index 3f836ed7e..8279a6a5d 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -1,5 +1,3 @@ -#! /usr/bin/env python - # Copyright (c) 2003-2005 The Regents of The University of Michigan # All rights reserved. # @@ -162,13 +160,12 @@ def t_CPPDIRECTIVE(t): def t_NEWFILE(t): r'^\#\#newfile\s+"[\w/.-]*"' - global fileNameStack - fileNameStack.append((t.value[11:-1], t.lineno)) + fileNameStack.push((t.value[11:-1], t.lineno)) t.lineno = 0 def t_ENDFILE(t): r'^\#\#endfile' - (filename, t.lineno) = fileNameStack.pop() + (old_filename, t.lineno) = fileNameStack.pop() # # The functions t_NEWLINE, t_ignore, and t_error are @@ -698,7 +695,7 @@ def p_error(t): if t: error(t.lineno, "syntax error at '%s'" % t.value) else: - error_bt(0, "unknown syntax error") + error(0, "unknown syntax error", True) # END OF GRAMMAR RULES # @@ -896,6 +893,12 @@ formatStack = Stack(NoFormat()) # The global default case stack. defaultStack = Stack( None ) +# Global stack that tracks current file and line number. +# Each element is a tuple (filename, lineno) that records the +# *current* filename and the line number in the *previous* file where +# it was included. +fileNameStack = Stack() + ################### # Utility functions @@ -932,25 +935,22 @@ def fixPythonIndentation(s): return s # Error handler. Just call exit. Output formatted to work under -# Emacs compile-mode. This function should be called when errors due -# to user input are detected (as opposed to parser bugs). -def error(lineno, string): +# Emacs compile-mode. Optional 'print_traceback' arg, if set to True, +# prints a Python stack backtrace too (can be handy when trying to +# debug the parser itself). +def error(lineno, string, print_traceback = False): spaces = "" for (filename, line) in fileNameStack[0:-1]: - print spaces + "In file included from " + filename + print spaces + "In file included from " + filename + ":" spaces += " " - # Uncomment the following line to get a Python stack backtrace for - # these errors too. Can be handy when trying to debug the parser. - # traceback.print_exc() - sys.exit(spaces + "%s:%d: %s" % (fileNameStack[-1][0], lineno, string)) - -# Like error(), but include a Python stack backtrace (for processing -# Python exceptions). This function should be called for errors that -# appear to be bugs in the parser itself. -def error_bt(lineno, string): - traceback.print_exc() - print >> sys.stderr, "%s:%d: %s" % (input_filename, lineno, string) - sys.exit(1) + # Print a Python stack backtrace if requested. + if (print_traceback): + traceback.print_exc() + if lineno != 0: + line_str = "%d:" % lineno + else: + line_str = "" + sys.exit(spaces + "%s:%s %s" % (fileNameStack[-1][0], line_str, string)) ##################################################################### @@ -1070,7 +1070,7 @@ def buildOperandTypeMap(userDict, lineno): elif size == 64: ctype = 'double' if ctype == '': - error(0, 'Unrecognized type description "%s" in userDict') + error(lineno, 'Unrecognized type description "%s" in userDict') operandTypeMap[ext] = (size, ctype, is_signed) # @@ -1618,13 +1618,27 @@ opClassRE = re.compile(r'.*Op|No_OpClass') class InstObjParams: def __init__(self, mnem, class_name, base_class = '', - code_block = None, opt_args = []): + code = None, opt_args = [], *extras): self.mnemonic = mnem self.class_name = class_name self.base_class = base_class - if code_block: - for code_attr in code_block.__dict__.keys(): - setattr(self, code_attr, getattr(code_block, code_attr)) + if code: + #If the user already made a CodeBlock, pick the parts from it + if isinstance(code, CodeBlock): + origCode = code.orig_code + codeBlock = code + else: + origCode = code + codeBlock = CodeBlock(code) + compositeCode = '\n'.join([origCode] + + [pair[1] for pair in extras]) + compositeBlock = CodeBlock(compositeCode) + for code_attr in compositeBlock.__dict__.keys(): + setattr(self, code_attr, getattr(compositeBlock, code_attr)) + for (key, snippet) in extras: + setattr(self, key, CodeBlock(snippet).code) + self.code = codeBlock.code + self.orig_code = origCode else: self.constructor = '' self.flags = [] @@ -1701,47 +1715,47 @@ def update_if_needed(file, contents): f.write(contents) f.close() -# This regular expression matches include directives +# This regular expression matches '##include' directives includeRE = re.compile(r'^\s*##include\s+"(?P<filename>[\w/.-]*)".*$', re.MULTILINE) -def preprocess_isa_desc(isa_desc): +# Function to replace a matched '##include' directive with the +# contents of the specified file (with nested ##includes replaced +# recursively). 'matchobj' is an re match object (from a match of +# includeRE) and 'dirname' is the directory relative to which the file +# path should be resolved. +def replace_include(matchobj, dirname): + fname = matchobj.group('filename') + full_fname = os.path.normpath(os.path.join(dirname, fname)) + contents = '##newfile "%s"\n%s\n##endfile\n' % \ + (full_fname, read_and_flatten(full_fname)) + return contents + +# Read a file and recursively flatten nested '##include' files. +def read_and_flatten(filename): + current_dir = os.path.dirname(filename) + try: + contents = open(filename).read() + except IOError: + error(0, 'Error including file "%s"' % filename) + fileNameStack.push((filename, 0)) # Find any includes and include them - pos = 0 - while 1: - m = includeRE.search(isa_desc, pos) - if not m: - break - filename = m.group('filename') - print 'Including file "%s"' % filename - try: - isa_desc = isa_desc[:m.start()] + \ - '##newfile "' + filename + '"\n' + \ - open(filename).read() + \ - '##endfile\n' + \ - isa_desc[m.end():] - except IOError: - error(0, 'Error including file "%s"' % (filename)) - pos = m.start() - return isa_desc + contents = includeRE.sub(lambda m: replace_include(m, current_dir), + contents) + fileNameStack.pop() + return contents # # Read in and parse the ISA description. # def parse_isa_desc(isa_desc_file, output_dir): - # set a global var for the input filename... used in error messages - global input_filename - input_filename = isa_desc_file - global fileNameStack - fileNameStack = [(input_filename, 1)] - - # Suck the ISA description file in. - input = open(isa_desc_file) - isa_desc = input.read() - input.close() - - # Perform Preprocessing - isa_desc = preprocess_isa_desc(isa_desc) + # Read file and (recursively) all included files into a string. + # PLY requires that the input be in a single string so we have to + # do this up front. + isa_desc = read_and_flatten(isa_desc_file) + + # Initialize filename stack with outer file. + fileNameStack.push((isa_desc_file, 0)) # Parse it. (isa_name, namespace, global_code, namespace_code) = yacc.parse(isa_desc) diff --git a/arch/mips/faults.cc b/arch/mips/faults.cc index 1b31dfa69..a31856f07 100644 --- a/arch/mips/faults.cc +++ b/arch/mips/faults.cc @@ -98,6 +98,10 @@ FaultName IntegerOverflowFault::_name = "intover"; FaultVect IntegerOverflowFault::_vect = 0x0501; FaultStat IntegerOverflowFault::_count; +FaultName UnimpFault::_name = "Unimplemented Simulator feature"; +FaultVect UnimpFault::_vect = 0x0001; +FaultStat UnimpFault::_count; + #if FULL_SYSTEM void MipsFault::invoke(ExecContext * xc) @@ -125,6 +129,12 @@ void ArithmeticFault::invoke(ExecContext * xc) panic("Arithmetic traps are unimplemented!"); } +void UnimpFault::invoke(ExecContext * xc) +{ + FaultBase::invoke(xc); + panic("Unimpfault: %s\n", panicStr.c_str()); +} + #endif } // namespace MipsISA diff --git a/arch/mips/faults.hh b/arch/mips/faults.hh index 0bdabe29e..b0d228090 100644 --- a/arch/mips/faults.hh +++ b/arch/mips/faults.hh @@ -264,6 +264,26 @@ class IntegerOverflowFault : public MipsFault FaultStat & countStat() {return _count;} }; +class UnimpFault : public MipsFault +{ + private: + std::string panicStr; + static FaultName _name; + static FaultVect _vect; + static FaultStat _count; + public: + UnimpFault(std::string _str) + : panicStr(_str) + { } + + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & countStat() {return _count;} +#if FULL_SYSTEM + void invoke(ExecContext * xc); +#endif +}; + } // MipsISA namespace #endif // __FAULTS_HH__ diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa index 139a6d876..9ed9651d2 100644 --- a/arch/mips/isa/base.isa +++ b/arch/mips/isa/base.isa @@ -9,8 +9,6 @@ output header {{ #define R31 31 -#include "arch/mips/faults.hh" -#include "arch/mips/isa_traits.hh" using namespace MipsISA; diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa deleted file mode 100644 index f7a9e4ce2..000000000 --- a/arch/mips/isa/formats.isa +++ /dev/null @@ -1,35 +0,0 @@ -// -*- mode:c++ -*- - -//Templates from this format are used later -//Include the basic format -##include "m5/arch/mips/isa/formats/basic.isa" - -//Include the basic format -##include "m5/arch/mips/isa/formats/noop.isa" - -//Include utility formats/functions -##include "m5/arch/mips/isa/formats/util.isa" - -//Include the cop0 formats -##include "m5/arch/mips/isa/formats/cop0.isa" - -//Include the integer formats -##include "m5/arch/mips/isa/formats/int.isa" - -//Include the floatOp format -##include "m5/arch/mips/isa/formats/fp.isa" - -//Include the mem format -##include "m5/arch/mips/isa/formats/mem.isa" - -//Include the trap format -##include "m5/arch/mips/isa/formats/trap.isa" - -//Include the branch format -##include "m5/arch/mips/isa/formats/branch.isa" - -//Include the noop format -##include "m5/arch/mips/isa/formats/unimp.isa" - -//Include the noop format -##include "m5/arch/mips/isa/formats/unknown.isa" diff --git a/arch/mips/isa/formats/formats.isa b/arch/mips/isa/formats/formats.isa new file mode 100644 index 000000000..7d493ffae --- /dev/null +++ b/arch/mips/isa/formats/formats.isa @@ -0,0 +1,35 @@ +// -*- mode:c++ -*- + +//Templates from this format are used later +//Include the basic format +##include "basic.isa" + +//Include the basic format +##include "noop.isa" + +//Include utility functions +##include "util.isa" + +//Include the cop0 formats +##include "cop0.isa" + +//Include the integer formats +##include "int.isa" + +//Include the floatOp format +##include "fp.isa" + +//Include the mem format +##include "mem.isa" + +//Include the trap format +##include "trap.isa" + +//Include the branch format +##include "branch.isa" + +//Include the noop format +##include "unimp.isa" + +//Include the noop format +##include "unknown.isa" diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa index a42976331..df1dca4e1 100644 --- a/arch/mips/isa/formats/mem.isa +++ b/arch/mips/isa/formats/mem.isa @@ -199,8 +199,23 @@ def template LoadMemAccExecute {{ %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { + Addr EA; Fault fault = NoFault; - //Fill in Code for Out-of-Order CPUs + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + EA = xc->getEA(); + + if (fault == NoFault) { + fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); + %(code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + } + return fault; } }}; @@ -236,8 +251,18 @@ def template LoadInitiateAcc {{ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { + Addr EA; Fault fault = NoFault; - //Fill in Code for Out-of-Order CPUs + + %(fp_enable_check)s; + %(op_src_decl)s; + %(op_rd)s; + %(ea_code)s; + + if (fault == NoFault) { + fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); + } + return fault; } }}; @@ -249,7 +274,20 @@ def template LoadCompleteAcc {{ Trace::InstRecord *traceData) const { Fault fault = NoFault; - //Fill in Code for Out-of-Order CPUs + + %(fp_enable_check)s; + %(op_decl)s; + + memcpy(&Mem, data, sizeof(Mem)); + + if (fault == NoFault) { + %(memacc_code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + } + return fault; } }}; @@ -260,8 +298,33 @@ def template StoreMemAccExecute {{ %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { + Addr EA; Fault fault = NoFault; - //Fill in Code for Out-of-Order CPUs + uint64_t write_result = 0; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + EA = xc->getEA(); + + if (fault == NoFault) { + %(code)s; + } + + if (fault == NoFault) { + fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + memAccessFlags, &write_result); + if (traceData) { traceData->setData(Mem); } + } + + if (fault == NoFault) { + %(postacc_code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + } + return fault; } }}; @@ -306,8 +369,25 @@ def template StoreInitiateAcc {{ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { + Addr EA; Fault fault = NoFault; - //Fill in Code for Out-of-Order CPUs + uint64_t write_result = 0; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + + if (fault == NoFault) { + %(memacc_code)s; + } + + if (fault == NoFault) { + fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + memAccessFlags, &write_result); + if (traceData) { traceData->setData(Mem); } + } + return fault; } }}; @@ -319,7 +399,21 @@ def template StoreCompleteAcc {{ Trace::InstRecord *traceData) const { Fault fault = NoFault; - //Fill in Code for Out-of-Order CPUs + uint64_t write_result = 0; + + %(fp_enable_check)s; + %(op_dest_decl)s; + + memcpy(&write_result, data, sizeof(write_result)); + + if (fault == NoFault) { + %(postacc_code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + } + return fault; } }}; diff --git a/arch/mips/isa/includes.isa b/arch/mips/isa/includes.isa index b81c4eda2..9c370fbe3 100644 --- a/arch/mips/isa/includes.isa +++ b/arch/mips/isa/includes.isa @@ -17,6 +17,8 @@ output decoder {{ #include "base/cprintf.hh" #include "base/loader/symtab.hh" #include "cpu/exec_context.hh" // for Jump::branchTarget() +#include "arch/mips/faults.hh" +#include "arch/mips/isa_traits.hh" #include <math.h> #if defined(linux) @@ -27,6 +29,7 @@ using namespace MipsISA; }}; output exec {{ +#include "arch/mips/faults.hh" #include "arch/mips/isa_traits.hh" #include <math.h> #if defined(linux) diff --git a/arch/mips/isa/main.isa b/arch/mips/isa/main.isa index 411e398b4..01d81323e 100644 --- a/arch/mips/isa/main.isa +++ b/arch/mips/isa/main.isa @@ -26,7 +26,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -##include "m5/arch/mips/isa/includes.isa" +##include "includes.isa" //////////////////////////////////////////////////////////////////// // @@ -37,16 +37,16 @@ namespace MipsISA; //Include the bitfield definitions -##include "m5/arch/mips/isa/bitfields.isa" +##include "bitfields.isa" //Include the operand_types and operand definitions -##include "m5/arch/mips/isa/operands.isa" +##include "operands.isa" //Include the base class for mips instructions, and some support code -##include "m5/arch/mips/isa/base.isa" +##include "base.isa" //Include the definitions for the instruction formats -##include "m5/arch/mips/isa/formats.isa" +##include "formats/formats.isa" //Include the decoder definition -##include "m5/arch/mips/isa/decoder.isa" +##include "decoder.isa" diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc index 849d3311d..c6cfb2a0f 100644 --- a/arch/mips/isa_traits.cc +++ b/arch/mips/isa_traits.cc @@ -275,9 +275,21 @@ RoundPage(Addr addr) { return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); } void +IntRegFile::serialize(std::ostream &os) +{ + SERIALIZE_ARRAY(regs, NumIntRegs); +} + +void +IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) +{ + UNSERIALIZE_ARRAY(regs, NumIntRegs); +} + +void RegFile::serialize(std::ostream &os) { - SERIALIZE_ARRAY(intRegFile, NumIntRegs); + intRegFile.serialize(os); //SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs); //SERIALIZE_SCALAR(miscRegs.fpcr); //SERIALIZE_SCALAR(miscRegs.uniq); @@ -298,7 +310,7 @@ RegFile::serialize(std::ostream &os) void RegFile::unserialize(Checkpoint *cp, const std::string §ion) { - UNSERIALIZE_ARRAY(intRegFile, NumIntRegs); + intRegFile.unserialize(cp, section); //UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs); //UNSERIALIZE_SCALAR(miscRegs.fpcr); //UNSERIALIZE_SCALAR(miscRegs.uniq); diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh index fd6f6e5c7..83b021540 100644 --- a/arch/mips/isa_traits.hh +++ b/arch/mips/isa_traits.hh @@ -43,7 +43,6 @@ class Checkpoint; class ExecContext; namespace LittleEndianGuest {}; -using namespace LittleEndianGuest; #define TARGET_MIPS @@ -92,6 +91,8 @@ class SyscallReturn { namespace MipsISA { + using namespace LittleEndianGuest; + typedef uint32_t MachInst; typedef uint32_t MachInst; typedef uint64_t ExtMachInst; @@ -515,6 +516,13 @@ extern const Addr PageOffset; void createCP0Regs(); void coldReset(); + + typedef int ContextParam; + typedef int ContextVal; + + void changeContext(ContextParam param, ContextVal val) + { + } }; StaticInstPtr decodeInst(ExtMachInst); diff --git a/arch/sparc/faults.cc b/arch/sparc/faults.cc index 9831a7679..e83bba800 100644 --- a/arch/sparc/faults.cc +++ b/arch/sparc/faults.cc @@ -179,13 +179,13 @@ TrapType AsyncDataError::_trapType = 0x040; FaultPriority AsyncDataError::_priority = 2; FaultStat AsyncDataError::_count; -//The enumerated faults - FaultName CleanWindow::_name = "clean_win"; -TrapType CleanWindow::_baseTrapType = 0x024; +TrapType CleanWindow::_trapType = 0x024; FaultPriority CleanWindow::_priority = 10; FaultStat CleanWindow::_count; +//The enumerated faults + FaultName InterruptLevelN::_name = "interrupt_n"; TrapType InterruptLevelN::_baseTrapType = 0x041; FaultStat InterruptLevelN::_count; @@ -215,7 +215,10 @@ TrapType TrapInstruction::_baseTrapType = 0x100; FaultPriority TrapInstruction::_priority = 16; FaultStat TrapInstruction::_count; - +FaultName UnimpFault::_name = "Unimplemented Simulator feature"; +TrapType UnimpFault::_trapType = 0x000; +FaultPriority UnimpFault::_priority = 0; +FaultStat UnimpFault::_count; #if FULL_SYSTEM @@ -242,6 +245,12 @@ void SparcFault::invoke(ExecContext * xc) xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/ } +void UnimpFault::invoke(ExecContext * xc) +{ + panic("Unimpfault: %s\n", panicStr.c_str()); +} + + #endif } // namespace SparcISA diff --git a/arch/sparc/faults.hh b/arch/sparc/faults.hh index 985407c26..87de8daaa 100644 --- a/arch/sparc/faults.hh +++ b/arch/sparc/faults.hh @@ -468,31 +468,30 @@ class AsyncDataError : public SparcFault FaultStat & countStat() {return _count;} }; -class EnumeratedFault : public SparcFault -{ - protected: - uint32_t _n; - virtual TrapType baseTrapType() = 0; - public: - EnumeratedFault(uint32_t n) : SparcFault() {_n = n;} - TrapType trapType() {return baseTrapType() + _n;} -}; - -class CleanWindow : public EnumeratedFault +class CleanWindow : public SparcFault { private: static FaultName _name; - static TrapType _baseTrapType; + static TrapType _trapType; static FaultPriority _priority; static FaultStat _count; - TrapType baseTrapType() {return _baseTrapType;} public: - CleanWindow(uint32_t n) : EnumeratedFault(n) {;} FaultName name() {return _name;} + TrapType trapType() {return _trapType;} FaultPriority priority() {return _priority;} FaultStat & countStat() {return _count;} }; +class EnumeratedFault : public SparcFault +{ + protected: + uint32_t _n; + virtual TrapType baseTrapType() = 0; + public: + EnumeratedFault(uint32_t n) : SparcFault() {_n = n;} + TrapType trapType() {return baseTrapType() + _n;} +}; + class InterruptLevelN : public EnumeratedFault { private: @@ -582,6 +581,29 @@ class TrapInstruction : public EnumeratedFault FaultStat & countStat() {return _count;} }; +class UnimpFault : public SparcFault +{ + private: + static FaultName _name; + static TrapType _trapType; + static FaultPriority _priority; + static FaultStat _count; + std::string panicStr; + public: + UnimpFault(std::string _str) + : panicStr(_str) + { } + + FaultName name() {return _name;} + TrapType trapType() {return _trapType;} + FaultPriority priority() {return _priority;} + FaultStat & countStat() {return _count;} +#if FULL_SYSTEM + void invoke(ExecContext * xc); +#endif +}; + + } // SparcISA namespace #endif // __FAULTS_HH__ diff --git a/arch/sparc/isa/base.isa b/arch/sparc/isa/base.isa index 4721f728b..434426ffa 100644 --- a/arch/sparc/isa/base.isa +++ b/arch/sparc/isa/base.isa @@ -57,6 +57,12 @@ output header {{ }; bool passesCondition(uint32_t codes, uint32_t condition); + + inline int64_t sign_ext(uint64_t data, int origWidth) + { + int shiftAmount = 64 - origWidth; + return (((int64_t)data) << shiftAmount) >> shiftAmount; + } }}; def template ROrImmDecode {{ @@ -68,28 +74,46 @@ def template ROrImmDecode {{ let {{ def splitOutImm(code): - matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>d{0,2})') + matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)') rOrImmMatch = matcher.search(code) if (rOrImmMatch == None): - return (False, CodeBlock(code), None, '', '') - rString = matcher.sub(r'(?P=rNum)', rOrImmMatch.string) - iString = matcher.sub(r'(?P=iNum)', rOrImmMatch.string) + return (False, code, '', '', '') + rString = rOrImmMatch.group("rNum") + iString = rOrImmMatch.group("iNum") orig_code = code - code = matcher.sub(r'Rs(?P<rNum>)', orig_code) + code = matcher.sub('Rs' + rOrImmMatch.group("rNum"), orig_code) imm_code = matcher.sub('imm', orig_code) - return (True, CodeBlock(code), CodeBlock(imm_code), rString, iString) + return (True, code, imm_code, rString, iString) }}; output decoder {{ + inline void printMnemonic(std::ostream &os, const char * mnemonic) + { + ccprintf(os, "\t%s ", mnemonic); + } + void SparcStaticInst::printReg(std::ostream &os, int reg) const { - if (reg < FP_Base_DepTag) { - ccprintf(os, "r%d", reg); - } + const int MaxGlobal = 8; + const int MaxOutput = 16; + const int MaxLocal = 24; + const int MaxInput = 32; + if (reg == FramePointerReg) + ccprintf(os, "%%fp"); + else if (reg == StackPointerReg) + ccprintf(os, "%%sp"); + else if(reg < MaxGlobal) + ccprintf(os, "%%g%d", reg); + else if(reg < MaxOutput) + ccprintf(os, "%%o%d", reg - MaxGlobal); + else if(reg < MaxLocal) + ccprintf(os, "%%l%d", reg - MaxOutput); + else if(reg < MaxInput) + ccprintf(os, "%%i%d", reg - MaxLocal); else { - ccprintf(os, "f%d", reg - FP_Base_DepTag); + ccprintf(os, "%%f%d", reg - FP_Base_DepTag); } } @@ -98,7 +122,7 @@ output decoder {{ { std::stringstream ss; - ccprintf(ss, "%-10s ", mnemonic); + printMnemonic(ss, mnemonic); // just print the first two source regs... if there's // a third one, it's a read-modify-write dest (Rc), diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa index a1bbf8984..b4084518c 100644 --- a/arch/sparc/isa/decoder.isa +++ b/arch/sparc/isa/decoder.isa @@ -7,61 +7,64 @@ decode OP default Unknown::unknown() { 0x0: decode OP2 { - format Branch + //Throw an illegal instruction acception + 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); + 0x1: decode BPCC { - //Throw an illegal instruction acception - 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); - 0x1: decode BPCC + format Branch19 { 0x0: bpcci({{ if(passesCondition(CcrIcc, COND2)) - ;//branchHere + NNPC = xc->readPC() + disp; }}); 0x2: bpccx({{ if(passesCondition(CcrXcc, COND2)) - ;//branchHere + NNPC = xc->readPC() + disp; }}); } - 0x2: bicc({{ - if(passesCondition(CcrIcc, COND2)) - ;//branchHere - }}); - 0x3: decode RCOND2 + } + 0x2: Branch22::bicc({{ + if(passesCondition(CcrIcc, COND2)) + NNPC = xc->readPC() + disp; + }}); + 0x3: decode RCOND2 + { + format BranchSplit { 0x1: bpreq({{ if(Rs1 == 0) - ;//branchHere + NNPC = xc->readPC() + disp; }}); 0x2: bprle({{ if(Rs1 <= 0) - ;//branchHere + NNPC = xc->readPC() + disp; }}); 0x3: bprl({{ if(Rs1 < 0) - ;//branchHere + NNPC = xc->readPC() + disp; }}); 0x5: bprne({{ if(Rs1 != 0) - ;//branchHere + NNPC = xc->readPC() + disp; }}); 0x6: bprg({{ if(Rs1 > 0) - ;//branchHere + NNPC = xc->readPC() + disp; }}); 0x7: bprge({{ if(Rs1 >= 0) - ;//branchHere + NNPC = xc->readPC() + disp; }}); } - //SETHI (or NOP if rd == 0 and imm == 0) - 0x4: IntOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}}); - 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); - 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); } + //SETHI (or NOP if rd == 0 and imm == 0) + 0x4: SetHi::sethi({{Rd = imm;}}); + 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); + 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); } - 0x1: Branch::call({{ - //branch here - Rd = xc->readPC(); + 0x1: Branch30::call({{ + R15 = xc->readPC(); + NNPC = R15 + disp; }}); 0x2: decode OP3 { format IntOp { @@ -69,74 +72,73 @@ decode OP default Unknown::unknown() 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}}); 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}}); 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}}); - 0x04: sub({{Rd = Rs1.sdw + (~Rs2_or_imm)+1;}}); - 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm;}}); - 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm;}}); - 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm);}}); - 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm + CcrIccC;}}); - 0x09: mulx({{Rd = Rs1 * Rs2_or_imm;}}); + 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); + 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}}); + 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}}); + 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}}); + 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + CcrIccC;}}); + 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}}); 0x0A: umul({{ - Rd = Rs1.udw<31:0> * Rs2_or_imm<31:0>; + Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; YValue = Rd<63:32>; }}); 0x0B: smul({{ - Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm<31:0>; + Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; YValue = Rd.sdw; }}); - 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm) + 1 + CcrIccC;}}); + 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + CcrIccC;}}); 0x0D: udivx({{ - if(val2 == 0) fault = new DivisionByZero; - else Rd.udw = Rs1.udw / Rs2_or_imm; + if(Rs2_or_imm13 == 0) fault = new DivisionByZero; + else Rd.udw = Rs1.udw / Rs2_or_imm13; }}); 0x0E: udiv({{ - uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>); - if(Rs2_or_imm.udw == 0) fault = new DivisionByZero; + if(Rs2_or_imm13 == 0) fault = new DivisionByZero; else { - Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm.udw; + Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; if(Rd.udw >> 32 != 0) Rd.udw = 0xFFFFFFFF; } }}); 0x0F: sdiv({{ - if(val2 == 0) + if(Rs2_or_imm13 == 0) fault = new DivisionByZero; else { - Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm; + Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm13; if(Rd.udw<63:31> != 0) Rd.udw = 0x7FFFFFFF; else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) Rd.udw = 0xFFFFFFFF80000000; } - }});//SDIV + }}); } format IntOpCc { 0x10: addcc({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 + val2;}}, {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - );//ADDcc + ); 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 0x14: subcc({{ - int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 - val2;}}, - {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}}, + {{((Rs1 & 0xFFFFFFFF - val2 & 0xFFFFFFFF) >> 31)}}, {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, - {{((Rs1 >> 1) + (~val2) >> 1) + + {{(((Rs1 >> 1) + (~val2) >> 1) + ((Rs1 | ~val2) & 0x1))<63:>}}, {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} - );//SUBcc + ); 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 0x18: addccc({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; int64_t carryin = CcrIccC; Rd = resTemp = Rs1 + val2 + carryin;}}, {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 @@ -145,83 +147,84 @@ decode OP default Unknown::unknown() {{((Rs1 >> 1) + (val2 >> 1) + ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - );//ADDCcc + ); 0x1A: umulcc({{ - uint64_t resTemp, val2 = (I ? SIMM13 : Rs2); + uint64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; YValue = resTemp<63:32>;}}, - {{0}},{{0}},{{0}},{{0}});//UMULcc + {{0}},{{0}},{{0}},{{0}}); 0x1B: smulcc({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>; - YValue = resTemp<63:32>;}} - ,{{0}},{{0}},{{0}},{{0}});//SMULcc + YValue = resTemp<63:32>;}}, + {{0}},{{0}},{{0}},{{0}}); 0x1C: subccc({{ - int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; int64_t carryin = CcrIccC; Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}}, {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, - {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}}, + {{(((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}}, {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} - );//SUBCcc + ); 0x1D: udivxcc({{ - uint64_t val2 = (I ? SIMM13 : Rs2.udw); - if(val2 == 0) fault = new DivisionByZero; - else Rd.udw = Rs1.udw / val2;}} - ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc + if(Rs2_or_imm13 == 0) fault = new DivisionByZero; + else Rd = Rs1.udw / Rs2_or_imm13;}} + ,{{0}},{{0}},{{0}},{{0}}); 0x1E: udivcc({{ - uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>); + uint32_t resTemp, val2 = Rs2_or_imm13; + int32_t overflow; if(val2 == 0) fault = new DivisionByZero; else { resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2; - int32_t overflow = (resTemp<63:32> != 0); - if(overflow) rd.udw = resTemp = 0xFFFFFFFF; - else rd.udw = resTemp; + overflow = (resTemp<63:32> != 0); + if(overflow) Rd = resTemp = 0xFFFFFFFF; + else Rd = resTemp; } }}, {{0}}, {{overflow}}, {{0}}, {{0}} - );//UDIVcc + ); 0x1F: sdivcc({{ - int32_t resTemp, val2 = (I ? SIMM13 : Rs2.sdw<31:0>); + int32_t resTemp, val2 = Rs2_or_imm13; + int32_t overflow, underflow; if(val2 == 0) fault = new DivisionByZero; else { - Rd.sdw = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2; - int32_t overflow = (resTemp<63:31> != 0); - int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); - if(overflow) rd.udw = resTemp = 0x7FFFFFFF; - else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000; - else rd.udw = resTemp; + Rd = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2; + overflow = (resTemp<63:31> != 0); + underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); + if(overflow) Rd = resTemp = 0x7FFFFFFF; + else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000; + else Rd = resTemp; } }}, {{0}}, {{overflow || underflow}}, {{0}}, {{0}} - );//SDIVcc + ); 0x20: taddcc({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 + val2; int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, {{overflow}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - );//TADDcc + ); 0x21: tsubcc({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 + val2; int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, - {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, + {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, {{overflow}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - );//TSUBcc + ); 0x22: taddcctv({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 + val2; int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); if(overflow) fault = new TagOverflow;}}, @@ -229,9 +232,9 @@ decode OP default Unknown::unknown() {{overflow}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - );//TADDccTV + ); 0x23: tsubcctv({{ - int64_t resTemp, val2 = (I ? SIMM13 : Rs2); + int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 + val2; int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); if(overflow) fault = new TagOverflow;}}, @@ -239,12 +242,12 @@ decode OP default Unknown::unknown() {{overflow}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - );//TSUBccTV + ); 0x24: mulscc({{ - int64_t resTemp, multiplicand = (I ? SIMM13 : Rs2); + int64_t resTemp, multiplicand = Rs2_or_imm13; int32_t multiplier = Rs1<31:0>; int32_t savedLSB = Rs1<0:>; - multiplier = multipler<31:1> | + multiplier = multiplier<31:1> | ((CcrIccN ^ CcrIccV) << 32); if(!YValue<0:>) @@ -255,286 +258,387 @@ decode OP default Unknown::unknown() {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} - );//MULScc + ); + } + format IntOp + { + 0x25: decode X { + 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); + 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); } - format IntOp - { - 0x25: decode X { - 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); - 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); - } - 0x26: decode X { - 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); - 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); - } - 0x27: decode X { - 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA - 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX - } - 0x28: decode RS1 { - 0x0: rdy({{Rd = YValue;}}); //RDY - 0x2: rdccr({{Rd = Ccr;}}); //RDCCR - 0x3: rdasi({{Rd = Asi;}}); //RDASI - 0x4: PrivTick::rdtick({{Rd = Tick;}}); - 0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC - 0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS - 0xF: decode I { - 0x0: Noop::membar({{//Membar isn't needed yet}}); - 0x1: Noop::stbar({{//Stbar isn't needed yet}}); - } - } - 0x2A: decode RS1 { - format Priv - { - 0x0: rdprtpc({{ - Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl); - }}); - 0x1: rdprtnpc({{ - Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); - }}); - 0x2: rdprtstate({{ - Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl); - }}); - 0x3: rdprtt({{ - Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl); - }}); - 0x4: rdprtick({{Rd = Tick;}}); - 0x5: rdprtba({{Rd = Tba;}}); - 0x6: rdprpstate({{Rd = Pstate;}}); - 0x7: rdprtl({{Rd = Tl;}}); - 0x8: rdprpil({{Rd = Pil;}}); - 0x9: rdprcwp({{Rd = Cwp;}}); - 0xA: rdprcansave({{Rd = Cansave;}}); - 0xB: rdprcanrestore({{Rd = CanRestore;}}); - 0xC: rdprcleanwin({{Rd = Cleanwin;}}); - 0xD: rdprotherwin({{Rd = Otherwin;}}); - 0xE: rdprwstate({{Rd = Wstate;}}); - } - //The floating point queue isn't implemented right now. - 0xF: Trap::rdprfq({{fault = IllegalInstruction;}}); - 0x1F: Priv::rdprver({{Rd = Ver;}}); + 0x26: decode X { + 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); + 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); + } + 0x27: decode X { + 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); + 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); + } + 0x28: decode RS1 { + 0x0: rdy({{Rd = YValue;}}); + 0x2: rdccr({{Rd = Ccr;}}); + 0x3: rdasi({{Rd = Asi;}}); + 0x4: PrivTick::rdtick({{Rd = Tick;}}); + 0x5: rdpc({{Rd = xc->readPC();}}); + 0x6: rdfprs({{Rd = Fprs;}}); + 0xF: decode I { + 0x0: Nop::membar({{/*Membar isn't needed yet*/}}); + 0x1: Nop::stbar({{/*Stbar isn't needed yet*/}}); } - 0x2B: BasicOperate::flushw({{//window toilet}}); //FLUSHW - 0x2C: decode MOVCC3 + } + 0x2A: decode RS1 { + format Priv { - 0x0: Trap::movccfcc({{fault = new FpDisabled}}); - 0x1: decode CC - { - 0x0: movcci({{ - if(passesCondition(CcrIcc, COND4)) - Rd = (I ? SIMM11 : RS2); - }}); - 0x2: movccx({{ - if(passesCondition(CcrXcc, COND4)) - Rd = (I ? SIMM11 : RS2); - }}); - } - } - 0x2D: sdivx({{ - if(Rs2_or_imm13 == 0) fault = new DivisionByZero; - else Rd.sdw = Rs1.sdw / Rs2_or_imm13; - }});//SDIVX - 0x2E: decode RS1 { - 0x0: IntOp::popc({{ - int64_t count = 0, val2 = Rs2_or_imm; - uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; - for(unsigned int x = 0; x < 16; x++) - { - count += oneBits[Rs2_or_imm13 & 0xF]; - val2 >> 4; - } - }});//POPC + 0x0: rdprtpc({{ + Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl); + }}); + 0x1: rdprtnpc({{ + Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); + }}); + 0x2: rdprtstate({{ + Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl); + }}); + 0x3: rdprtt({{ + Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl); + }}); + 0x4: rdprtick({{Rd = Tick;}}); + 0x5: rdprtba({{Rd = Tba;}}); + 0x6: rdprpstate({{Rd = Pstate;}}); + 0x7: rdprtl({{Rd = Tl;}}); + 0x8: rdprpil({{Rd = Pil;}}); + 0x9: rdprcwp({{Rd = Cwp;}}); + 0xA: rdprcansave({{Rd = Cansave;}}); + 0xB: rdprcanrestore({{Rd = Canrestore;}}); + 0xC: rdprcleanwin({{Rd = Cleanwin;}}); + 0xD: rdprotherwin({{Rd = Otherwin;}}); + 0xE: rdprwstate({{Rd = Wstate;}}); } - 0x2F: decode RCOND3 + //The floating point queue isn't implemented right now. + 0xF: Trap::rdprfq({{fault = new IllegalInstruction;}}); + 0x1F: Priv::rdprver({{Rd = Ver;}}); + } + 0x2B: BasicOperate::flushw({{ + if(NWindows - 2 - Cansave == 0) { - 0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}}); - 0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}}); - 0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}}); - 0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}}); - 0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}}); - 0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}}); + if(Otherwin) + fault = new SpillNOther(WstateOther); + else + fault = new SpillNNormal(WstateNormal); } - 0x30: decode RD { - 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}}); - 0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); - 0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); - 0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}}); - 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}}); - } - 0x31: decode FCN { - 0x0: BasicOperate::saved({{//Boogy Boogy}}); //SAVED - 0x1: BasicOperate::restored({{//Boogy Boogy}}); //RESTORED + }}); + 0x2C: decode MOVCC3 + { + 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); + 0x1: decode CC + { + 0x0: movcci({{ + if(passesCondition(CcrIcc, COND4)) + Rd = (I ? SIMM11 : RS2); + }}); + 0x2: movccx({{ + if(passesCondition(CcrXcc, COND4)) + Rd = (I ? SIMM11 : RS2); + }}); } - 0x32: decode RD { - format Priv + } + 0x2D: sdivx({{ + if(Rs2_or_imm13 == 0) fault = new DivisionByZero; + else Rd.sdw = Rs1.sdw / Rs2_or_imm13; + }}); + 0x2E: decode RS1 { + 0x0: IntOp::popc({{ + int64_t count = 0; + uint64_t temp = Rs2_or_imm13; + //Count the 1s in the front 4bits until none are left + uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; + while(temp) { - 0x0: wrprtpc({{ - xc->setMiscReg(MISCREG_TPC_BASE + Tl, - Rs1 ^ Rs2_or_imm13); - }}); - 0x1: wrprtnpc({{ - xc->setMiscReg(MISCREG_TNPC_BASE + Tl, - Rs1 ^ Rs2_or_imm13); - }}); - 0x2: wrprtstate({{ - xc->setMiscReg(MISCREG_TSTATE_BASE + Tl, - Rs1 ^ Rs2_or_imm13); - }}); - 0x3: wrprtt({{ - xc->setMiscReg(MISCREG_TT_BASE + Tl, - Rs1 ^ Rs2_or_imm13); - }}); - 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); - 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); - 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); - 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}}); - 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); - 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); - 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); - 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); - 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); - 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); - 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); + count += oneBits[temp & 0xF]; + temp = temp >> 4; } + }}); + } + 0x2F: decode RCOND3 + { + 0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}}); + 0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}}); + 0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}}); + 0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}}); + 0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}}); + 0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}}); + } + 0x30: decode RD { + 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}}); + 0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); + 0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); + 0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}}); + 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}}); + } + 0x31: decode FCN { + 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); + 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); + } + 0x32: decode RD { + format Priv + { + 0x0: wrprtpc({{ + xc->setMiscReg(MISCREG_TPC_BASE + Tl, + Rs1 ^ Rs2_or_imm13); + }}); + 0x1: wrprtnpc({{ + xc->setMiscReg(MISCREG_TNPC_BASE + Tl, + Rs1 ^ Rs2_or_imm13); + }}); + 0x2: wrprtstate({{ + xc->setMiscReg(MISCREG_TSTATE_BASE + Tl, + Rs1 ^ Rs2_or_imm13); + }}); + 0x3: wrprtt({{ + xc->setMiscReg(MISCREG_TT_BASE + Tl, + Rs1 ^ Rs2_or_imm13); + }}); + 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); + 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); + 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); + 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}}); + 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); + 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); + 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); + 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); + 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); + 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); + 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); } - - 0x34: Trap::fpop1({{fault = new FpDisabled;}}); - 0x35: Trap::fpop2({{fault = new FpDisabled;}}); - - 0x38: Branch::jmpl({{//Stuff}}); //JMPL - 0x39: Branch::return({{//Other Stuff}}); //RETURN - 0x3A: decode CC + } + 0x34: Trap::fpop1({{fault = new FpDisabled;}}); + 0x35: Trap::fpop2({{fault = new FpDisabled;}}); + 0x38: Branch::jmpl({{ + Addr target = Rs1 + Rs2_or_imm13; + if(target & 0x3) + fault = new MemAddressNotAligned; + else { - 0x0: Trap::tcci({{ + Rd = xc->readPC(); + NNPC = target; + } + }}); + 0x39: Branch::return({{ + Addr target = Rs1 + Rs2_or_imm13; + if(target & 0x3) + fault = new MemAddressNotAligned; + else + NNPC = target; + //This needs to change the register window + //like restore does + }}); + 0x3A: decode CC + { + 0x0: Trap::tcci({{ #if FULL_SYSTEM - fault = new TrapInstruction; + fault = new TrapInstruction; #else - if(passesCondition(CcrIcc, machInst<25:28>)) - // At least glibc only uses trap 0, - // solaris/sunos may use others - assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); - xc->syscall(); + if(passesCondition(CcrIcc, machInst<25:28>)) + { + // At least glibc only uses trap 0, + // solaris/sunos may use others + assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); + xc->syscall(); + } #endif - }}); - 0x2: Trap::tccx({{ + }}); + 0x2: Trap::tccx({{ #if FULL_SYSTEM - fault = new TrapInstruction; + fault = new TrapInstruction; #else - if(passesCondition(CcrXcc, machInst<25:28>)) - // At least glibc only uses trap 0, - // solaris/sunos may use others - assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); - xc->syscall(); + if(passesCondition(CcrXcc, machInst<25:28>)) + { + // At least glibc only uses trap 0, + // solaris/sunos may use others + assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); + xc->syscall(); + } #endif - }}); + }}); + } + 0x3B: Nop::flush({{/*Instruction memory flush*/}}); + 0x3C: save({{ + //CWP should be set directly so that it always happens + //Also, this will allow writing to the new window and + //reading from the old one + if(Cansave == 0) + { + if(Otherwin) + fault = new SpillNOther(WstateOther); + else + fault = new SpillNNormal(WstateNormal); + Cwp = (Cwp + 2) % NWindows; + } + else if(Cleanwin - Canrestore == 0) + { + Cwp = (Cwp + 1) % NWindows; + fault = new CleanWindow; } - 0x3B: BasicOperate::flush({{//Lala}}); //FLUSH - 0x3C: BasicOperate::save({{//leprechauns); //SAVE - 0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE - 0x3E: decode FCN { - 0x1: BasicOperate::done({{//Done thing}}); //DONE - 0x2: BasicOperate::retry({{//Retry thing}}); //RETRY + else + { + Cwp = (Cwp + 1) % NWindows; + Rd = Rs1 + Rs2_or_imm13; + Cansave--; + Canrestore++; + } + //This is here to make sure the CWP is written + //no matter what. This ensures that the results + //are written in the new window as well. + xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); + }}); + 0x3D: restore({{ + //CWP should be set directly so that it always happens + //Also, this will allow writing to the new window and + //reading from the old one + Cwp = (Cwp - 1 + NWindows) % NWindows; + if(Canrestore == 0) + { + if(Otherwin) + fault = new FillNOther(WstateOther); + else + fault = new FillNNormal(WstateNormal); } + else + { + Rd = Rs1 + Rs2_or_imm13; + Cansave++; + Canrestore--; + } + //This is here to make sure the CWP is written + //no matter what. This ensures that the results + //are written in the new window as well. + xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); + }}); + 0x3E: decode FCN { + 0x0: Priv::done({{ + if(Tl == 0) + return new IllegalInstruction; + Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl); + Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl); + Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl); + Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl); + NPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); + NNPC = NPC + 4; + Tl = Tl - 1; + }}); + 0x1: BasicOperate::retry({{ + if(Tl == 0) + return new IllegalInstruction; + Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl); + Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl); + Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl); + Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl); + NPC = xc->readMiscReg(MISCREG_TPC_BASE + Tl); + NNPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); + Tl = Tl - 1; + }}); } + } } 0x3: decode OP3 { - format Mem { - 0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW - 0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB - 0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH - 0x03: ldd({{ - uint64_t val = Mem.udw; - setIntReg(RD & (~1), val<31:0>); - setIntReg(RD | 1, val<63:32>); - }});//LDD - 0x04: stw({{Mem.sw = Rd.sw;}}); //STW - 0x05: stb({{Mem.sb = Rd.sb;}}); //STB - 0x06: sth({{Mem.shw = Rd.shw;}}); //STH - 0x07: std({{ - Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); - }});//STD - 0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW - 0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB - 0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH - 0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX - - 0x0D: ldstub({{ - Rd.ub = Mem.ub; - Mem.ub = 0xFF; - }}); //LDSTUB - 0x0E: stx({{Rd.udw = Mem.udw;}}); //STX - 0x0F: swap({{ - uint32_t temp = Rd.uw; - Rd.uw = Mem.uw; - Mem.uw = temp; - }}); //SWAP - 0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA - 0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA - 0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA - 0x13: ldda({{ - uint64_t val = Mem.udw; - setIntReg(RD & (~1), val<31:0>); - setIntReg(RD | 1, val<63:32>); - }}); //LDDA - 0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA - 0x15: stba({{Mem.ub = Rd.ub;}}); //STBA - 0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA - 0x17: stda({{ - Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); - }}); //STDA - 0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA - 0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA - 0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA - 0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA - - 0x1D: ldstuba({{ - Rd.ub = Mem.ub; - Mem.ub = 0xFF; - }}); //LDSTUBA - 0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA - 0x1F: swapa({{ - uint32_t temp = Rd.uw; - Rd.uw = Mem.uw; - Mem.uw = temp; - }}); //SWAPA - 0x20: Trap::ldf({{fault = new FpDisabled;}}); - 0x21: decode X { - 0x0: Trap::ldfsr({{fault = new FpDisabled;}}); - 0x1: Trap::ldxfsr({{fault = new FpDisabled;}}); - } - 0x22: Trap::ldqf({{fault = new FpDisabled;}}); - 0x23: Trap::lddf({{fault = new FpDisabled;}}); - 0x24: Trap::stf({{fault = new FpDisabled;}}); - 0x25: decode X { - 0x0: Trap::stfsr({{fault = new FpDisabled;}}); - 0x1: Trap::stxfsr({{fault = new FpDisabled;}}); - } - 0x26: Trap::stqf({{fault = new FpDisabled;}}); - 0x27: Trap::stdf({{fault = new FpDisabled;}}); - - 0x2D: Noop::prefetch({{ }}); //PREFETCH - - 0x30: Trap::ldfa({{return new FpDisabled;}}); - - 0x32: Trap::ldqfa({{fault = new FpDisabled;}}); - 0x33: Trap::lddfa({{fault = new FpDisabled;}}); - 0x34: Trap::stfa({{fault = new FpDisabled;}}); - 0x35: Trap::stqfa({{fault = new FpDisabled;}}); - 0x36: Trap::stdfa({{fault = new FpDisabled;}}); - - 0x3C: Cas::casa( - {{uint64_t val = Mem.uw; - if(Rs2.uw == val) - Mem.uw = Rd.uw; - Rd.uw = val; - }}); //CASA - 0x3D: Noop::prefetcha({{ }}); //PREFETCHA - 0x3E: Cas::casxa({{ - uint64_t val = Mem.udw; - if(Rs2 == val) - Mem.udw = Rd; - Rd = val; - }}); //CASXA + format Load { + 0x00: lduw({{Rd = Mem;}}, {{32}}); + 0x01: ldub({{Rd = Mem;}}, {{8}}); + 0x02: lduh({{Rd = Mem;}}, {{16}}); + 0x03: ldd({{ + uint64_t val = Mem; + RdLow = val<31:0>; + RdHigh = val<63:32>; + }}, {{64}}); + } + format Store { + 0x04: stw({{Mem = Rd.sw;}}, {{32}}); + 0x05: stb({{Mem = Rd.sb;}}, {{8}}); + 0x06: sth({{Mem = Rd.shw;}}, {{16}}); + 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); + } + format Load { + 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}}); + 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}}); + 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}}); + 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}}); + 0x0D: ldstub({{ + Rd = Mem; + Mem = 0xFF; + }}, {{8}}); + } + 0x0E: Store::stx({{Mem = Rd}}, {{64}}); + 0x0F: LoadStore::swap({{ + uint32_t temp = Rd; + Rd = Mem; + Mem = temp; + }}, {{32}}); + format Load { + 0x10: lduwa({{Rd = Mem;}}, {{32}}); + 0x11: lduba({{Rd = Mem;}}, {{8}}); + 0x12: lduha({{Rd = Mem;}}, {{16}}); + 0x13: ldda({{ + uint64_t val = Mem; + RdLow = val<31:0>; + RdHigh = val<63:32>; + }}, {{64}}); + } + format Store { + 0x14: stwa({{Mem = Rd;}}, {{32}}); + 0x15: stba({{Mem = Rd;}}, {{8}}); + 0x16: stha({{Mem = Rd;}}, {{16}}); + 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); + } + format Load { + 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}}); + 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}}); + 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}}); + 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}}); + } + 0x1D: LoadStore::ldstuba({{ + Rd = Mem; + Mem = 0xFF; + }}, {{8}}); + 0x1E: Store::stxa({{Mem = Rd}}, {{64}}); + 0x1F: LoadStore::swapa({{ + uint32_t temp = Rd; + Rd = Mem; + Mem = temp; + }}, {{32}}); + format Trap { + 0x20: ldf({{fault = new FpDisabled;}}); + 0x21: decode X { + 0x0: ldfsr({{fault = new FpDisabled;}}); + 0x1: ldxfsr({{fault = new FpDisabled;}}); + } + 0x22: ldqf({{fault = new FpDisabled;}}); + 0x23: lddf({{fault = new FpDisabled;}}); + 0x24: stf({{fault = new FpDisabled;}}); + 0x25: decode X { + 0x0: stfsr({{fault = new FpDisabled;}}); + 0x1: stxfsr({{fault = new FpDisabled;}}); } + 0x26: stqf({{fault = new FpDisabled;}}); + 0x27: stdf({{fault = new FpDisabled;}}); + 0x2D: Nop::prefetch({{ }}); + 0x30: ldfa({{return new FpDisabled;}}); + 0x32: ldqfa({{fault = new FpDisabled;}}); + 0x33: lddfa({{fault = new FpDisabled;}}); + 0x34: stfa({{fault = new FpDisabled;}}); + 0x35: stqfa({{fault = new FpDisabled;}}); + 0x36: stdfa({{fault = new FpDisabled;}}); + 0x3C: Cas::casa({{ + uint64_t val = Mem.uw; + if(Rs2.uw == val) + Mem.uw = Rd.uw; + Rd.uw = val; + }}); + 0x3D: Nop::prefetcha({{ }}); + 0x3E: Cas::casxa({{ + uint64_t val = Mem.udw; + if(Rs2 == val) + Mem.udw = Rd; + Rd = val; + }}); + } } } diff --git a/arch/sparc/isa/formats.isa b/arch/sparc/isa/formats.isa index 9310ba3d3..17d68061b 100644 --- a/arch/sparc/isa/formats.isa +++ b/arch/sparc/isa/formats.isa @@ -1,28 +1,28 @@ //Include the basic format //Templates from this format are used later -##include "m5/arch/sparc/isa/formats/basic.isa" +##include "formats/basic.isa" + +//Include the noop format +##include "formats/nop.isa" //Include the integerOp and integerOpCc format -##include "m5/arch/sparc/isa/formats/integerop.isa" +##include "formats/integerop.isa" //Include the memory format -##include "m5/arch/sparc/isa/formats/mem.isa" +##include "formats/mem.isa" //Include the compare and swap format -##include "m5/arch/sparc/isa/formats/cas.isa" +##include "formats/cas.isa" //Include the trap format -##include "m5/arch/sparc/isa/formats/trap.isa" +##include "formats/trap.isa" //Include the "unknown" format -##include "m5/arch/sparc/isa/formats/unknown.isa" +##include "formats/unknown.isa" //Include the priveleged mode format -##include "m5/arch/sparc/isa/formats/priv.isa" +##include "formats/priv.isa" //Include the branch format -##include "m5/arch/sparc/isa/formats/branch.isa" - -//Include the noop format -##include "m5/arch/sparc/isa/formats/noop.isa" +##include "formats/branch.isa" diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa index b9dc960de..e4ce4592c 100644 --- a/arch/sparc/isa/formats/branch.isa +++ b/arch/sparc/isa/formats/branch.isa @@ -5,7 +5,7 @@ output header {{ /** - * Base class for integer operations. + * Base class for branch operations. */ class Branch : public SparcStaticInst { @@ -19,12 +19,187 @@ output header {{ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; + + /** + * Base class for branch operations with an immediate displacement. + */ + class BranchDisp : public Branch + { + protected: + // Constructor + BranchDisp(const char *mnem, MachInst _machInst, + OpClass __opClass) : + Branch(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + + int32_t disp; + }; + + /** + * Base class for branches with 19 bit displacements. + */ + class Branch19 : public BranchDisp + { + protected: + // Constructor + Branch19(const char *mnem, MachInst _machInst, + OpClass __opClass) : + BranchDisp(mnem, _machInst, __opClass) + { + disp = sign_ext(DISP19 << 2, 21); + } + }; + + /** + * Base class for branches with 22 bit displacements. + */ + class Branch22 : public BranchDisp + { + protected: + // Constructor + Branch22(const char *mnem, MachInst _machInst, + OpClass __opClass) : + BranchDisp(mnem, _machInst, __opClass) + { + disp = sign_ext(DISP22 << 2, 24); + } + }; + + /** + * Base class for branches with 30 bit displacements. + */ + class Branch30 : public BranchDisp + { + protected: + // Constructor + Branch30(const char *mnem, MachInst _machInst, + OpClass __opClass) : + BranchDisp(mnem, _machInst, __opClass) + { + disp = sign_ext(DISP30 << 2, 32); + } + }; + + /** + * Base class for 16bit split displacements. + */ + class BranchSplit : public BranchDisp + { + protected: + // Constructor + BranchSplit(const char *mnem, MachInst _machInst, + OpClass __opClass) : + BranchDisp(mnem, _machInst, __opClass) + { + disp = sign_ext((D16HI << 16) | (D16LO << 2), 18); + } + }; + + /** + * Base class for branches that use an immediate and a register to + * compute their displacements. + */ + class BranchImm13 : public Branch + { + protected: + // Constructor + BranchImm13(const char *mnem, MachInst _machInst, OpClass __opClass) : + Branch(mnem, _machInst, __opClass), imm(sign_ext(SIMM13, 13)) + { + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + + int32_t imm; + }; }}; output decoder {{ - std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const + std::string Branch::generateDisassembly(Addr pc, + const SymbolTable *symtab) const { - return "Branch instruction\n"; + std::stringstream response; + + printMnemonic(response, mnemonic); + + if (_numSrcRegs > 0) + { + printReg(response, _srcRegIdx[0]); + for(int x = 1; x < _numSrcRegs; x++) + { + response << ", "; + printReg(response, _srcRegIdx[x]); + } + } + + if (_numDestRegs > 0) + { + if(_numSrcRegs > 0) + response << ", "; + printReg(response, _destRegIdx[0]); + } + + return response.str(); + } + + std::string BranchImm13::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, mnemonic); + + if (_numSrcRegs > 0) + { + printReg(response, _srcRegIdx[0]); + for(int x = 1; x < _numSrcRegs; x++) + { + response << ", "; + printReg(response, _srcRegIdx[x]); + } + } + + if(_numSrcRegs > 0) + response << ", "; + + ccprintf(response, "0x%x", imm); + + if (_numDestRegs > 0) + { + response << ", "; + printReg(response, _destRegIdx[0]); + } + + return response.str(); + } + + std::string BranchDisp::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + std::string symbol; + Addr symbolAddr; + + Addr target = disp + pc; + + printMnemonic(response, mnemonic); + ccprintf(response, "0x%x", target); + + if(symtab->findNearestSymbol(target, symbol, symbolAddr)) + { + ccprintf(response, " <%s", symbol); + if(symbolAddr != target) + ccprintf(response, "+0x%x>", target - symbolAddr); + else + ccprintf(response, ">"); + } + + return response.str(); } }}; @@ -37,6 +212,8 @@ def template BranchExecute {{ %(op_decl)s; %(op_rd)s; + + NNPC = xc->readNextNPC(); %(code)s; if(fault == NoFault) @@ -49,13 +226,63 @@ def template BranchExecute {{ } }}; -// Primary format for integer operate instructions: +// Primary format for branch instructions: def format Branch(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + (usesImm, code, immCode, + rString, iString) = splitOutImm(code) + codeBlk = CodeBlock(code) + iop = InstObjParams(name, Name, 'Branch', codeBlk, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) + exec_output = BranchExecute.subst(iop) + if usesImm: + imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString, + codeBlk, opt_flags) + header_output += BasicDeclare.subst(imm_iop) + decoder_output += BasicConstructor.subst(imm_iop) + exec_output += BranchExecute.subst(imm_iop) + decode_block = ROrImmDecode.subst(iop) + else: + decode_block = BasicDecode.subst(iop) +}}; + +// Primary format for branch instructions: +def format Branch19(code, *opt_flags) {{ + codeBlk = CodeBlock(code) + iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + exec_output = BranchExecute.subst(iop) decode_block = BasicDecode.subst(iop) +}}; + +// Primary format for branch instructions: +def format Branch22(code, *opt_flags) {{ + codeBlk = CodeBlock(code) + iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) exec_output = BranchExecute.subst(iop) + decode_block = BasicDecode.subst(iop) +}}; + +// Primary format for branch instructions: +def format Branch30(code, *opt_flags) {{ + codeBlk = CodeBlock(code) + iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + exec_output = BranchExecute.subst(iop) + decode_block = BasicDecode.subst(iop) }}; + +// Primary format for branch instructions: +def format BranchSplit(code, *opt_flags) {{ + codeBlk = CodeBlock(code) + iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + exec_output = BranchExecute.subst(iop) + decode_block = BasicDecode.subst(iop) +}}; + diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa index e7bd4c2a4..f14f9e858 100644 --- a/arch/sparc/isa/formats/integerop.isa +++ b/arch/sparc/isa/formats/integerop.isa @@ -11,103 +11,230 @@ output header {{ { protected: // Constructor - IntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : + IntOp(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) { } std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + + virtual bool printPseudoOps(std::ostream &os, Addr pc, + const SymbolTable *symtab) const; }; /** - * Base class for 10 bit immediate integer operations. + * Base class for immediate integer operations. */ - class IntOpImm10 : public IntOp + class IntOpImm : public IntOp { protected: // Constructor - IntOpImm10(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - IntOp(mnem, _machInst, __opClass), imm(SIMM10) + IntOpImm(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + IntOp(mnem, _machInst, __opClass) { } - uint32_t imm; + int32_t imm; + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + + virtual bool printPseudoOps(std::ostream &os, Addr pc, + const SymbolTable *symtab) const; + }; + + /** + * Base class for 10 bit immediate integer operations. + */ + class IntOpImm10 : public IntOpImm + { + protected: + // Constructor + IntOpImm10(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + IntOpImm(mnem, _machInst, __opClass) + { + imm = sign_ext(SIMM10, 10); + } }; /** * Base class for 13 bit immediate integer operations. */ - class IntOpImm13 : public IntOp + class IntOpImm13 : public IntOpImm { protected: // Constructor - IntOpImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - IntOp(mnem, _machInst, __opClass), imm(SIMM13) + IntOpImm13(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + IntOpImm(mnem, _machInst, __opClass) { + imm = sign_ext(SIMM13, 13); } + }; - uint32_t imm; + /** + * Base class for sethi. + */ + class SetHi : public IntOpImm + { + protected: + // Constructor + SetHi(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + IntOpImm(mnem, _machInst, __opClass) + { + imm = (IMM22 << 10) & 0xFFFFFC00; + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; }; }}; +def template SetHiDecode {{ + { + if(RD == 0 && IMM22 == 0) + return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass)); + else + return (SparcStaticInst *)(new %(class_name)s(machInst)); + } +}}; + output decoder {{ - std::string IntOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + + bool IntOp::printPseudoOps(std::ostream &os, Addr pc, + const SymbolTable *symbab) const { - return "Integer instruction\n"; + if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) + { + printMnemonic(os, "mov"); + if(_numSrcRegs > 0) + printReg(os, _srcRegIdx[1]); + ccprintf(os, ", "); + if(_numDestRegs > 0) + printReg(os, _destRegIdx[0]); + + return true; + } + return false; } -}}; -def template IntOpExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const + bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc, + const SymbolTable *symbab) const { - Fault fault = NoFault; + if(!strcmp(mnemonic, "or")) + { + if(_srcRegIdx[0] == 0) + { + if(imm == 0) + { + printMnemonic(os, "clr"); + if(_numDestRegs > 0) + printReg(os, _destRegIdx[0]); + return true; + } + else + { + printMnemonic(os, "mov"); + ccprintf(os, ", 0x%x, ", imm); + if(_numDestRegs > 0) + printReg(os, _destRegIdx[0]); + return true; + } + } + else if(imm == 0) + { + printMnemonic(os, "mov"); + if(_numSrcRegs > 0) + printReg(os, _srcRegIdx[0]); + ccprintf(os, ", "); + if(_numDestRegs > 0) + printReg(os, _destRegIdx[0]); + return true; + } + } + return false; + } - %(op_decl)s; - %(op_rd)s; - %(code)s; + std::string IntOp::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; - //Write the resulting state to the execution context - if(fault == NoFault) - %(op_wb)s; - return fault; + if(!printPseudoOps(response, pc, symtab)) + { + printMnemonic(response, mnemonic); + if (_numSrcRegs > 0) + { + printReg(response, _srcRegIdx[0]); + for(int x = 1; x < _numSrcRegs; x++) + { + response << ", "; + printReg(response, _srcRegIdx[x]); + } + } + if (_numDestRegs > 0) + { + if(_numSrcRegs > 0) + response << ", "; + printReg(response, _destRegIdx[0]); + } + } + return response.str(); } -}}; -def template IntOpCcExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const + std::string IntOpImm::generateDisassembly(Addr pc, + const SymbolTable *symtab) const { - Fault fault; - - %(op_decl)s; - %(op_rd)s; - %(code)s; + std::stringstream response; - //Write the resulting state to the execution context - if(fault == NoFault) + if(!printPseudoOps(response, pc, symtab)) { - %(op_wb)s; - CcrIccN = Rd & (1 << 63); - CcrIccZ = (Rd == 0); - CcrIccV = ivValue; - CcrIccC = icValue; - CcrXccN = Rd & (1 << 31); - CcrXccZ = ((Rd & 0xFFFFFFFF) == 0); - CcrXccV = xvValue; - CcrXccC = xcValue; + printMnemonic(response, mnemonic); + if (_numSrcRegs > 0) + { + printReg(response, _srcRegIdx[0]); + for(int x = 1; x < _numSrcRegs - 1; x++) + { + response << ", "; + printReg(response, _srcRegIdx[x]); + } + } + if(_numSrcRegs > 0) + response << ", "; + ccprintf(response, "0x%x", imm); + if (_numDestRegs > 0) + { + response << ", "; + printReg(response, _destRegIdx[0]); + } } - return fault; + return response.str(); + } + + std::string SetHi::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, mnemonic); + if(_numSrcRegs > 0) + response << ", "; + ccprintf(response, "%%hi(0x%x), ", imm); + printReg(response, _destRegIdx[0]); + return response.str(); } }}; -def template IntOpCcResExecute {{ +def template IntOpExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - Fault fault; + Fault fault = NoFault; %(op_decl)s; %(op_rd)s; @@ -117,49 +244,83 @@ def template IntOpCcResExecute {{ if(fault == NoFault) { %(op_wb)s; - CcrIccN = Rd & (1 << 63); - CcrIccZ = (Rd == 0); - CcrXccN = Rd & (1 << 31); - CcrXccZ = ((Rd & 0xFFFFFFFF) == 0); - CcrIccV = CcrIccC = CcrXccV = CcrXccC = 0; + %(cc_code)s; } return fault; } }}; let {{ - def doIntFormat(code, execTemplate, name, Name, opt_flags): - (usesImm, cblk, immCblk, rString, iString) = splitOutImm(code) - iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags) + def doIntFormat(code, ccCode, name, Name, opt_flags): + (usesImm, code, immCode, + rString, iString) = splitOutImm(code) + iop = InstObjParams(name, Name, 'IntOp', code, + opt_flags, ("cc_code", ccCode)) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) - exec_output = execTemplate.subst(iop) + exec_output = IntOpExecute.subst(iop) if usesImm: imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString, - immCblk, opt_flags) + immCode, opt_flags, ("cc_code", ccCode)) header_output += BasicDeclare.subst(imm_iop) decoder_output += BasicConstructor.subst(imm_iop) - exec_output += execTemplate.subst(imm_iop) + exec_output += IntOpExecute.subst(imm_iop) decode_block = ROrImmDecode.subst(iop) else: decode_block = BasicDecode.subst(iop) + return (header_output, decoder_output, exec_output, decode_block) + + calcCcCode = ''' + CcrIccN = (Rd >> 63) & 1; + CcrIccZ = (Rd == 0); + CcrXccN = (Rd >> 31) & 1; + CcrXccZ = ((Rd & 0xFFFFFFFF) == 0); + CcrIccV = %(ivValue)s; + CcrIccC = %(icValue)s; + CcrXccV = %(xvValue)s; + CcrXccC = %(xcValue)s; + ''' }}; // Primary format for integer operate instructions: def format IntOp(code, *opt_flags) {{ - doIntFormat(code, IntOpExecute, name, Name, opt_flags) + ccCode = '' + (header_output, + decoder_output, + exec_output, + decode_block) = doIntFormat(code, ccCode, + name, Name, opt_flags) }}; // Primary format for integer operate instructions: def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ - for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), - ('xvValue', xvValue), ('xcValue', xcValue)): - code.replace(marker, value) - doIntFormat(code, IntOpCcExecute, name, Name, opt_flags) + ccCode = calcCcCode % vars() + (header_output, + decoder_output, + exec_output, + decode_block) = doIntFormat(code, ccCode, + name, Name, opt_flags) }}; // Primary format for integer operate instructions: def format IntOpCcRes(code, *opt_flags) {{ - doIntFormat(code, IntOpCcResExecute, name, Name, opt_flags) + ccCode = calcCcCode % {"icValue":"0", + "ivValue":"0", + "xcValue":"0", + "xvValue":"0"} + (header_output, + decoder_output, + exec_output, + decode_block) = doIntFormat(code, ccCode, + name, Name, opt_flags) +}}; + +def format SetHi(code, *opt_flags) {{ + iop = InstObjParams(name, Name, 'SetHi', + code, opt_flags, ("cc_code", '')) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + exec_output = IntOpExecute.subst(iop) + decode_block = SetHiDecode.subst(iop) }}; diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa index 06725eae8..db2a4aaaa 100644 --- a/arch/sparc/isa/formats/mem.isa +++ b/arch/sparc/isa/formats/mem.isa @@ -5,7 +5,7 @@ output header {{ /** - * Base class for integer operations. + * Base class for memory operations. */ class Mem : public SparcStaticInst { @@ -20,12 +20,76 @@ output header {{ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; + + /** + * Class for memory operations which use an immediate offset. + */ + class MemImm : public Mem + { + protected: + + // Constructor + MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : + Mem(mnem, _machInst, __opClass), imm(SIMM13) + { + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + + int32_t imm; + }; }}; output decoder {{ - std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const + std::string Mem::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + bool load = flags[IsLoad]; + + printMnemonic(response, mnemonic); + if(!load) + { + printReg(response, _srcRegIdx[0]); + ccprintf(response, ", "); + } + ccprintf(response, "[ "); + printReg(response, _srcRegIdx[load ? 0 : 1]); + ccprintf(response, " + "); + printReg(response, _srcRegIdx[load ? 1 : 2]); + ccprintf(response, " ]"); + if(load) + { + ccprintf(response, ", "); + printReg(response, _destRegIdx[0]); + } + + return response.str(); + } + + std::string MemImm::generateDisassembly(Addr pc, + const SymbolTable *symtab) const { - return "Memory instruction\n"; + std::stringstream response; + bool load = flags[IsLoad]; + + printMnemonic(response, mnemonic); + if(!load) + { + printReg(response, _srcRegIdx[0]); + ccprintf(response, ", "); + } + ccprintf(response, "[ "); + printReg(response, _srcRegIdx[load ? 0 : 1]); + ccprintf(response, " + 0x%x ]", imm); + if(load) + { + ccprintf(response, ", "); + printReg(response, _destRegIdx[0]); + } + + return response.str(); } }}; @@ -34,10 +98,13 @@ def template MemExecute {{ Trace::InstRecord *traceData) const { Fault fault = NoFault; + Addr EA; %(op_decl)s; %(op_rd)s; - ea_code + %(ea_code)s; + %(load)s; %(code)s; + %(store)s; if(fault == NoFault) { @@ -49,14 +116,49 @@ def template MemExecute {{ } }}; -// Primary format for integer operate instructions: -def format Mem(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = MemExecute.subst(iop) - exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;'); +let {{ + # Leave memAccessFlags at 0 for now + loadString = "xc->read(EA, (uint%(width)s_t&)Mem, 0);" + storeString = "uint64_t write_result = 0; \ + xc->write((uint%(width)s_t)Mem, EA, 0, &write_result);" + + def doMemFormat(code, load, store, name, Name, opt_flags): + addrCalcReg = 'EA = Rs1 + Rs2;' + addrCalcImm = 'EA = Rs1 + SIMM13;' + iop = InstObjParams(name, Name, 'Mem', code, + opt_flags, ("ea_code", addrCalcReg), + ("load", load), ("store", store)) + iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code, + opt_flags, ("ea_code", addrCalcImm), + ("load", load), ("store", store)) + header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm) + decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm) + decode_block = ROrImmDecode.subst(iop) + exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm) + return (header_output, decoder_output, exec_output, decode_block) +}}; + +def format Load(code, width, *opt_flags) {{ + (header_output, + decoder_output, + exec_output, + decode_block) = doMemFormat(code, + loadString % {"width":width}, '', name, Name, opt_flags) +}}; + +def format Store(code, width, *opt_flags) {{ + (header_output, + decoder_output, + exec_output, + decode_block) = doMemFormat(code, '', + storeString % {"width":width}, name, Name, opt_flags) +}}; + +def format LoadStore(code, width, *opt_flags) {{ + (header_output, + decoder_output, + exec_output, + decode_block) = doMemFormat(code, + loadString % {"width":width}, storeString % {"width":width}, + name, Name, opt_flags) }}; diff --git a/arch/sparc/isa/formats/noop.isa b/arch/sparc/isa/formats/nop.isa index 5007f5bcb..df7503eee 100644 --- a/arch/sparc/isa/formats/noop.isa +++ b/arch/sparc/isa/formats/nop.isa @@ -1,35 +1,47 @@ //////////////////////////////////////////////////////////////////// // -// Noop instruction +// Nop instruction // output header {{ /** - * Noop class. + * Nop class. */ - class Noop : public SparcStaticInst + class Nop : public SparcStaticInst { - protected: + public: // Constructor - Noop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : + Nop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) { } + // All Nop instructions do the same thing, so this can be + // defined here. Nops can be defined directly, so there needs + // to be a default implementation + Fault execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + //Nothing to see here, move along + return NoFault; + } + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; }}; output decoder {{ - std::string Noop::generateDisassembly(Addr pc, + std::string Nop::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return "Noop\n"; + std::stringstream response; + printMnemonic(response, mnemonic); + return response.str(); } }}; -def template NoopExecute {{ +def template NopExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -39,12 +51,12 @@ def template NoopExecute {{ }}; // Primary format for integer operate instructions: -def format Noop(code, *opt_flags) {{ +def format Nop(code, *opt_flags) {{ orig_code = code cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + iop = InstObjParams(name, Name, 'Nop', cblk, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) - exec_output = NoopExecute.subst(iop) + exec_output = NopExecute.subst(iop) }}; diff --git a/arch/sparc/isa/formats/priv.isa b/arch/sparc/isa/formats/priv.isa index c89e769b4..f9fea01f2 100644 --- a/arch/sparc/isa/formats/priv.isa +++ b/arch/sparc/isa/formats/priv.isa @@ -50,7 +50,7 @@ output header {{ { } - uint32_t imm; + int32_t imm; }; /** @@ -66,7 +66,7 @@ output header {{ { } - uint32_t imm; + int32_t imm; }; }}; @@ -92,74 +92,48 @@ def template PrivExecute {{ %(op_rd)s; //If the processor isn't in privileged mode, fault out right away - if(!PstatePriv) - return new PrivilegedOpcode + if(%(check)s) + return new PrivilegedAction; %(code)s; %(op_wb)s; + return NoFault; } }}; -def template PrivTickExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - %(op_decl)s; - %(op_rd)s; - - //If the processor isn't in privileged mode, fault out right away - if(!PstatePriv && TickNpt) - return new PrivilegedAction - - %(code)s; - %(op_wb)s; - } -}}; - -// Primary format for integer operate instructions: -def format Priv(code, *opt_flags) {{ - uses_imm = (code.find('Rs2_or_imm13') != -1) - if uses_imm: - orig_code = code - code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code) - imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code) - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'Priv', cblk, opt_flags) +let {{ + def doPrivFormat(code, checkCode, name, Name, opt_flags): + (usesImm, code, immCode, + rString, iString) = splitOutImm(code) + iop = InstObjParams(name, Name, 'Priv', code, + opt_flags, ("check", checkCode)) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) exec_output = PrivExecute.subst(iop) - if uses_imm: - imm_cblk = CodeBlock(imm_code) - imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', imm_cblk, - opt_flags) + if usesImm: + imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', + immCode, opt_flags, ("check", checkCode)) header_output += BasicDeclare.subst(imm_iop) decoder_output += BasicConstructor.subst(imm_iop) exec_output += PrivExecute.subst(imm_iop) decode_block = ROrImmDecode.subst(iop) else: decode_block = BasicDecode.subst(iop) + return (header_output, decoder_output, exec_output, decode_block) +}}; + +// Primary format for integer operate instructions: +def format Priv(code, *opt_flags) {{ + checkCode = "(!PstatePriv)" + (header_output, decoder_output, + exec_output, decode_block) = doPrivFormat(code, + checkCode, name, Name, opt_flags) }}; // Primary format for integer operate instructions: def format PrivTick(code, *opt_flags) {{ - uses_imm = (code.find('Rs2_or_imm13') != -1) - if uses_imm: - orig_code = code - code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code) - imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code) - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'PrivTick', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = PrivTickExecute.subst(iop) - if uses_imm: - imm_cblk = CodeBlock(imm_code) - imm_iop = InstObjParams(name, Name + 'Imm', 'PrivTickImm', imm_cblk, - opt_flags) - header_output += BasicDeclare.subst(imm_iop) - decoder_output += BasicConstructor.subst(imm_iop) - exec_output += PrivTickExecute.subst(imm_iop) - decode_block = Rb2OrImmDecode.subst(iop) - else: - decode_block = BasicDecode.subst(iop) + checkCode = "(!PstatePriv && TickNpt)" + (header_output, decoder_output, + exec_output, decode_block) = doPrivFormat(code, + checkCode, name, Name, opt_flags) }}; diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa index 935fbfe6b..5608548bd 100644 --- a/arch/sparc/isa/formats/trap.isa +++ b/arch/sparc/isa/formats/trap.isa @@ -27,7 +27,7 @@ output decoder {{ std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return "Trap instruction\n"; + return "Trap instruction"; } }}; @@ -36,6 +36,8 @@ def template TrapExecute {{ Trace::InstRecord *traceData) const { Fault fault = NoFault; + %(op_decl)s; + %(op_rd)s; %(code)s return fault; } @@ -44,7 +46,7 @@ def template TrapExecute {{ def format Trap(code, *opt_flags) {{ orig_code = code cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + iop = InstObjParams(name, Name, 'Trap', cblk, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) diff --git a/arch/sparc/isa/formats/unknown.isa b/arch/sparc/isa/formats/unknown.isa index eeb2b9496..223111905 100644 --- a/arch/sparc/isa/formats/unknown.isa +++ b/arch/sparc/isa/formats/unknown.isa @@ -29,7 +29,7 @@ output decoder {{ std::string Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return "Unknown instruction\n"; + return "Unknown instruction"; } }}; diff --git a/arch/sparc/isa/includes.isa b/arch/sparc/isa/includes.isa index c39fc2ef9..ff4174899 100644 --- a/arch/sparc/isa/includes.isa +++ b/arch/sparc/isa/includes.isa @@ -12,6 +12,7 @@ output header {{ #include "arch/sparc/faults.hh" #include "mem/request.hh" // some constructors use MemReq flags #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/regfile.hh" }}; output decoder {{ diff --git a/arch/sparc/isa/main.isa b/arch/sparc/isa/main.isa index ab0290d58..35167d6b7 100644 --- a/arch/sparc/isa/main.isa +++ b/arch/sparc/isa/main.isa @@ -26,7 +26,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -##include "m5/arch/sparc/isa/includes.isa" +##include "includes.isa" //////////////////////////////////////////////////////////////////// // @@ -37,16 +37,16 @@ namespace SparcISA; //Include the bitfield definitions -##include "m5/arch/sparc/isa/bitfields.isa" +##include "bitfields.isa" //Include the operand_types and operand definitions -##include "m5/arch/sparc/isa/operands.isa" +##include "operands.isa" //Include the base class for sparc instructions, and some support code -##include "m5/arch/sparc/isa/base.isa" +##include "base.isa" //Include the definitions for the instruction formats -##include "m5/arch/sparc/isa/formats.isa" +##include "formats.isa" //Include the decoder definition -##include "m5/arch/sparc/isa/decoder.isa" +##include "decoder.isa" diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa index abfdf7bcd..17e58ad59 100644 --- a/arch/sparc/isa/operands.isa +++ b/arch/sparc/isa/operands.isa @@ -16,18 +16,22 @@ def operands {{ # Int regs default to unsigned, but code should not count on this. # For clarity, descriptions that depend on unsigned behavior should # explicitly specify '.uq'. - 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), - 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2), - 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3), + 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), + 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), + 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), + 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), + 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), - 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), - #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), + 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), + 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 4), + 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 4), #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), - 'R0': ('IntReg', 'udw', '0', None, 1), - 'R16': ('IntReg', 'udw', '16', None, 1), + 'R0': ('IntReg', 'udw', '0', None, 6), + 'R15': ('IntReg', 'udw', '15', 'IsInteger', 7), + 'R16': ('IntReg', 'udw', '16', None, 8), # Control registers 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1), 'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2), @@ -55,7 +59,7 @@ def operands {{ 'CcrXccC': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22), 'CcrXccV': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23), 'CcrXccZ': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24), - 'CcrXccN': ('ControlReg', 'udw', 'MISCREG_XCC_N', None, 25), + 'CcrXccN': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_N', None, 25), 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26), 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27), #'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28), diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh index 4886da7cf..57206c5e5 100644 --- a/arch/sparc/isa_traits.hh +++ b/arch/sparc/isa_traits.hh @@ -90,6 +90,9 @@ namespace SparcISA // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) FP_Base_DepTag = 32, Ctrl_Base_DepTag = 96, + //XXX These are here solely to get compilation and won't work + Fpcr_DepTag = 0, + Uniq_DepTag = 0 }; //This makes sure the big endian versions of certain functions are used. @@ -98,11 +101,6 @@ namespace SparcISA typedef uint32_t MachInst; typedef uint64_t ExtMachInst; - inline ExtMachInst - makeExtMI(MachInst inst, const Addr &pc) { - return ExtMachInst(inst); - } - const int NumIntRegs = 32; const int NumFloatRegs = 64; const int NumMiscRegs = 32; @@ -121,12 +119,12 @@ namespace SparcISA const int ArgumentReg4 = 12; const int ArgumentReg5 = 13; const int SyscallNumReg = 1; - // Some OS syscall sue a second register (o1) to return a second value + // Some OS syscall use a second register (o1) to return a second value const int SyscallPseudoReturnReg = ArgumentReg1; //XXX These numbers are bogus - const int MaxInstSrcRegs = 3; - const int MaxInstDestRegs = 2; + const int MaxInstSrcRegs = 8; + const int MaxInstDestRegs = 3; typedef uint64_t IntReg; @@ -160,31 +158,6 @@ namespace SparcISA // return a no-op instruction... used for instruction fetch faults extern const MachInst NoopMachInst; - - // Instruction address compression hooks - inline Addr realPCToFetchPC(const Addr &addr) - { - return addr; - } - - inline Addr fetchPCToRealPC(const Addr &addr) - { - return addr; - } - - // the size of "fetched" instructions (not necessarily the size - // of real instructions for PISA) - inline size_t fetchInstSize() - { - return sizeof(MachInst); - } - - /** - * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. - */ - template <class XC> - void zeroRegisters(XC *xc); } #include "arch/sparc/regfile.hh" @@ -201,12 +174,12 @@ namespace SparcISA // and put the return value itself in the standard return value reg (). if (return_value.successful()) { // no error - regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 0); - regs->intRegFile[ReturnValueReg] = return_value.value(); + regs->setMiscReg(MISCREG_CCR_ICC_C, 0); + regs->setIntReg(ReturnValueReg, return_value.value()); } else { // got an error, return details - regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 1); - regs->intRegFile[ReturnValueReg] = -return_value.value(); + regs->setMiscReg(MISCREG_CCR_ICC_C, 1); + regs->setIntReg(ReturnValueReg, return_value.value()); } } #endif diff --git a/arch/sparc/linux/process.cc b/arch/sparc/linux/process.cc index cb056eadc..c7e5f79ca 100644 --- a/arch/sparc/linux/process.cc +++ b/arch/sparc/linux/process.cc @@ -356,9 +356,9 @@ SparcLinuxProcess::SparcLinuxProcess(const std::string &name, stdin_fd, stdout_fd, stderr_fd, argv, envp), Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) { - // The sparc syscall table must be <= 283 entries because that is all there + // The sparc syscall table must be <= 284 entries because that is all there // is space for. - assert(Num_Syscall_Descs <= 283); + assert(Num_Syscall_Descs <= 284); } diff --git a/arch/sparc/regfile.hh b/arch/sparc/regfile.hh index 944fdfe80..566cd1d1f 100644 --- a/arch/sparc/regfile.hh +++ b/arch/sparc/regfile.hh @@ -30,6 +30,7 @@ #define __ARCH_SPARC_REGFILE_HH__ #include "arch/sparc/faults.hh" +#include "base/trace.hh" #include "sim/byteswap.hh" #include "sim/host.hh" @@ -40,11 +41,112 @@ namespace SparcISA typedef uint8_t RegIndex; - // Maximum trap level + // MAXTL - maximum trap level const int MaxTL = 4; - //For right now, let's pretend the register file is flat - typedef IntReg IntRegFile[NumIntRegs]; + // NWINDOWS - number of register windows, can be 3 to 32 + const int NWindows = 6; + + class IntRegFile + { + protected: + static const int FrameOffsetBits = 3; + static const int FrameNumBits = 2; + + static const int RegsPerFrame = 1 << FrameOffsetBits; + static const int FrameNumMask = + (FrameNumBits == sizeof(int)) ? + (unsigned int)(-1) : + (1 << FrameNumBits) - 1; + static const int FrameOffsetMask = + (FrameOffsetBits == sizeof(int)) ? + (unsigned int)(-1) : + (1 << FrameOffsetBits) - 1; + + IntReg regGlobals[RegsPerFrame]; + IntReg altGlobals[RegsPerFrame]; + IntReg regSegments[2 * NWindows][RegsPerFrame]; + + enum regFrame {Globals, Outputs, Locals, Inputs, NumFrames}; + + IntReg * regView[NumFrames]; + + static const int RegGlobalOffset = 0; + static const int AltGlobalOffset = 8; + static const int FrameOffset = 16; + int offset[NumFrames]; + + public: + + int flattenIndex(int reg) + { + int flatIndex = offset[reg >> FrameOffsetBits] + | (reg & FrameOffsetMask); + DPRINTF(Sparc, "Flattened index %d into %d.\n", reg, flatIndex); + return flatIndex; + } + + void clear() + { + bzero(regGlobals, sizeof(regGlobals)); + bzero(altGlobals, sizeof(altGlobals)); + for(int x = 0; x < 2 * NWindows; x++) + bzero(regSegments[x], sizeof(regSegments[x])); + } + + IntRegFile() + { + offset[Globals] = 0; + regView[Globals] = regGlobals; + setCWP(0); + clear(); + } + + IntReg readReg(int intReg) + { + IntReg val = + regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask]; + DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val); + return val; + } + + Fault setReg(int intReg, const IntReg &val) + { + if(intReg) + DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val); + regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val; + return NoFault; + } + + //This doesn't effect the actual CWP register. + //It's purpose is to adjust the view of the register file + //to what it would be if CWP = cwp. + void setCWP(int cwp) + { + int index = ((NWindows - cwp) % NWindows) * 2; + offset[Outputs] = FrameOffset + (index * RegsPerFrame); + offset[Locals] = FrameOffset + ((index+1) * RegsPerFrame); + offset[Inputs] = FrameOffset + + (((index+2) % (NWindows * 2)) * RegsPerFrame); + regView[Outputs] = regSegments[index]; + regView[Locals] = regSegments[index+1]; + regView[Inputs] = regSegments[(index+2) % (NWindows * 2)]; + + DPRINTF(Sparc, "Changed the CWP value to %d\n", cwp); + } + + void setAltGlobals(bool useAlt) + { + DPRINTF(Sparc, "Now using %s globals", + useAlt ? "alternate" : "regular"); + regView[Globals] = useAlt ? altGlobals : regGlobals; + offset[Globals] = useAlt ? AltGlobalOffset : RegGlobalOffset; + } + + void serialize(std::ostream &os); + + void unserialize(Checkpoint *cp, const std::string §ion); + }; typedef float float32_t; typedef double float64_t; @@ -54,18 +156,25 @@ namespace SparcISA class FloatRegFile { + public: + static const int SingleWidth = 32; + static const int DoubleWidth = 64; + static const int QuadWidth = 128; + protected: + //Since the floating point registers overlap each other, //A generic storage space is used. The float to be returned is //pulled from the appropriate section of this region. - char regSpace[32 * 64]; - - static const int SingleWidth = 32; - static const int DoubleWidth = 64; - static const int QuadWidth = 128; + char regSpace[SingleWidth / 8 * NumFloatRegs]; public: + void clear() + { + bzero(regSpace, sizeof(regSpace)); + } + FloatReg readReg(int floatReg, int width) { //In each of these cases, we have to copy the value into a temporary @@ -90,12 +199,6 @@ namespace SparcISA } } - FloatReg readReg(int floatReg) - { - //Use the "natural" width of a single float - return readReg(floatReg, SingleWidth); - } - FloatRegBits readRegBits(int floatReg, int width) { //In each of these cases, we have to copy the value into a temporary @@ -120,12 +223,6 @@ namespace SparcISA } } - FloatRegBits readRegBits(int floatReg) - { - //Use the "natural" width of a single float - return readRegBits(floatReg, SingleWidth); - } - Fault setReg(int floatReg, const FloatReg &val, int width) { //In each of these cases, we have to copy the value into a temporary @@ -148,12 +245,6 @@ namespace SparcISA return NoFault; } - Fault setReg(int floatReg, const FloatReg &val) - { - //Use the "natural" width of a single float - return setReg(floatReg, val, SingleWidth); - } - Fault setRegBits(int floatReg, const FloatRegBits &val, int width) { //In each of these cases, we have to copy the value into a temporary @@ -176,12 +267,6 @@ namespace SparcISA return NoFault; } - Fault setRegBits(int floatReg, const FloatRegBits &val) - { - //Use the "natural" width of a single float - return setReg(floatReg, val, SingleWidth); - } - void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); @@ -474,14 +559,59 @@ namespace SparcISA }; public: + + void reset() + { + pstateFields.pef = 0; //No FPU + //pstateFields.pef = 1; //FPU +#if FULL_SYSTEM + //For SPARC, when a system is first started, there is a power + //on reset Trap which sets the processor into the following state. + //Bits that aren't set aren't defined on startup. + tl = MaxTL; + tt[tl] = PowerOnReset.trapType(); + pstateFields.mm = 0; //Total Store Order + pstateFields.red = 1; //Enter RED_State + pstateFields.am = 0; //Address Masking is turned off + pstateFields.priv = 1; //Processor enters privileged mode + pstateFields.ie = 0; //Interrupts are disabled + pstateFields.ag = 1; //Globals are replaced with alternate globals + pstateFields.tle = 0; //Big Endian mode for traps + pstateFields.cle = 0; //Big Endian mode for non-traps + tickFields.npt = 1; //The TICK register is unreadable by + //non-priveleged software +#else + //This sets up the initial state of the processor for usermode processes + pstateFields.priv = 0; //Process runs in user mode + pstateFields.ie = 1; //Interrupts are enabled + fsrFields.rd = 0; //Round to nearest + fsrFields.tem = 0; //Floating point traps not enabled + fsrFields.ns = 0; //Non standard mode off + fsrFields.qne = 0; //Floating point queue is empty + fsrFields.aexc = 0; //No accrued exceptions + fsrFields.cexc = 0; //No current exceptions + + //Register window management registers + otherwin = 0; //No windows contain info from other programs + canrestore = 0; //There are no windows to pop + cansave = MaxTL - 2; //All windows are available to save into + cleanwin = MaxTL; +#endif + } + + MiscRegFile() + { + reset(); + } + MiscReg readReg(int miscReg); MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc); Fault setReg(int miscReg, const MiscReg &val); - Fault setRegWithEffect(int miscReg, const MiscReg &val, - ExecContext *xc); + Fault setRegWithEffect(int miscReg, + const MiscReg &val, ExecContext * xc); void serialize(std::ostream & os); @@ -497,18 +627,171 @@ namespace SparcISA MiscReg ctrlreg; } AnyReg; - struct RegFile + class RegFile { - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegs; // control register file - + protected: Addr pc; // Program Counter Addr npc; // Next Program Counter Addr nnpc; + public: + Addr readPC() + { + return pc; + } + + void setPC(Addr val) + { + pc = val; + } + + Addr readNextPC() + { + return npc; + } + + void setNextPC(Addr val) + { + npc = val; + } + + Addr readNextNPC() + { + return nnpc; + } + + void setNextNPC(Addr val) + { + nnpc = val; + } + + protected: + IntRegFile intRegFile; // integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegFile; // control register file + + public: + + void clear() + { + intRegFile.clear(); + floatRegFile.clear(); + } + + int flattenIntIndex(int reg) + { + return intRegFile.flattenIndex(reg); + } + + MiscReg readMiscReg(int miscReg) + { + return miscRegFile.readReg(miscReg); + } + + MiscReg readMiscRegWithEffect(int miscReg, + Fault &fault, ExecContext *xc) + { + return miscRegFile.readRegWithEffect(miscReg, fault, xc); + } + + Fault setMiscReg(int miscReg, const MiscReg &val) + { + return miscRegFile.setReg(miscReg, val); + } + + Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, + ExecContext * xc) + { + return miscRegFile.setRegWithEffect(miscReg, val, xc); + } + + FloatReg readFloatReg(int floatReg, int width) + { + return floatRegFile.readReg(floatReg, width); + } + + FloatReg readFloatReg(int floatReg) + { + //Use the "natural" width of a single float + return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth); + } + + FloatRegBits readFloatRegBits(int floatReg, int width) + { + return floatRegFile.readRegBits(floatReg, width); + } + + FloatRegBits readFloatRegBits(int floatReg) + { + //Use the "natural" width of a single float + return floatRegFile.readRegBits(floatReg, + FloatRegFile::SingleWidth); + } + + Fault setFloatReg(int floatReg, const FloatReg &val, int width) + { + return floatRegFile.setReg(floatReg, val, width); + } + + Fault setFloatReg(int floatReg, const FloatReg &val) + { + //Use the "natural" width of a single float + return setFloatReg(floatReg, val, FloatRegFile::SingleWidth); + } + + Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width) + { + return floatRegFile.setRegBits(floatReg, val, width); + } + + Fault setFloatRegBits(int floatReg, const FloatRegBits &val) + { + //Use the "natural" width of a single float + return floatRegFile.setRegBits(floatReg, val, + FloatRegFile::SingleWidth); + } + + IntReg readIntReg(int intReg) + { + return intRegFile.readReg(intReg); + } + + Fault setIntReg(int intReg, const IntReg &val) + { + return intRegFile.setReg(intReg, val); + } + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); + + public: + + enum ContextParam + { + CONTEXT_CWP, + CONTEXT_GLOBALS + }; + + union ContextVal + { + MiscReg reg; + bool altGlobals; + }; + + void changeContext(ContextParam param, ContextVal val) + { + switch(param) + { + case CONTEXT_CWP: + intRegFile.setCWP(val.reg); + break; + case CONTEXT_GLOBALS: + intRegFile.setAltGlobals(val.altGlobals); + break; + default: + panic("Tried to set illegal context parameter in the SPARC regfile.\n"); + } + } }; void copyRegs(ExecContext *src, ExecContext *dest); diff --git a/arch/sparc/utility.hh b/arch/sparc/utility.hh new file mode 100644 index 000000000..1e67b3370 --- /dev/null +++ b/arch/sparc/utility.hh @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_SPARC_UTILITY_HH__ +#define __ARCH_SPARC_UTILITY_HH__ + +#include "arch/sparc/isa_traits.hh" +#include "base/misc.hh" + +namespace SparcISA +{ + inline ExtMachInst + makeExtMI(MachInst inst, const Addr &pc) { + return ExtMachInst(inst); + } + + inline bool isCallerSaveIntegerRegister(unsigned int reg) { + panic("register classification not implemented"); + return false; + } + + inline bool isCalleeSaveIntegerRegister(unsigned int reg) { + panic("register classification not implemented"); + return false; + } + + inline bool isCallerSaveFloatRegister(unsigned int reg) { + panic("register classification not implemented"); + return false; + } + + inline bool isCalleeSaveFloatRegister(unsigned int reg) { + panic("register classification not implemented"); + return false; + } + + // Instruction address compression hooks + inline Addr realPCToFetchPC(const Addr &addr) + { + return addr; + } + + inline Addr fetchPCToRealPC(const Addr &addr) + { + return addr; + } + + // the size of "fetched" instructions (not necessarily the size + // of real instructions for PISA) + inline size_t fetchInstSize() + { + return sizeof(MachInst); + } + + /** + * Function to insure ISA semantics about 0 registers. + * @param xc The execution context. + */ + template <class XC> + void zeroRegisters(XC *xc); + +} // namespace SparcISA + +#endif |