diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/SConscript | 1 | ||||
| -rw-r--r-- | arch/alpha/ev5.cc | 12 | ||||
| -rw-r--r-- | arch/alpha/isa_traits.hh | 5 | ||||
| -rw-r--r-- | arch/sparc/isa_traits.hh | 14 |
4 files changed, 29 insertions, 3 deletions
diff --git a/arch/SConscript b/arch/SConscript index 380cda307..0533261a2 100644 --- a/arch/SConscript +++ b/arch/SConscript @@ -52,7 +52,6 @@ isa_switch_hdrs = Split(''' stacktrace.hh vtophys.hh faults.hh - ev5.hh ''') # Generate the header. target[0] is the full path of the output diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index e313c1a1c..47ada6de6 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -152,6 +152,18 @@ ExecContext::hwrei() return NoFault; } +int +AlphaISA::MiscRegFile::getInstAsid() +{ + return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); +} + +int +AlphaISA::MiscRegFile::getDataAsid() +{ + return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); +} + void AlphaISA::MiscRegFile::clearIprs() { diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 742539e89..be6d5111d 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -166,6 +166,11 @@ extern const int reg_redir[NumIntRegs]; public: MiscReg readReg(int misc_reg); + //These functions should be removed once the simplescalar cpu model + //has been replaced. + int getInstAsid(); + int getDataAsid(); + MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); Fault setReg(int misc_reg, const MiscReg &val); diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh index 0fdac1662..73daae8a9 100644 --- a/arch/sparc/isa_traits.hh +++ b/arch/sparc/isa_traits.hh @@ -57,7 +57,7 @@ class StaticInstPtr; namespace SparcISA { typedef uint32_t MachInst; - typedef uint64_t Addr; + typedef uint64_t ExtMachInst; typedef uint8_t RegIndex; enum @@ -179,7 +179,7 @@ namespace SparcISA // The control registers, broken out into fields class MiscRegFile { - public: + private: union { uint16_t pstate; // Process State Register @@ -365,6 +365,16 @@ namespace SparcISA } fprsFields; }; + public: + MiscReg readReg(int misc_reg); + + MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); + + Fault setReg(int misc_reg, const MiscReg &val); + + Fault setRegWithEffect(int misc_reg, const MiscReg &val, + ExecContext *xc); + void serialize(std::ostream & os); void unserialize(Checkpoint * cp, std::string & section); |