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-rw-r--r--arch/mips/isa/decoder.isa179
-rw-r--r--arch/mips/isa/formats.isa21
-rw-r--r--arch/mips/isa/formats/basic.isa2
-rw-r--r--arch/mips/isa/formats/branch.isa273
-rw-r--r--arch/mips/isa/formats/fp.isa27
-rw-r--r--arch/mips/isa/formats/int.isa4
-rw-r--r--arch/mips/isa/formats/mem.isa2
-rw-r--r--arch/mips/isa/formats/noop.isa87
-rw-r--r--arch/mips/isa/formats/unimp.isa165
-rw-r--r--arch/mips/isa/formats/unknown.isa52
-rw-r--r--arch/mips/isa/main.isa12
-rw-r--r--arch/mips/isa/operands.isa6
12 files changed, 680 insertions, 150 deletions
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index 2ec7da805..6bb5bf4d8 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -9,7 +9,7 @@
//
//@todo: Distinguish "unknown/future" use insts from "reserved"
// ones
-decode OPCODE_HI default FailUnimpl::unknown() {
+decode OPCODE_HI default Unknown::unknown() {
// Derived From ... Table A-2 MIPS32 ISA Manual
0x0: decode OPCODE_LO default FailUnimpl::reserved(){
@@ -66,10 +66,11 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x3: movn({{ if (Rt != 0) Rd = Rs; }});
}
+
format WarnUnimpl {
- 0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
- 0x5: break({{ }});
- 0x7: sync({{ }});
+ 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative
+ 0x5: break();
+ 0x7: sync();
}
}
@@ -80,14 +81,14 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x2: mflo({{ Rd = xc->miscRegs.lo; }});
0x3: mtlo({{ xc->miscRegs.lo = Rs; }});
}
- };
+ }
0x3: decode FUNCTION_LO {
format IntOp {
0x0: mult({{
INT64 temp1 = Rs.sw * Rt.sw;
xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>
+ xc->miscRegs.lo->temp1<31:0>;
}});
0x1: multu({{
@@ -107,7 +108,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
xc->miscRegs.lo = Rs.uw / Rt.uw;
}});
}
- };
+ }
0x4: decode FUNCTION_LO {
format IntOp {
@@ -127,7 +128,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
}
- };
+ }
0x6: decode FUNCTION_LO {
format Trap {
@@ -143,13 +144,13 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode REGIMM_HI {
0x0: decode REGIMM_LO {
- format Branch {
- 0x0: bltz({{ cond = (Rs.sq < 0); }});
- 0x1: bgez({{ cond = (Rs.sq >= 0); }});
+ format CondBranch {
+ 0x0: bltz({{ cond = (Rs.sw < 0); }});
+ 0x1: bgez({{ cond = (Rs.sw >= 0); }});
//MIPS obsolete instructions
- 0x2: bltzl({{ cond = (Rs.sq < 0); }});
- 0x3: bgezl({{ cond = (Rs.sq >= 0); }});
+ 0x2: bltzl({{ cond = (Rs.sw < 0); }});
+ 0x3: bgezl({{ cond = (Rs.sw >= 0); }});
}
}
@@ -165,19 +166,19 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}
0x2: decode REGIMM_LO {
- format Branch {
- 0x0: bltzal({{ cond = (Rs.sq < 0); }});
- 0x1: bgezal({{ cond = (Rs.sq >= 0); }});
+ format CondBranch {
+ 0x0: bltzal({{ cond = (Rs.sw < 0); }});
+ 0x1: bgezal({{ cond = (Rs.sw >= 0); }});
//MIPS obsolete instructions
- 0x2: bltzall({{ cond = (Rs.sq < 0); }});
- 0x3: bgezall({{ cond = (Rs.sq >= 0); }});
+ 0x2: bltzall({{ cond = (Rs.sw < 0); }});
+ 0x3: bgezall({{ cond = (Rs.sw >= 0); }});
}
}
0x3: decode REGIMM_LO {
format WarnUnimpl {
- 0x7: synci({{ }});
+ 0x7: synci();
}
}
}
@@ -187,13 +188,13 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x3: jal(IsCall);
}
- format Branch {
- 0x4: beq({{ cond = (Rs.sq == 0); }});
- 0x5: bne({{ cond = (Rs.sq != 0); }});
- 0x6: blez({{ cond = (Rs.sq <= 0); }});
- 0x7: bgtz({{ cond = (Rs.sq > 0); }});
+ format CondBranch {
+ 0x4: beq({{ cond = (Rs.sw == 0); }});
+ 0x5: bne({{ cond = (Rs.sw != 0); }});
+ 0x6: blez({{ cond = (Rs.sw <= 0); }});
+ 0x7: bgtz({{ cond = (Rs.sw > 0); }});
}
- };
+ }
0x1: decode OPCODE_LO default FailUnimpl::reserved(){
format IntOp {
@@ -205,8 +206,8 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
0x7: lui({{ Rt = INTIMM << 16}});
- };
- };
+ }
+ }
0x2: decode OPCODE_LO default FailUnimpl::reserved(){
@@ -335,9 +336,9 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}
format WarnUnimpl {
- 0x18: eret({{ }});
- 0x1F: deret({{ }});
- 0x20: wait({{ }});
+ 0x18: eret();
+ 0x1F: deret();
+ 0x20: wait();
}
}
}
@@ -359,14 +360,14 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode ND {
0x0: decode TF {
- format Branch {
+ format CondBranch {
0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
}
}
0x1: decode TF {
- format Branch {
+ format CondBranch {
0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
}
@@ -394,7 +395,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}
0x1: decode RS_LO {
- //only legal for 64 bit
+ //only legal for 64 bit-FP
format Float64Op {
0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}});
0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}});
@@ -425,18 +426,21 @@ decode OPCODE_HI default FailUnimpl::unknown() {
format Float64Op {
0x2: recips({{ Fd = 1 / Fs; }});
- 0x3: rsqrts{{ Fd = 1 / sqrt(Fs); }});
+ 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}});
}
}
0x4: decode RS_LO {
- 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr;
+
+ format FloatOp {
+ 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
}});
- 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
}});
+ }
//only legal for 64 bit
format Float64Op {
@@ -466,7 +470,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode RS_LO {
//only legal for 64 bit
- format FloatOp64 {
+ format Float64Op {
0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}});
0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}});
@@ -494,9 +498,9 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }});
}
- format FloatOp64 {
+ format Float64Op {
0x5: recipd({{ Fd.df = 1 / Fs.df}});
- 0x6: rsqrtd{{ Fd.df = 1 / sqrt(Fs.df) }});
+ 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }});
}
}
@@ -514,7 +518,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}
//only legal for 64 bit
- format FloatOp64 {
+ format Float64Op {
0x5: cvt_l_d({{
int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
@@ -560,7 +564,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
//are enabled. "
0x6: decode RS_HI {
0x0: decode RS_LO {
- format FloatOp64 {
+ format Float64Op {
0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
Fd.df = Fs.df + Ft.df;
@@ -595,23 +599,23 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x2: decode RS_LO {
0x1: decode MOVCF {
- format FloatOp64 {
- 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}})
- 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}})
+ format Float64Op {
+ 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
+ 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
}
}
}
0x4: decode RS_LO {
- 0x0: FloatOp64::cvt_s_pu({{
+ 0x0: Float64Op::cvt_s_pu({{
int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI);
}});
}
0x5: decode RS_LO {
- format FloatOp64 {
+ format Float64Op {
0x0: cvt_s_pl({{
int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
@@ -630,27 +634,27 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x0: decode RS_HI {
0x0: decode RS_LO {
format WarnUnimpl {
- 0x0: mfc2({{ }});
- 0x2: cfc2({{ }});
- 0x3: mfhc2({{ }});
- 0x4: mtc2({{ }});
- 0x6: ctc2({{ }});
- 0x7: mftc2({{ }});
+ 0x0: mfc2();
+ 0x2: cfc2();
+ 0x3: mfhc2();
+ 0x4: mtc2();
+ 0x6: ctc2();
+ 0x7: mftc2();
}
}
0x1: decode ND {
0x0: decode TF {
format WarnUnimpl {
- 0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
- 0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
+ 0x0: bc2f();
+ 0x1: bc2t();
}
}
0x1: decode TF {
format WarnUnimpl {
- 0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
- 0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
+ 0x0: bc2fl();
+ 0x1: bc2tl();
}
}
}
@@ -680,12 +684,13 @@ decode OPCODE_HI default FailUnimpl::unknown() {
EA = Rs + Rt;
}},
{{ Mem.df = Ft<63:0>;}});
- 0x7: prefx({{ }});
}
+
+ 0x7: WarnUnimpl::prefx();
}
format FloatOp {
- 0x3: WarnUnimpl::alnv_ps({{ }});
+ 0x3: WarnUnimpl::alnv_ps();
format BasicOp {
0x4: decode FUNCTION_LO {
@@ -732,13 +737,13 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}
//MIPS obsolete instructions
- format Branch {
- 0x4: beql({{ cond = (Rs.sq == 0); }});
- 0x5: bnel({{ cond = (Rs.sq != 0); }});
- 0x6: blezl({{ cond = (Rs.sq <= 0); }});
- 0x7: bgtzl({{ cond = (Rs.sq > 0); }});
+ format CondBranch {
+ 0x4: beql({{ cond = (Rs.sw == 0); }});
+ 0x5: bnel({{ cond = (Rs.sw != 0); }});
+ 0x6: blezl({{ cond = (Rs.sw <= 0); }});
+ 0x7: bgtzl({{ cond = (Rs.sw > 0); }});
}
- };
+ }
0x3: decode OPCODE_LO default FailUnimpl::reserved() {
@@ -806,7 +811,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}
0x7: decode FUNCTION_LO {
- 0x7: WarnUnimpl::sdbbp({{ }});
+ 0x7: WarnUnimpl::sdbbp();
}
}
@@ -815,15 +820,15 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x0: decode FUNCTION_LO {
format WarnUnimpl {
- 0x1: ext({{ }});
- 0x4: ins({{ }});
+ 0x1: ext();
+ 0x4: ins();
}
}
0x1: decode FUNCTION_LO {
format WarnUnimpl {
- 0x0: fork({{ }});
- 0x1: yield({{ }});
+ 0x0: fork();
+ 0x1: yield();
}
}
@@ -831,7 +836,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
//Table A-10 MIPS32 BSHFL Encoding of sa Field
0x4: decode SA {
- 0x02: WarnUnimpl::wsbh({{ }});
+ 0x02: WarnUnimpl::wsbh();
format BasicOp {
0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}});
@@ -843,53 +848,53 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}});
}
}
- };
+ }
0x4: decode OPCODE_LO default FailUnimpl::reserved() {
format Memory {
0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }});
0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }});
- 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign);
+ 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }});//, WordAlign);
0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }});
0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }});
0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }});
- 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign);
- };
+ 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }});//, WordAlign);
+ }
- 0x7: FailUnimpl::reserved({{ }});
- };
+ 0x7: FailUnimpl::reserved();
+ }
0x5: decode OPCODE_LO default FailUnimpl::reserved() {
format Memory {
0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }});
0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }});
- 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
+ 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign);
0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});
- 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
- };
+ 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign);
+ }
format WarnUnimpl {
- 0x7: cache({{ }});
- };
+ 0x7: cache();
+ }
- };
+ }
0x6: decode OPCODE_LO default FailUnimpl::reserved() {
- 0x0: WarnUnimpl::ll({{ }});
+ 0x0: WarnUnimpl::ll();
format Memory {
0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
- };
- };
+ }
+ }
0x7: decode OPCODE_LO default FailUnimpl::reserved() {
- 0x0: WarnUnimpl::sc({{ }});
+ 0x0: WarnUnimpl::sc();
format Memory {
0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
- };
+ }
}
}
diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa
index 404314c7a..20ef49d82 100644
--- a/arch/mips/isa/formats.isa
+++ b/arch/mips/isa/formats.isa
@@ -1,22 +1,29 @@
//Include the basic format
//Templates from this format are used later
-##include "m5/arch/mips/isa_desc/formats/basic.format"
+##include "m5/arch/mips/isa/formats/basic.isa"
//Include the integerOp and integerOpCc format
-##include "m5/arch/mips/isa_desc/formats/integerop.format"
+##include "m5/arch/mips/isa/formats/int.isa"
//Include the floatOp format
-##include "m5/arch/mips/isa_desc/formats/floatop.format"
+##include "m5/arch/mips/isa/formats/fp.isa"
//Include the mem format
-##include "m5/arch/mips/isa_desc/formats/mem.format"
+##include "m5/arch/mips/isa/formats/mem.isa"
//Include the trap format
-##include "m5/arch/mips/isa_desc/formats/trap.format"
+##include "m5/arch/mips/isa/formats/trap.isa"
//Include the branch format
-##include "m5/arch/mips/isa_desc/formats/branch.format"
+##include "m5/arch/mips/isa/formats/branch.isa"
//Include the noop format
-##include "m5/arch/mips/isa_desc/formats/noop.format"
+##include "m5/arch/mips/isa/formats/noop.isa"
+
+
+//Include the noop format
+##include "m5/arch/mips/isa/formats/unimp.isa"
+
+//Include the noop format
+##include "m5/arch/mips/isa/formats/unknown.isa"
diff --git a/arch/mips/isa/formats/basic.isa b/arch/mips/isa/formats/basic.isa
index 8fba9845a..fc97c6ffa 100644
--- a/arch/mips/isa/formats/basic.isa
+++ b/arch/mips/isa/formats/basic.isa
@@ -56,7 +56,7 @@ def template BasicDecodeWithMnemonic {{
}};
// The most basic instruction format... used only for a few misc. insts
-def format BasicOperate(code, *flags) {{
+def format BasicOp(code, *flags) {{
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
index a565eb71b..e9c790c53 100644
--- a/arch/mips/isa/formats/branch.isa
+++ b/arch/mips/isa/formats/branch.isa
@@ -1,57 +1,212 @@
-////////////////////////////////////////////////////////////////////
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
//
-// Branch instructions
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{
- /**
- * Base class for integer operations.
- */
- class Branch : public MipsStaticInst
+
+ /**
+ * Base class for instructions whose disassembly is not purely a
+ * function of the machine instruction (i.e., it depends on the
+ * PC). This class overrides the disassemble() method to check
+ * the PC and symbol table values before re-using a cached
+ * disassembly string. This is necessary for branches and jumps,
+ * where the disassembly string includes the target address (which
+ * may depend on the PC and/or symbol table).
+ */
+ class PCDependentDisassembly : public AlphaStaticInst
+ {
+ protected:
+ /// Cached program counter from last disassembly
+ mutable Addr cachedPC;
+ /// Cached symbol table pointer from last disassembly
+ mutable const SymbolTable *cachedSymtab;
+
+ /// Constructor
+ PCDependentDisassembly(const char *mnem, MachInst _machInst,
+ OpClass __opClass)
+ : AlphaStaticInst(mnem, _machInst, __opClass),
+ cachedPC(0), cachedSymtab(0)
{
- protected:
+ }
- /// Constructor
- Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
- {
- }
+ const std::string &
+ disassemble(Addr pc, const SymbolTable *symtab) const;
+ };
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
-}};
+ /**
+ * Base class for branches (PC-relative control transfers),
+ * conditional or unconditional.
+ */
+ class Branch : public PCDependentDisassembly
+ {
+ protected:
+ /// Displacement to target address (signed).
+ int32_t disp;
-output decoder {{
- std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ /// Constructor.
+ Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : PCDependentDisassembly(mnem, _machInst, __opClass),
+ disp(BRDISP << 2)
+ {
+ }
+
+ Addr branchTarget(Addr branchPC) const;
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Base class for jumps (register-indirect control transfers). In
+ * the Alpha ISA, these are always unconditional.
+ */
+ class Jump : public PCDependentDisassembly
+ {
+ protected:
+
+ /// Displacement to target address (signed).
+ int32_t disp;
+
+ public:
+ /// Constructor
+ Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : PCDependentDisassembly(mnem, _machInst, __opClass),
+ disp(BRDISP)
{
- return "Disassembly of integer instruction\n";
}
+
+ Addr branchTarget(ExecContext *xc) const;
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
}};
-def template BranchExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+output decoder {{
+ Addr
+ Branch::branchTarget(Addr branchPC) const
+ {
+ return branchPC + 4 + disp;
+ }
+
+ Addr
+ Jump::branchTarget(ExecContext *xc) const
+ {
+ Addr NPC = xc->readPC() + 4;
+ uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
+ return (Rb & ~3) | (NPC & 1);
+ }
+
+ const std::string &
+ PCDependentDisassembly::disassemble(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ if (!cachedDisassembly ||
+ pc != cachedPC || symtab != cachedSymtab)
{
- //Attempt to execute the instruction
- try
- {
- checkPriv;
-
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
- }
- //If we have an exception for some reason,
- //deal with it
- catch(MipsException except)
- {
- //Deal with exception
- return No_Fault;
- }
-
- //Write the resulting state to the execution context
- %(op_wb)s;
-
- return No_Fault;
+ if (cachedDisassembly)
+ delete cachedDisassembly;
+
+ cachedDisassembly =
+ new std::string(generateDisassembly(pc, symtab));
+ cachedPC = pc;
+ cachedSymtab = symtab;
+ }
+
+ return *cachedDisassembly;
+ }
+
+ std::string
+ Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ // There's only one register arg (RA), but it could be
+ // either a source (the condition for conditional
+ // branches) or a destination (the link reg for
+ // unconditional branches)
+ if (_numSrcRegs > 0) {
+ printReg(ss, _srcRegIdx[0]);
+ ss << ",";
+ }
+ else if (_numDestRegs > 0) {
+ printReg(ss, _destRegIdx[0]);
+ ss << ",";
}
+
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+ if (_numSrcRegs == 0 && _numDestRegs == 0) {
+ printReg(ss, 31);
+ ss << ",";
+ }
+#endif
+
+ Addr target = pc + 4 + disp;
+
+ std::string str;
+ if (symtab && symtab->findSymbol(target, str))
+ ss << str;
+ else
+ ccprintf(ss, "0x%x", target);
+
+ return ss.str();
+ }
+
+ std::string
+ Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+ if (_numDestRegs == 0) {
+ printReg(ss, 31);
+ ss << ",";
+ }
+#endif
+
+ if (_numDestRegs > 0) {
+ printReg(ss, _destRegIdx[0]);
+ ss << ",";
+ }
+
+ ccprintf(ss, "(r%d)", RB);
+
+ return ss.str();
+ }
+}};
+
+def template JumpOrBranchDecode {{
+ return (RA == 31)
+ ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
+ : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
}};
def format CondBranch(code) {{
@@ -64,3 +219,41 @@ def format CondBranch(code) {{
exec_output = BasicExecute.subst(iop)
}};
+let {{
+def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
+ # Declare basic control transfer w/o link (i.e. link reg is R31)
+ nolink_code = 'NPC = %s;\n' % npc_expr
+ nolink_iop = InstObjParams(name, Name, base_class,
+ CodeBlock(nolink_code), flags)
+ header_output = BasicDeclare.subst(nolink_iop)
+ decoder_output = BasicConstructor.subst(nolink_iop)
+ exec_output = BasicExecute.subst(nolink_iop)
+
+ # Generate declaration of '*AndLink' version, append to decls
+ link_code = 'Ra = NPC & ~3;\n' + nolink_code
+ link_iop = InstObjParams(name, Name + 'AndLink', base_class,
+ CodeBlock(link_code), flags)
+ header_output += BasicDeclare.subst(link_iop)
+ decoder_output += BasicConstructor.subst(link_iop)
+ exec_output += BasicExecute.subst(link_iop)
+
+ # need to use link_iop for the decode template since it is expecting
+ # the shorter version of class_name (w/o "AndLink")
+
+ return (header_output, decoder_output,
+ JumpOrBranchDecode.subst(nolink_iop), exec_output)
+}};
+
+def format UncondBranch(*flags) {{
+ flags += ('IsUncondControl', 'IsDirectControl')
+ (header_output, decoder_output, decode_block, exec_output) = \
+ UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
+}};
+
+def format Jump(*flags) {{
+ flags += ('IsUncondControl', 'IsIndirectControl')
+ (header_output, decoder_output, decode_block, exec_output) = \
+ UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
+}};
+
+
diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa
index 707109fc2..23fcbaa67 100644
--- a/arch/mips/isa/formats/fp.isa
+++ b/arch/mips/isa/formats/fp.isa
@@ -27,7 +27,7 @@ output decoder {{
}
}};
-def template FPExecute {{
+def template FloatingPointExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
//These are set to constants when the execute method
@@ -70,7 +70,7 @@ def template FPExecute {{
}};
// Primary format for integer operate instructions:
-def format FPOp(code, *opt_flags) {{
+def format FloatOp(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
checkPriv = (code.find('checkPriv') != -1)
@@ -86,12 +86,33 @@ def format FPOp(code, *opt_flags) {{
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
- exec_output = IntegerExecute.subst(iop)
+ exec_output = FloatingPointExecute.subst(iop)
+}};
+
+// Primary format for integer operate instructions:
+def format Float64Op(code, *opt_flags) {{
+ orig_code = code
+ cblk = CodeBlock(code)
+ checkPriv = (code.find('checkPriv') != -1)
+ code.replace('checkPriv', '')
+ if checkPriv:
+ code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
+ else:
+ code.replace('checkPriv;', '')
+ for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
+ ('xvValue', '0'), ('xcValue', '0')):
+ code.replace(marker, value)
+ iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+ exec_output = FloatingPointExecute.subst(iop)
}};
// Primary format for integer operate instructions:
def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
orig_code = code
+
cblk = CodeBlock(code)
checkPriv = (code.find('checkPriv') != -1)
code.replace('checkPriv', '')
diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa
index 5b8df54e9..521f3a130 100644
--- a/arch/mips/isa/formats/int.isa
+++ b/arch/mips/isa/formats/int.isa
@@ -53,9 +53,9 @@ def format IntOp(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
- //Figure out if we are creating a IntImmOp or a IntOp
+ # Figure out if we are creating a IntImmOp or a IntOp
strlen = len(name)
- if ( name[strlen-1] = 'i' or ( name[strlen-2:] = 'iu'))
+ if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
else:
iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
index 5ed5237c5..e3028eb7c 100644
--- a/arch/mips/isa/formats/mem.isa
+++ b/arch/mips/isa/formats/mem.isa
@@ -55,7 +55,7 @@ def template MemExecute {{
}};
// Primary format for integer operate instructions:
-def format Mem(code, *opt_flags) {{
+def format Memory(code, ea_code = {{ EA = Rb + disp; }},*opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa
index b1ece654d..6d45ba9b6 100644
--- a/arch/mips/isa/formats/noop.isa
+++ b/arch/mips/isa/formats/noop.isa
@@ -45,3 +45,90 @@ def format Noop(code, *opt_flags) {{
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = NoopExecute.subst(iop)
}};
+
+////////////////////////////////////////////////////////////////////
+//
+// Nop
+//
+
+output header {{
+ /**
+ * Static instruction class for no-ops. This is a leaf class.
+ */
+ class Nop : public AlphaStaticInst
+ {
+ /// Disassembly of original instruction.
+ const std::string originalDisassembly;
+
+ public:
+ /// Constructor
+ Nop(const std::string _originalDisassembly, MachInst _machInst)
+ : AlphaStaticInst("nop", _machInst, No_OpClass),
+ originalDisassembly(_originalDisassembly)
+ {
+ flags[IsNop] = true;
+ }
+
+ ~Nop() { }
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+ %(BasicExecDeclare)s
+ };
+}};
+
+output decoder {{
+ std::string Nop::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+ return originalDisassembly;
+#else
+ return csprintf("%-10s (%s)", "nop", originalDisassembly);
+#endif
+ }
+
+ /// Helper function for decoding nops. Substitute Nop object
+ /// for original inst passed in as arg (and delete latter).
+ inline
+ AlphaStaticInst *
+ makeNop(AlphaStaticInst *inst)
+ {
+ AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
+ delete inst;
+ return nop;
+ }
+}};
+
+output exec {{
+ Fault
+ Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
+ {
+ return No_Fault;
+ }
+}};
+
+// integer & FP operate instructions use Rc as dest, so check for
+// Rc == 31 to detect nops
+def template OperateNopCheckDecode {{
+ {
+ AlphaStaticInst *i = new %(class_name)s(machInst);
+ if (RC == 31) {
+ i = makeNop(i);
+ }
+ return i;
+ }
+}};
+
+
+// Like BasicOperate format, but generates NOP if RC/FC == 31
+def format BasicOperateWithNopCheck(code, *opt_args) {{
+ iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
+ opt_args)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = OperateNopCheckDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
diff --git a/arch/mips/isa/formats/unimp.isa b/arch/mips/isa/formats/unimp.isa
new file mode 100644
index 000000000..767888157
--- /dev/null
+++ b/arch/mips/isa/formats/unimp.isa
@@ -0,0 +1,165 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+output header {{
+ /**
+ * Static instruction class for unimplemented instructions that
+ * cause simulator termination. Note that these are recognized
+ * (legal) instructions that the simulator does not support; the
+ * 'Unknown' class is used for unrecognized/illegal instructions.
+ * This is a leaf class.
+ */
+ class FailUnimplemented : public AlphaStaticInst
+ {
+ public:
+ /// Constructor
+ FailUnimplemented(const char *_mnemonic, MachInst _machInst)
+ : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
+ {
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+ }
+
+ %(BasicExecDeclare)s
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Base class for unimplemented instructions that cause a warning
+ * to be printed (but do not terminate simulation). This
+ * implementation is a little screwy in that it will print a
+ * warning for each instance of a particular unimplemented machine
+ * instruction, not just for each unimplemented opcode. Should
+ * probably make the 'warned' flag a static member of the derived
+ * class.
+ */
+ class WarnUnimplemented : public AlphaStaticInst
+ {
+ private:
+ /// Have we warned on this instruction yet?
+ mutable bool warned;
+
+ public:
+ /// Constructor
+ WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
+ : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
+ {
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+ }
+
+ %(BasicExecDeclare)s
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
+output decoder {{
+ std::string
+ FailUnimplemented::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ return csprintf("%-10s (unimplemented)", mnemonic);
+ }
+
+ std::string
+ WarnUnimplemented::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+ return csprintf("%-10s", mnemonic);
+#else
+ return csprintf("%-10s (unimplemented)", mnemonic);
+#endif
+ }
+}};
+
+output exec {{
+ Fault
+ FailUnimplemented::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ panic("attempt to execute unimplemented instruction '%s' "
+ "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
+ return Unimplemented_Opcode_Fault;
+ }
+
+ Fault
+ WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ if (!warned) {
+ warn("instruction '%s' unimplemented\n", mnemonic);
+ warned = true;
+ }
+
+ return No_Fault;
+ }
+}};
+
+
+def format FailUnimpl() {{
+ iop = InstObjParams(name, 'FailUnimplemented')
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+
+def format WarnUnimpl() {{
+ iop = InstObjParams(name, 'WarnUnimplemented')
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+
+output header {{
+ /**
+ * Static instruction class for unknown (illegal) instructions.
+ * These cause simulator termination if they are executed in a
+ * non-speculative mode. This is a leaf class.
+ */
+ class Unknown : public AlphaStaticInst
+ {
+ public:
+ /// Constructor
+ Unknown(MachInst _machInst)
+ : AlphaStaticInst("unknown", _machInst, No_OpClass)
+ {
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+ }
+
+ %(BasicExecDeclare)s
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
diff --git a/arch/mips/isa/formats/unknown.isa b/arch/mips/isa/formats/unknown.isa
new file mode 100644
index 000000000..6eba5b4f9
--- /dev/null
+++ b/arch/mips/isa/formats/unknown.isa
@@ -0,0 +1,52 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+output decoder {{
+ std::string
+ Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
+ "unknown", machInst, OPCODE);
+ }
+}};
+
+output exec {{
+ Fault
+ Unknown::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ panic("attempt to execute unknown instruction "
+ "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
+ return Unimplemented_Opcode_Fault;
+ }
+}};
+
+def format Unknown() {{
+ decode_block = 'return new Unknown(machInst);\n'
+}};
+
diff --git a/arch/mips/isa/main.isa b/arch/mips/isa/main.isa
index a8c71872b..411e398b4 100644
--- a/arch/mips/isa/main.isa
+++ b/arch/mips/isa/main.isa
@@ -26,7 +26,7 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-##include "m5/arch/sparc/isa_desc/includes.h"
+##include "m5/arch/mips/isa/includes.isa"
////////////////////////////////////////////////////////////////////
//
@@ -37,16 +37,16 @@
namespace MipsISA;
//Include the bitfield definitions
-##include "m5/arch/mips/isa_desc/bitfields.h"
+##include "m5/arch/mips/isa/bitfields.isa"
//Include the operand_types and operand definitions
-##include "m5/arch/mips/isa_desc/operands.h"
+##include "m5/arch/mips/isa/operands.isa"
//Include the base class for mips instructions, and some support code
-##include "m5/arch/mips/isa_desc/base.h"
+##include "m5/arch/mips/isa/base.isa"
//Include the definitions for the instruction formats
-##include "m5/arch/mips/isa_desc/formats.h"
+##include "m5/arch/mips/isa/formats.isa"
//Include the decoder definition
-##include "m5/arch/mips/isa_desc/decoder.h"
+##include "m5/arch/mips/isa/decoder.isa"
diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index c8e08a436..cf6f10e0b 100644
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -5,8 +5,8 @@ def operand_types {{
'uhw' : ('unsigned int', 16),
'sw' : ('signed int', 32),
'uw' : ('unsigned int', 32),
- 'sdw' : ('signed int', 64),
- 'udw' : ('unsigned int', 64),
+ 'sd' : ('signed int', 64),
+ 'ud' : ('unsigned int', 64),
'sf' : ('float', 32),
'df' : ('float', 64),
'qf' : ('float', 128)
@@ -24,7 +24,7 @@ def operands {{
'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
- 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
+ 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 19:24:06 +0000