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-rw-r--r--arch/alpha/alpha_memory.cc4
-rw-r--r--arch/alpha/arguments.cc4
-rw-r--r--arch/alpha/arguments.hh2
-rw-r--r--arch/alpha/ev5.hh12
-rw-r--r--arch/alpha/faults.cc2
-rw-r--r--arch/alpha/isa_traits.hh13
-rw-r--r--arch/alpha/osfpal.cc2
-rw-r--r--arch/alpha/vtophys.cc116
-rw-r--r--arch/alpha/vtophys.hh16
9 files changed, 76 insertions, 95 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 4a350dbfc..b9187a92e 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -30,13 +30,13 @@
#include <string>
#include <vector>
+#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/ev5.hh"
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "sim/builder.hh"
-#include "targetarch/alpha_memory.hh"
-#include "targetarch/ev5.hh"
using namespace std;
diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc
index 2dca3f51e..905d6b9ae 100644
--- a/arch/alpha/arguments.cc
+++ b/arch/alpha/arguments.cc
@@ -26,10 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "arch/alpha/arguments.hh"
+#include "arch/alpha/vtophys.hh"
#include "cpu/exec_context.hh"
#include "mem/functional_mem/physical_memory.hh"
-#include "targetarch/arguments.hh"
-#include "targetarch/vtophys.hh"
AlphaArguments::Data::~Data()
{
diff --git a/arch/alpha/arguments.hh b/arch/alpha/arguments.hh
index 78e66b3fd..b4dc0eea8 100644
--- a/arch/alpha/arguments.hh
+++ b/arch/alpha/arguments.hh
@@ -31,9 +31,9 @@
#include <assert.h>
+#include "arch/alpha/vtophys.hh"
#include "base/refcnt.hh"
#include "sim/host.hh"
-#include "targetarch/vtophys.hh"
class ExecContext;
diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index f49eadeb0..7b1ff4a2f 100644
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -7,18 +7,6 @@
#error This code is only valid for EV5 systems
#endif
-#include "targetarch/isa_traits.hh"
-
-////////////////////////////////////////////////////////////////////////
-//
-//
-//
-
-////////////////////////////////////////////////////////////////////////
-//
-//
-//
-
#define MODE2MASK(X) (1 << (X))
// Alpha IPR register accessors
diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc
index a800f9886..c98bb91a5 100644
--- a/arch/alpha/faults.cc
+++ b/arch/alpha/faults.cc
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "targetarch/faults.hh"
+#include "arch/alpha/faults.hh"
namespace {
const char *
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 6559368e4..b22b2fa29 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -29,9 +29,9 @@
#ifndef __ISA_TRAITS_HH__
#define __ISA_TRAITS_HH__
-#include "sim/host.hh"
-#include "targetarch/faults.hh"
+#include "arch/alpha/faults.hh"
#include "base/misc.hh"
+#include "sim/host.hh"
class FastCPU;
class FullCPU;
@@ -121,11 +121,16 @@ class AlphaISA
Addr lock_addr; // lock address for LL/SC
} MiscRegFile;
+static const Addr PageShift = 13;
+static const Addr PageBytes = ULL(1) << PageShift;
+static const Addr PageMask = ~(PageBytes - 1);
+static const Addr PageOffset = PageBytes - 1;
+
#ifdef FULL_SYSTEM
typedef uint64_t InternalProcReg;
-#include "targetarch/isa_fullsys_traits.hh"
+#include "arch/alpha/isa_fullsys_traits.hh"
#else
enum {
@@ -278,7 +283,7 @@ const int NumInterruptLevels = TheISA::NumInterruptLevels;
// more stuff that should be imported here, but I'm too tired to do it
// right now...
-#include "targetarch/ev5.hh"
+#include "arch/alpha/ev5.hh"
#endif
#endif // __ALPHA_ISA_H__
diff --git a/arch/alpha/osfpal.cc b/arch/alpha/osfpal.cc
index 2717079ab..3cdc3864a 100644
--- a/arch/alpha/osfpal.cc
+++ b/arch/alpha/osfpal.cc
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "targetarch/osfpal.hh"
+#include "arch/alpha/osfpal.hh"
namespace {
const char *strings[PAL::NumCodes] = {
diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc
index 5468d4b07..a8af8f238 100644
--- a/arch/alpha/vtophys.cc
+++ b/arch/alpha/vtophys.cc
@@ -28,61 +28,47 @@
#include <string>
-#include "targetarch/pmap.h"
-
+#include "arch/alpha/vtophys.hh"
+#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "mem/functional_mem/physical_memory.hh"
-#include "base/trace.hh"
-#include "targetarch/vtophys.hh"
using namespace std;
-inline Addr
-level3_index(Addr vaddr)
-{ return (vaddr >> ALPHA_PGSHIFT) & PTEMASK; }
-
-inline Addr
-level2_index(Addr vaddr)
-{ return (vaddr >> (ALPHA_PGSHIFT + NPTEPG_SHIFT)) & PTEMASK; }
-
-inline Addr
-level1_index(Addr vaddr)
-{ return (vaddr >> (ALPHA_PGSHIFT + 2 * NPTEPG_SHIFT)) & PTEMASK; }
-
-Addr
-kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, Addr vaddr)
+AlphaISA::PageTableEntry
+kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr)
{
- uint64_t level1_map = ptbr;
- Addr level1_pte = level1_map + (level1_index(vaddr) << PTESHIFT);
-
- uint64_t level1 = pmem->phys_read_qword(level1_pte);
- if (!entry_valid(level1)) {
+ Addr level1_pte = ptbr + vaddr.level1();
+ AlphaISA::PageTableEntry level1 = pmem->phys_read_qword(level1_pte);
+ if (!level1.valid()) {
DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
return 0;
}
- uint64_t level2_map = PMAP_PTE_PA(level1);
- Addr level2_pte = level2_map + (level2_index(vaddr) << PTESHIFT);
- uint64_t level2 = pmem->phys_read_qword(level2_pte);
- if (!entry_valid(level2)) {
+ Addr level2_pte = level1.paddr() + vaddr.level2();
+ AlphaISA::PageTableEntry level2 = pmem->phys_read_qword(level2_pte);
+ if (!level2.valid()) {
DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
return 0;
}
- uint64_t level3_map = PMAP_PTE_PA(level2);
- Addr level3_pte = level3_map + (level3_index(vaddr) << PTESHIFT);
-
- return level3_pte;
+ Addr level3_pte = level2.paddr() + vaddr.level3();
+ AlphaISA::PageTableEntry level3 = pmem->phys_read_qword(level3_pte);
+ if (!level3.valid()) {
+ DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
+ return 0;
+ }
+ return level3;
}
Addr
vtophys(PhysicalMemory *xc, Addr vaddr)
{
Addr paddr = 0;
- if (vaddr < ALPHA_K0SEG_BASE)
+ if (AlphaISA::IsUSeg(vaddr))
DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
- else if (vaddr < ALPHA_K1SEG_BASE)
- paddr = ALPHA_K0SEG_TO_PHYS(vaddr);
+ else if (AlphaISA::IsK0Seg(vaddr))
+ paddr = AlphaISA::K0Seg2Phys(vaddr);
else
panic("vtophys: ptbr is not set on virtual lookup");
@@ -92,8 +78,9 @@ vtophys(PhysicalMemory *xc, Addr vaddr)
}
Addr
-vtophys(ExecContext *xc, Addr vaddr)
+vtophys(ExecContext *xc, Addr addr)
{
+ AlphaISA::VAddr vaddr = addr;
Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
Addr paddr = 0;
//@todo Andrew couldn't remember why he commented some of this code
@@ -101,15 +88,15 @@ vtophys(ExecContext *xc, Addr vaddr)
if (PC_PAL(vaddr) && (vaddr < PAL_MAX)) {
paddr = vaddr & ~ULL(1);
} else {
- if (vaddr >= ALPHA_K0SEG_BASE && vaddr <= ALPHA_K0SEG_END) {
- paddr = ALPHA_K0SEG_TO_PHYS(vaddr);
+ if (AlphaISA::IsK0Seg(vaddr)) {
+ paddr = AlphaISA::K0Seg2Phys(vaddr);
} else if (!ptbr) {
paddr = vaddr;
} else {
- Addr pte = kernel_pte_lookup(xc->physmem, ptbr, vaddr);
- uint64_t entry = xc->physmem->phys_read_qword(pte);
- if (pte && entry_valid(entry))
- paddr = PMAP_PTE_PA(entry) | (vaddr & PGOFSET);
+ AlphaISA::PageTableEntry pte =
+ kernel_pte_lookup(xc->physmem, ptbr, vaddr);
+ if (pte.valid())
+ paddr = pte.paddr() | vaddr.offset();
}
}
@@ -141,7 +128,8 @@ CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
int len;
paddr = vtophys(xc, src);
- len = min((int)(ALPHA_PGBYTES - (paddr & PGOFSET)), (int)cplen);
+ len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
+ (int)cplen);
dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
assert(dmaaddr);
@@ -153,15 +141,15 @@ CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
dst += len;
src += len;
- while (cplen > ALPHA_PGBYTES) {
+ while (cplen > AlphaISA::PageBytes) {
paddr = vtophys(xc, src);
- dmaaddr = (char *)xc->physmem->dma_addr(paddr, ALPHA_PGBYTES);
+ dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
assert(dmaaddr);
- memcpy(dst, dmaaddr, ALPHA_PGBYTES);
- cplen -= ALPHA_PGBYTES;
- dst += ALPHA_PGBYTES;
- src += ALPHA_PGBYTES;
+ memcpy(dst, dmaaddr, AlphaISA::PageBytes);
+ cplen -= AlphaISA::PageBytes;
+ dst += AlphaISA::PageBytes;
+ src += AlphaISA::PageBytes;
}
if (cplen > 0) {
@@ -182,7 +170,8 @@ CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
int len;
paddr = vtophys(xc, dest);
- len = min((int)(ALPHA_PGBYTES - (paddr & PGOFSET)), (int)cplen);
+ len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
+ (int)cplen);
dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
assert(dmaaddr);
@@ -194,15 +183,15 @@ CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
src += len;
dest += len;
- while (cplen > ALPHA_PGBYTES) {
+ while (cplen > AlphaISA::PageBytes) {
paddr = vtophys(xc, dest);
- dmaaddr = (char *)xc->physmem->dma_addr(paddr, ALPHA_PGBYTES);
+ dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
assert(dmaaddr);
- memcpy(dmaaddr, src, ALPHA_PGBYTES);
- cplen -= ALPHA_PGBYTES;
- src += ALPHA_PGBYTES;
- dest += ALPHA_PGBYTES;
+ memcpy(dmaaddr, src, AlphaISA::PageBytes);
+ cplen -= AlphaISA::PageBytes;
+ src += AlphaISA::PageBytes;
+ dest += AlphaISA::PageBytes;
}
if (cplen > 0) {
@@ -222,7 +211,8 @@ CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
int len;
paddr = vtophys(xc, vaddr);
- len = min((int)(ALPHA_PGBYTES - (paddr & PGOFSET)), (int)maxlen);
+ len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
+ (int)maxlen);
dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
assert(dmaaddr);
@@ -239,21 +229,21 @@ CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
dst += len;
vaddr += len;
- while (maxlen > ALPHA_PGBYTES) {
+ while (maxlen > AlphaISA::PageBytes) {
paddr = vtophys(xc, vaddr);
- dmaaddr = (char *)xc->physmem->dma_addr(paddr, ALPHA_PGBYTES);
+ dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
assert(dmaaddr);
- char *term = (char *)memchr(dmaaddr, 0, ALPHA_PGBYTES);
- len = term ? (term - dmaaddr + 1) : ALPHA_PGBYTES;
+ char *term = (char *)memchr(dmaaddr, 0, AlphaISA::PageBytes);
+ len = term ? (term - dmaaddr + 1) : AlphaISA::PageBytes;
memcpy(dst, dmaaddr, len);
if (term)
return;
- maxlen -= ALPHA_PGBYTES;
- dst += ALPHA_PGBYTES;
- vaddr += ALPHA_PGBYTES;
+ maxlen -= AlphaISA::PageBytes;
+ dst += AlphaISA::PageBytes;
+ vaddr += AlphaISA::PageBytes;
}
if (maxlen > 0) {
diff --git a/arch/alpha/vtophys.hh b/arch/alpha/vtophys.hh
index 7c22e3371..8e47a0031 100644
--- a/arch/alpha/vtophys.hh
+++ b/arch/alpha/vtophys.hh
@@ -26,19 +26,17 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __VTOPHYS_H__
-#define __VTOPHYS_H__
+#ifndef __ARCH_ALPHA_VTOPHYS_H__
+#define __ARCH_ALPHA_VTOPHYS_H__
-#include "targetarch/isa_traits.hh"
-#include "targetarch/pmap.h"
-
-inline bool entry_valid(uint64_t entry)
-{ return (entry & ALPHA_PTE_VALID) != 0; }
+#include "arch/alpha/isa_traits.hh"
class ExecContext;
class PhysicalMemory;
-Addr kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, Addr vaddr);
+AlphaISA::PageTableEntry
+kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr);
+
Addr vtophys(PhysicalMemory *xc, Addr vaddr);
Addr vtophys(ExecContext *xc, Addr vaddr);
uint8_t *vtomem(ExecContext *xc, Addr vaddr, size_t len);
@@ -48,5 +46,5 @@ void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len);
void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len);
void CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen);
-#endif // __VTOPHYS_H__
+#endif // __ARCH_ALPHA_VTOPHYS_H__
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-24 02:10:10 +0000