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-rw-r--r--arch/SConscript10
-rw-r--r--arch/alpha/SConscript8
-rw-r--r--arch/alpha/ev5.cc55
-rw-r--r--arch/alpha/faults.cc120
-rw-r--r--arch/alpha/faults.hh256
-rw-r--r--arch/alpha/isa/decoder.isa26
-rw-r--r--arch/alpha/isa/fp.isa2
-rw-r--r--arch/alpha/isa/unimp.isa2
-rw-r--r--arch/alpha/isa/unknown.isa2
-rw-r--r--arch/alpha/linux_process.cc (renamed from arch/alpha/alpha_linux_process.cc)4
-rw-r--r--arch/alpha/linux_process.hh (renamed from arch/alpha/alpha_linux_process.hh)0
-rw-r--r--arch/alpha/tlb.cc (renamed from arch/alpha/alpha_memory.cc)32
-rw-r--r--arch/alpha/tlb.hh (renamed from arch/alpha/alpha_memory.hh)0
-rw-r--r--arch/alpha/tru64_process.cc (renamed from arch/alpha/alpha_tru64_process.cc)4
-rw-r--r--arch/alpha/tru64_process.hh (renamed from arch/alpha/alpha_tru64_process.hh)0
15 files changed, 339 insertions, 182 deletions
diff --git a/arch/SConscript b/arch/SConscript
index 142bd763b..5783b39dd 100644
--- a/arch/SConscript
+++ b/arch/SConscript
@@ -46,6 +46,16 @@ sources = []
# List of headers to generate
isa_switch_hdrs = Split('''
isa_traits.hh
+ linux_process.hh
+ tru64_process.hh
+ tlb.hh
+ aout_machdep.h
+ ecoff_machdep.h
+ arguments.hh
+ stacktrace.hh
+ vtophys.hh
+ faults.hh
+ ev5.hh
''')
# Generate the header. target[0] is the full path of the output
diff --git a/arch/alpha/SConscript b/arch/alpha/SConscript
index 050dfb9cf..3b0e69b7a 100644
--- a/arch/alpha/SConscript
+++ b/arch/alpha/SConscript
@@ -50,7 +50,7 @@ base_sources = Split('''
# Full-system sources
full_system_sources = Split('''
- alpha_memory.cc
+ tlb.cc
arguments.cc
ev5.cc
osfpal.cc
@@ -61,9 +61,9 @@ full_system_sources = Split('''
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
- alpha_common_syscall_emul.cc
- alpha_linux_process.cc
- alpha_tru64_process.cc
+ common_syscall_emul.cc
+ linux_process.cc
+ tru64_process.cc
''')
# Set up complete list of sources based on configuration.
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 14b87b16f..ca26fc257 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/tlb.hh"
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/osfpal.hh"
#include "base/kgdb.h"
@@ -79,25 +79,10 @@ AlphaISA::initCPU(RegFile *regs, int cpuId)
regs->intRegFile[16] = cpuId;
regs->intRegFile[0] = cpuId;
- regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
+ regs->pc = regs->ipr[IPR_PAL_BASE] + (new ResetFault)->vect();
regs->npc = regs->pc + sizeof(MachInst);
}
-////////////////////////////////////////////////////////////////////////
-//
-// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
-//
-const Addr
-AlphaISA::fault_addr(Fault fault)
-{
- //Check for the system wide faults
- if(fault == NoFault) return 0x0000;
- else if(fault == MachineCheckFault) return 0x0401;
- else if(fault == AlignmentFault) return 0x0301;
- //Deal with the alpha specific faults
- return ((AlphaFault*)fault)->vect;
-};
-
const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
/* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
/* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
@@ -162,7 +147,7 @@ AlphaISA::processInterrupts(CPU *cpu)
if (ipl && ipl > ipr[IPR_IPLR]) {
ipr[IPR_ISR] = summary;
ipr[IPR_INTID] = ipl;
- cpu->trap(InterruptFault);
+ cpu->trap(new InterruptFault);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
ipr[IPR_IPLR], ipl, summary);
}
@@ -181,33 +166,34 @@ AlphaISA::zeroRegisters(CPU *cpu)
}
void
-ExecContext::ev5_trap(Fault fault)
+ExecContext::ev5_temp_trap(Fault fault)
{
- DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc);
- cpu->recordEvent(csprintf("Fault %s", fault->name));
+ DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc);
+ cpu->recordEvent(csprintf("Fault %s", fault->name()));
assert(!misspeculating());
kernelStats->fault(fault);
- if (fault == ArithmeticFault)
+ if (fault->isA<ArithmeticFault>())
panic("Arithmetic traps are unimplemented!");
AlphaISA::InternalProcReg *ipr = regs.ipr;
// exception restart address
- if (fault != InterruptFault || !inPalMode())
+ if (!fault->isA<InterruptFault>() || !inPalMode())
ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
- if (fault == PalFault || fault == ArithmeticFault /* ||
+ if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
fault == InterruptFault && !inPalMode() */) {
- // traps... skip faulting instruction
+ // traps... skip faulting instruction.
ipr[AlphaISA::IPR_EXC_ADDR] += 4;
}
if (!inPalMode())
AlphaISA::swap_palshadow(&regs, true);
- regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault);
+ regs.pc = ipr[AlphaISA::IPR_PAL_BASE] +
+ (dynamic_cast<AlphaFault *>(fault.get()))->vect();
regs.npc = regs.pc + sizeof(MachInst);
}
@@ -218,11 +204,11 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
InternalProcReg *ipr = regs->ipr;
bool use_pc = (fault == NoFault);
- if (fault == ArithmeticFault)
+ if (fault->isA<ArithmeticFault>())
panic("arithmetic faults NYI...");
// compute exception restart address
- if (use_pc || fault == PalFault || fault == ArithmeticFault) {
+ if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) {
// traps... skip faulting instruction
ipr[IPR_EXC_ADDR] = regs->pc + 4;
} else {
@@ -232,7 +218,8 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
// jump to expection address (PAL PC bit set here as well...)
if (!use_pc)
- regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault);
+ regs->npc = ipr[IPR_PAL_BASE] +
+ (dynamic_cast<AlphaFault *>(fault.get()))->vect();
else
regs->npc = ipr[IPR_PAL_BASE] + pc;
@@ -245,7 +232,7 @@ ExecContext::hwrei()
uint64_t *ipr = regs.ipr;
if (!inPalMode())
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
@@ -357,12 +344,12 @@ ExecContext::readIpr(int idx, Fault &fault)
case AlphaISA::IPR_DTB_IAP:
case AlphaISA::IPR_ITB_IA:
case AlphaISA::IPR_ITB_IAP:
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
break;
default:
// invalid IPR
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
break;
}
@@ -527,7 +514,7 @@ ExecContext::setIpr(int idx, uint64_t val)
case AlphaISA::IPR_ITB_PTE_TEMP:
case AlphaISA::IPR_DTB_PTE_TEMP:
// read-only registers
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
case AlphaISA::IPR_HWINT_CLR:
case AlphaISA::IPR_SL_XMIT:
@@ -629,7 +616,7 @@ ExecContext::setIpr(int idx, uint64_t val)
default:
// invalid IPR
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
}
// no error...
diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc
index fa4950198..78613761d 100644
--- a/arch/alpha/faults.cc
+++ b/arch/alpha/faults.cc
@@ -27,37 +27,95 @@
*/
#include "arch/alpha/faults.hh"
+#include "cpu/exec_context.hh"
-ResetFaultType * const ResetFault =
- new ResetFaultType("reset", 1, 0x0001);
-ArithmeticFaultType * const ArithmeticFault =
- new ArithmeticFaultType("arith", 3, 0x0501);
-InterruptFaultType * const InterruptFault =
- new InterruptFaultType("interrupt", 4, 0x0101);
-NDtbMissFaultType * const NDtbMissFault =
- new NDtbMissFaultType("dtb_miss_single", 5, 0x0201);
-PDtbMissFaultType * const PDtbMissFault =
- new PDtbMissFaultType("dtb_miss_double", 6, 0x0281);
-DtbPageFaultType * const DtbPageFault =
- new DtbPageFaultType("dfault", 8, 0x0381);
-DtbAcvFaultType * const DtbAcvFault =
- new DtbAcvFaultType("dfault", 9, 0x0381);
-ItbMissFaultType * const ItbMissFault =
- new ItbMissFaultType("itbmiss", 10, 0x0181);
-ItbPageFaultType * const ItbPageFault =
- new ItbPageFaultType("itbmiss", 11, 0x0181);
-ItbAcvFaultType * const ItbAcvFault =
- new ItbAcvFaultType("iaccvio", 12, 0x0081);
-UnimplementedOpcodeFaultType * const UnimplementedOpcodeFault =
- new UnimplementedOpcodeFaultType("opdec", 13, 0x0481);
-FloatEnableFaultType * const FloatEnableFault =
- new FloatEnableFaultType("fen", 14, 0x0581);
-PalFaultType * const PalFault =
- new PalFaultType("pal", 15, 0x2001);
-IntegerOverflowFaultType * const IntegerOverflowFault =
- new IntegerOverflowFaultType("intover", 16, 0x0501);
-
-Fault * ListOfFaults[] = {
+namespace AlphaISA
+{
+
+FaultVect AlphaMachineCheckFault::_vect = 0x0401;
+FaultStat AlphaMachineCheckFault::_stat;
+
+FaultVect AlphaAlignmentFault::_vect = 0x0301;
+FaultStat AlphaAlignmentFault::_stat;
+
+FaultName ResetFault::_name = "reset";
+FaultVect ResetFault::_vect = 0x0001;
+FaultStat ResetFault::_stat;
+
+FaultName ArithmeticFault::_name = "arith";
+FaultVect ArithmeticFault::_vect = 0x0501;
+FaultStat ArithmeticFault::_stat;
+
+FaultName InterruptFault::_name = "interrupt";
+FaultVect InterruptFault::_vect = 0x0101;
+FaultStat InterruptFault::_stat;
+
+FaultName NDtbMissFault::_name = "dtb_miss_single";
+FaultVect NDtbMissFault::_vect = 0x0201;
+FaultStat NDtbMissFault::_stat;
+
+FaultName PDtbMissFault::_name = "dtb_miss_double";
+FaultVect PDtbMissFault::_vect = 0x0281;
+FaultStat PDtbMissFault::_stat;
+
+FaultName DtbPageFault::_name = "dfault";
+FaultVect DtbPageFault::_vect = 0x0381;
+FaultStat DtbPageFault::_stat;
+
+FaultName DtbAcvFault::_name = "dfault";
+FaultVect DtbAcvFault::_vect = 0x0381;
+FaultStat DtbAcvFault::_stat;
+
+FaultName ItbMissFault::_name = "itbmiss";
+FaultVect ItbMissFault::_vect = 0x0181;
+FaultStat ItbMissFault::_stat;
+
+FaultName ItbPageFault::_name = "itbmiss";
+FaultVect ItbPageFault::_vect = 0x0181;
+FaultStat ItbPageFault::_stat;
+
+FaultName ItbAcvFault::_name = "iaccvio";
+FaultVect ItbAcvFault::_vect = 0x0081;
+FaultStat ItbAcvFault::_stat;
+
+FaultName UnimplementedOpcodeFault::_name = "opdec";
+FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
+FaultStat UnimplementedOpcodeFault::_stat;
+
+FaultName FloatEnableFault::_name = "fen";
+FaultVect FloatEnableFault::_vect = 0x0581;
+FaultStat FloatEnableFault::_stat;
+
+FaultName PalFault::_name = "pal";
+FaultVect PalFault::_vect = 0x2001;
+FaultStat PalFault::_stat;
+
+FaultName IntegerOverflowFault::_name = "intover";
+FaultVect IntegerOverflowFault::_vect = 0x0501;
+FaultStat IntegerOverflowFault::_stat;
+
+#if FULL_SYSTEM
+
+void AlphaFault::ev5_trap(ExecContext * xc)
+{
+ xc->ev5_temp_trap(this);
+}
+
+void AlphaMachineCheckFault::ev5_trap(ExecContext * xc)
+{
+ xc->ev5_temp_trap(this);
+}
+
+void AlphaAlignmentFault::ev5_trap(ExecContext * xc)
+{
+ xc->ev5_temp_trap(this);
+}
+
+#endif
+
+} // namespace AlphaISA
+
+/*Fault * ListOfFaults[] = {
(Fault *)&NoFault,
(Fault *)&ResetFault,
(Fault *)&MachineCheckFault,
@@ -77,4 +135,4 @@ Fault * ListOfFaults[] = {
(Fault *)&IntegerOverflowFault,
};
-int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);
+int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);*/
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index 3e25adc4e..156faa8fb 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -30,131 +30,231 @@
#define __ALPHA_FAULTS_HH__
#include "sim/faults.hh"
-#include "arch/isa_traits.hh" //For the Addr type
-class AlphaFault : public FaultBase
+// The design of the "name" and "vect" functions is in sim/faults.hh
+
+namespace AlphaISA
+{
+
+typedef const Addr FaultVect;
+
+class AlphaFault : public virtual FaultBase
{
public:
- AlphaFault(char * newName, int newId, Addr newVect)
- : FaultBase(newName, newId), vect(newVect)
- {;}
+#if FULL_SYSTEM
+ void ev5_trap(ExecContext * xc);
+#endif
+ virtual FaultVect vect() = 0;
+};
- Addr vect;
+class AlphaMachineCheckFault :
+ public MachineCheckFault,
+ public AlphaFault
+{
+ private:
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+#if FULL_SYSTEM
+ void ev5_trap(ExecContext * xc);
+#endif
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
};
-extern class ResetFaultType : public AlphaFault
+class AlphaAlignmentFault :
+ public AlignmentFault,
+ public AlphaFault
{
+ private:
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- ResetFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const ResetFault;
+#if FULL_SYSTEM
+ void ev5_trap(ExecContext * xc);
+#endif
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class ArithmeticFaultType : public AlphaFault
+static inline Fault genMachineCheckFault()
{
+ return new AlphaMachineCheckFault;
+}
+
+static inline Fault genAlignmentFault()
+{
+ return new AlphaAlignmentFault;
+}
+
+class ResetFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- ArithmeticFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const ArithmeticFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class InterruptFaultType : public AlphaFault
+class ArithmeticFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- InterruptFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const InterruptFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class NDtbMissFaultType : public AlphaFault
+class InterruptFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- NDtbMissFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const NDtbMissFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class PDtbMissFaultType : public AlphaFault
+class NDtbMissFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- PDtbMissFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const PDtbMissFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class DtbPageFaultType : public AlphaFault
+class PDtbMissFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- DtbPageFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const DtbPageFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class DtbAcvFaultType : public AlphaFault
+class DtbPageFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- DtbAcvFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const DtbAcvFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class DtbAcvFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class ItbMissFaultType : public AlphaFault
+class ItbMissFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- ItbMissFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const ItbMissFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class ItbPageFaultType : public AlphaFault
+class ItbPageFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- ItbPageFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const ItbPageFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class ItbAcvFaultType : public AlphaFault
+class ItbAcvFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- ItbAcvFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const ItbAcvFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class UnimplementedOpcodeFaultType : public AlphaFault
+class UnimplementedOpcodeFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const UnimplementedOpcodeFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class FloatEnableFaultType : public AlphaFault
+class FloatEnableFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- FloatEnableFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const FloatEnableFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class PalFaultType : public AlphaFault
+class PalFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- PalFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const PalFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class IntegerOverflowFaultType : public AlphaFault
+class IntegerOverflowFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- IntegerOverflowFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const IntegerOverflowFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern Fault * ListOfFaults[];
-extern int NumFaults;
+} // AlphaISA namespace
#endif // __FAULTS_HH__
diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index 37b15416b..cdcf96215 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -98,7 +98,7 @@ decode OPCODE default Unknown::unknown() {
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc.sl = tmp;
}});
0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
@@ -110,7 +110,7 @@ decode OPCODE default Unknown::unknown() {
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc = tmp;
}});
0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
@@ -124,7 +124,7 @@ decode OPCODE default Unknown::unknown() {
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc.sl = tmp;
}});
0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
@@ -138,7 +138,7 @@ decode OPCODE default Unknown::unknown() {
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc = tmp;
}});
0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
@@ -299,7 +299,7 @@ decode OPCODE default Unknown::unknown() {
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = tmp<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc.sl = tmp<31:0>;
}}, IntMultOp);
0x60: mulqv({{
@@ -310,7 +310,7 @@ decode OPCODE default Unknown::unknown() {
// the lower 64
if (!((hi == 0 && lo<63:> == 0) ||
(hi == mask(64) && lo<63:> == 1)))
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc = lo;
}}, IntMultOp);
}
@@ -427,19 +427,19 @@ decode OPCODE default Unknown::unknown() {
#if SS_COMPATIBLE_FP
0x0b: sqrts({{
if (Fb < 0.0)
- fault = ArithmeticFault;
+ fault = new ArithmeticFault;
Fc = sqrt(Fb);
}}, FloatSqrtOp);
#else
0x0b: sqrts({{
if (Fb.sf < 0.0)
- fault = ArithmeticFault;
+ fault = new ArithmeticFault;
Fc.sf = sqrt(Fb.sf);
}}, FloatSqrtOp);
#endif
0x2b: sqrtt({{
if (Fb < 0.0)
- fault = ArithmeticFault;
+ fault = new ArithmeticFault;
Fc = sqrt(Fb);
}}, FloatSqrtOp);
}
@@ -570,7 +570,7 @@ decode OPCODE default Unknown::unknown() {
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = Fb.uq<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
}});
@@ -673,7 +673,7 @@ decode OPCODE default Unknown::unknown() {
&& xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
// invalid pal function code, or attempt to do privileged
// PAL call in non-kernel mode
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
}
else {
// check to see if simulator wants to do something special
@@ -729,7 +729,7 @@ decode OPCODE default Unknown::unknown() {
0x19: hw_mfpr({{
// this instruction is only valid in PAL mode
if (!xc->inPalMode()) {
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
}
else {
Ra = xc->readIpr(ipr_index, fault);
@@ -738,7 +738,7 @@ decode OPCODE default Unknown::unknown() {
0x1d: hw_mtpr({{
// this instruction is only valid in PAL mode
if (!xc->inPalMode()) {
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
}
else {
xc->setIpr(ipr_index, Ra);
diff --git a/arch/alpha/isa/fp.isa b/arch/alpha/isa/fp.isa
index 7e81fb830..2ee714b0f 100644
--- a/arch/alpha/isa/fp.isa
+++ b/arch/alpha/isa/fp.isa
@@ -36,7 +36,7 @@ output exec {{
{
Fault fault = NoFault; // dummy... this ipr access should not fault
if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
- fault = FloatEnableFault;
+ fault = new FloatEnableFault;
}
return fault;
}
diff --git a/arch/alpha/isa/unimp.isa b/arch/alpha/isa/unimp.isa
index de4ac3eaf..09df39706 100644
--- a/arch/alpha/isa/unimp.isa
+++ b/arch/alpha/isa/unimp.isa
@@ -111,7 +111,7 @@ output exec {{
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
}
Fault
diff --git a/arch/alpha/isa/unknown.isa b/arch/alpha/isa/unknown.isa
index 4601b3684..47d166255 100644
--- a/arch/alpha/isa/unknown.isa
+++ b/arch/alpha/isa/unknown.isa
@@ -42,7 +42,7 @@ output exec {{
{
panic("attempt to execute unknown instruction "
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
}
}};
diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/linux_process.cc
index 16ebcca7b..0b193fb55 100644
--- a/arch/alpha/alpha_linux_process.cc
+++ b/arch/alpha/linux_process.cc
@@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "arch/alpha/alpha_common_syscall_emul.hh"
-#include "arch/alpha/alpha_linux_process.hh"
+#include "arch/alpha/common_syscall_emul.hh"
+#include "arch/alpha/linux_process.hh"
#include "arch/alpha/isa_traits.hh"
#include "base/trace.hh"
diff --git a/arch/alpha/alpha_linux_process.hh b/arch/alpha/linux_process.hh
index 7de1b1ac1..7de1b1ac1 100644
--- a/arch/alpha/alpha_linux_process.hh
+++ b/arch/alpha/linux_process.hh
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/tlb.cc
index d00186d95..8297737bd 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/tlb.cc
@@ -30,7 +30,7 @@
#include <string>
#include <vector>
-#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/tlb.hh"
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
@@ -322,7 +322,7 @@ AlphaITB::translate(MemReqPtr &req) const
if (!validVirtualAddress(req->vaddr)) {
fault(req->vaddr, req->xc);
acv++;
- return ItbAcvFault;
+ return new ItbAcvFault;
}
@@ -339,7 +339,7 @@ AlphaITB::translate(MemReqPtr &req) const
AlphaISA::mode_kernel) {
fault(req->vaddr, req->xc);
acv++;
- return ItbAcvFault;
+ return new ItbAcvFault;
}
req->paddr = req->vaddr & PAddrImplMask;
@@ -360,7 +360,7 @@ AlphaITB::translate(MemReqPtr &req) const
if (!pte) {
fault(req->vaddr, req->xc);
misses++;
- return ItbPageFault;
+ return new ItbPageFault;
}
req->paddr = (pte->ppn << AlphaISA::PageShift) +
@@ -371,7 +371,7 @@ AlphaITB::translate(MemReqPtr &req) const
// instruction access fault
fault(req->vaddr, req->xc);
acv++;
- return ItbAcvFault;
+ return new ItbAcvFault;
}
hits++;
@@ -380,7 +380,7 @@ AlphaITB::translate(MemReqPtr &req) const
// check that the physical address is ok (catch bad physical addresses)
if (req->paddr & ~PAddrImplMask)
- return MachineCheckFault;
+ return genMachineCheckFault();
checkCacheability(req);
@@ -511,7 +511,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
fault(req, write ? MM_STAT_WR_MASK : 0);
DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
req->size);
- return AlignmentFault;
+ return genAlignmentFault();
}
if (pc & 0x1) {
@@ -530,7 +530,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
MM_STAT_ACV_MASK);
if (write) { write_acv++; } else { read_acv++; }
- return DtbPageFault;
+ return new DtbPageFault;
}
// Check for "superpage" mapping
@@ -547,7 +547,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
fault(req, ((write ? MM_STAT_WR_MASK : 0) |
MM_STAT_ACV_MASK));
if (write) { write_acv++; } else { read_acv++; }
- return DtbAcvFault;
+ return new DtbAcvFault;
}
req->paddr = req->vaddr & PAddrImplMask;
@@ -575,7 +575,9 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
fault(req, (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_DTB_MISS_MASK);
if (write) { write_misses++; } else { read_misses++; }
- return (req->flags & VPTE) ? (Fault)PDtbMissFault : (Fault)NDtbMissFault;
+ return (req->flags & VPTE) ?
+ (Fault)(new PDtbMissFault) :
+ (Fault)(new NDtbMissFault);
}
req->paddr = (pte->ppn << AlphaISA::PageShift) +
@@ -588,25 +590,25 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
MM_STAT_ACV_MASK |
(pte->fonw ? MM_STAT_FONW_MASK : 0));
write_acv++;
- return DtbPageFault;
+ return new DtbPageFault;
}
if (pte->fonw) {
fault(req, MM_STAT_WR_MASK |
MM_STAT_FONW_MASK);
write_acv++;
- return DtbPageFault;
+ return new DtbPageFault;
}
} else {
if (!(pte->xre & MODE2MASK(mode))) {
fault(req, MM_STAT_ACV_MASK |
(pte->fonr ? MM_STAT_FONR_MASK : 0));
read_acv++;
- return DtbAcvFault;
+ return new DtbAcvFault;
}
if (pte->fonr) {
fault(req, MM_STAT_FONR_MASK);
read_acv++;
- return DtbPageFault;
+ return new DtbPageFault;
}
}
}
@@ -619,7 +621,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
// check that the physical address is ok (catch bad physical addresses)
if (req->paddr & ~PAddrImplMask)
- return MachineCheckFault;
+ return genMachineCheckFault();
checkCacheability(req);
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/tlb.hh
index de955fa46..de955fa46 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/tlb.hh
diff --git a/arch/alpha/alpha_tru64_process.cc b/arch/alpha/tru64_process.cc
index 8121d3452..90e8b1139 100644
--- a/arch/alpha/alpha_tru64_process.cc
+++ b/arch/alpha/tru64_process.cc
@@ -27,8 +27,8 @@
*/
#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/alpha_common_syscall_emul.hh"
-#include "arch/alpha/alpha_tru64_process.hh"
+#include "arch/alpha/common_syscall_emul.hh"
+#include "arch/alpha/tru64_process.hh"
#include "cpu/exec_context.hh"
#include "kern/tru64/tru64.hh"
#include "mem/functional/functional.hh"
diff --git a/arch/alpha/alpha_tru64_process.hh b/arch/alpha/tru64_process.hh
index 051760702..051760702 100644
--- a/arch/alpha/alpha_tru64_process.hh
+++ b/arch/alpha/tru64_process.hh
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 14:47:17 +0000