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-rw-r--r--arch/mips/isa/decoder.isa14
-rw-r--r--arch/mips/isa/formats/int.isa3
2 files changed, 7 insertions, 10 deletions
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index ffedfbca8..eaa7b7248 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -137,17 +137,15 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: decode FUNCTION_LO {
format IntOp {
0x0: mult({{
- int64_t temp1 = Rs.sw * Rt.sw;
+ int64_t temp1 = Rs.sd * Rt.sd;
xc->setMiscReg(Hi,temp1<63:32>);
xc->setMiscReg(Lo,temp1<31:0>);
}});
0x1: multu({{
- uint64_t temp1 = Rs.uw * Rt.uw;
- uint32_t hi_val = temp1<63:32>;
- uint32_t lo_val = temp1<31:0>;
- xc->setMiscReg(Hi,hi_val);
- xc->setMiscReg(Lo,lo_val);
+ uint64_t temp1 = Rs.ud * Rt.ud;
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
0x2: div({{
@@ -156,8 +154,8 @@ decode OPCODE_HI default Unknown::unknown() {
}});
0x3: divu({{
- xc->setMiscReg(Hi,Rs.uw % Rt.uw);
- xc->setMiscReg(Lo,Rs.uw / Rt.uw);
+ xc->setMiscReg(Hi,Rs.uw % Rt.uw);
+ xc->setMiscReg(Lo,Rs.uw / Rt.uw);
}});
}
}
diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa
index 98e58f7f2..7d38b9ff5 100644
--- a/arch/mips/isa/formats/int.isa
+++ b/arch/mips/isa/formats/int.isa
@@ -64,10 +64,9 @@ output decoder {{
// it's generally implicit
if (_numDestRegs > 0) {
printReg(ss, _destRegIdx[0]);
+ ss << ",";
}
- ss << ",";
-
// just print the first two source regs... if there's
// a third one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx