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-rw-r--r--arch/alpha/alpha_linux_process.cc2
-rw-r--r--arch/alpha/alpha_memory.cc69
-rw-r--r--arch/alpha/alpha_memory.hh2
-rw-r--r--arch/alpha/alpha_tru64_process.cc2
-rw-r--r--arch/alpha/ev5.hh47
-rw-r--r--arch/alpha/faults.hh2
-rw-r--r--arch/alpha/isa_desc26
-rw-r--r--arch/alpha/isa_traits.hh2
-rw-r--r--arch/alpha/osfpal.cc2
-rw-r--r--arch/alpha/osfpal.hh2
-rw-r--r--arch/alpha/pseudo_inst.cc2
-rw-r--r--arch/alpha/pseudo_inst.hh2
-rw-r--r--arch/alpha/vptr.hh2
-rw-r--r--arch/alpha/vtophys.cc5
-rw-r--r--arch/alpha/vtophys.hh2
15 files changed, 134 insertions, 35 deletions
diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/alpha_linux_process.cc
index b9eb42a21..67bb0ab3b 100644
--- a/arch/alpha/alpha_linux_process.cc
+++ b/arch/alpha/alpha_linux_process.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 58aa13b8f..a40ad7a5c 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2001-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -44,6 +44,11 @@ using namespace std;
//
// Alpha TLB
//
+#ifdef DEBUG
+bool uncacheBit39 = false;
+bool uncacheBit40 = false;
+#endif
+
AlphaTLB::AlphaTLB(const string &name, int s)
: SimObject(name), size(s), nlu(0)
{
@@ -87,9 +92,23 @@ AlphaTLB::checkCacheability(MemReqPtr &req)
{
// in Alpha, cacheability is controlled by upper-level bits of the
// physical address
- if (req->paddr & PA_UNCACHED_BIT) {
+
+ /*
+ * We support having the uncacheable bit in either bit 39 or bit 40.
+ * The Turbolaser platform (and EV5) support having the bit in 39, but
+ * Tsunami (which Linux assumes uses an EV6) generates accesses with
+ * the bit in 40. So we must check for both, but we have debug flags
+ * to catch a weird case where both are used, which shouldn't happen.
+ */
+
+
+#ifdef ALPHA_TLASER
+ if (req->paddr & PA_UNCACHED_BIT_39) {
+#else
+ if (req->paddr & PA_UNCACHED_BIT_43) {
+#endif
+ // IPR memory space not implemented
if (PA_IPR_SPACE(req->paddr)) {
- // IPR memory space not implemented
if (!req->xc->misspeculating()) {
switch (req->paddr) {
case ULL(0xFFFFF00188):
@@ -104,6 +123,11 @@ AlphaTLB::checkCacheability(MemReqPtr &req)
} else {
// mark request as uncacheable
req->flags |= UNCACHEABLE;
+
+#ifndef ALPHA_TLASER
+ // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
+ req->paddr &= PA_UNCACHED_MASK;
+#endif
}
}
}
@@ -290,10 +314,16 @@ AlphaITB::translate(MemReqPtr &req) const
return ITB_Acv_Fault;
}
- // Check for "superpage" mapping: when SP<1> is set, and
- // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
+
+ // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
+ // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
+#ifdef ALPHA_TLASER
if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
- VA_SPACE(req->vaddr) == 2) {
+ VA_SPACE_EV5(req->vaddr) == 2) {
+#else
+ if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
+#endif
+
// only valid in kernel mode
if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) {
@@ -303,6 +333,15 @@ AlphaITB::translate(MemReqPtr &req) const
}
req->paddr = req->vaddr & PA_IMPL_MASK;
+
+#ifndef ALPHA_TLASER
+ // sign extend the physical address properly
+ if (req->paddr & PA_UNCACHED_BIT_40)
+ req->paddr |= ULL(0xf0000000000);
+ else
+ req->paddr &= ULL(0xffffffffff);
+#endif
+
} else {
// not a physical address: need to look up pte
AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr),
@@ -470,10 +509,13 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
return DTB_Fault_Fault;
}
- // Check for "superpage" mapping: when SP<1> is set, and
- // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
+ // Check for "superpage" mapping
+#ifdef ALPHA_TLASER
if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
- VA_SPACE(req->vaddr) == 2) {
+ VA_SPACE_EV5(req->vaddr) == 2) {
+#else
+ if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
+#endif
// only valid in kernel mode
if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
@@ -484,6 +526,15 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
}
req->paddr = req->vaddr & PA_IMPL_MASK;
+
+#ifndef ALPHA_TLASER
+ // sign extend the physical address properly
+ if (req->paddr & PA_UNCACHED_BIT_40)
+ req->paddr |= ULL(0xf0000000000);
+ else
+ req->paddr &= ULL(0xffffffffff);
+#endif
+
} else {
if (write)
write_accesses++;
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index fbd6ecf15..42bc03ddd 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2001-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/alpha/alpha_tru64_process.cc b/arch/alpha/alpha_tru64_process.cc
index 2366baed8..149569f14 100644
--- a/arch/alpha/alpha_tru64_process.cc
+++ b/arch/alpha/alpha_tru64_process.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2001-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index 6947ef708..5b27dd3dc 100644
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -32,8 +32,15 @@
#define ALT_MODE_AM(X) (((X) >> 3) & 0x3)
#define DTB_CM_CM(X) (((X) >> 3) & 0x3)
-#define DTB_ASN_ASN(X) (((X) >> 57) & 0x7f)
-#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
+
+#ifdef ALPHA_TLASER
+#define DTB_ASN_ASN(X) (((X) >> 57) & 0x7f)
+#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
+#else
+#define DTB_ASN_ASN(X) (((X) >> 57) & 0xff)
+#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
+#endif
+
#define DTB_PTE_XRE(X) (((X) >> 8) & 0xf)
#define DTB_PTE_XWE(X) (((X) >> 12) & 0xf)
#define DTB_PTE_FONR(X) (((X) >> 1) & 0x1)
@@ -41,9 +48,16 @@
#define DTB_PTE_GH(X) (((X) >> 5) & 0x3)
#define DTB_PTE_ASMA(X) (((X) >> 4) & 0x1)
-#define ICM_CM(X) (((X) >> 3) & 0x3)
-#define ITB_ASN_ASN(X) (((X) >> 4) & 0x7f)
-#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
+#define ICM_CM(X) (((X) >> 3) & 0x3)
+
+#ifdef ALPHA_TLASER
+#define ITB_ASN_ASN(X) (((X) >> 4) & 0x7f)
+#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
+#else
+#define ITB_ASN_ASN(X) (((X) >> 4) & 0xff)
+#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
+#endif
+
#define ITB_PTE_XRE(X) (((X) >> 8) & 0xf)
#define ITB_PTE_FONR(X) (((X) >> 1) & 0x1)
#define ITB_PTE_FONW(X) (((X) >> 2) & 0x1)
@@ -52,14 +66,23 @@
#define VA_UNIMPL_MASK ULL(0xfffff80000000000)
#define VA_IMPL_MASK ULL(0x000007ffffffffff)
-#define VA_IMPL(X) ((X) & VA_IMPL_MASK)
-#define VA_VPN(X) (VA_IMPL(X) >> 13)
-#define VA_SPACE(X) (((X) >> 41) & 0x3)
-#define VA_POFS(X) ((X) & 0x1fff)
-
+#define VA_IMPL(X) ((X) & VA_IMPL_MASK)
+#define VA_VPN(X) (VA_IMPL(X) >> 13)
+#define VA_SPACE_EV5(X) (((X) >> 41) & 0x3)
+#define VA_SPACE_EV6(X) (((X) >> 41) & 0x7f)
+#define VA_POFS(X) ((X) & 0x1fff)
+
+#define PA_UNCACHED_BIT_39 ULL(0x8000000000)
+#define PA_UNCACHED_BIT_40 ULL(0x10000000000)
+#define PA_UNCACHED_BIT_43 ULL(0x80000000000)
+#define PA_UNCACHED_MASK ULL(0x807ffffffff) // Clear PA<42:35>
+#ifdef ALPHA_TLASER
+#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFF00000))
#define PA_IMPL_MASK ULL(0xffffffffff)
-#define PA_UNCACHED_BIT ULL(0x8000000000)
-#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFF00000))
+#else
+#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFFF00000))
+#define PA_IMPL_MASK ULL(0xfffffffffff) // for Tsunami
+#endif
#define PA_PFN2PA(X) ((X) << 13)
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index 33aa55439..45ac122dc 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 6c5912c52..94f5d9bc3 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -2119,12 +2119,34 @@ decode OPCODE default Unknown::unknown() {
0x1c: decode INTFUNC {
0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
+ 0x32: ctlz({{
+ uint64_t count = 0;
+ uint64_t temp = Rb;
+ if (temp<63:32>) temp >>= 32; else count += 32;
+ if (temp<31:16>) temp >>= 16; else count += 16;
+ if (temp<15:8>) temp >>= 8; else count += 8;
+ if (temp<7:4>) temp >>= 4; else count += 4;
+ if (temp<3:2>) temp >>= 2; else count += 2;
+ if (temp<1:1>) temp >>= 1; else count += 1;
+ if ((temp<0:0>) != 0x1) count += 1;
+ Rc = count;
+ }}, IntAluOp);
+
+ 0x33: cttz({{
+ uint64_t count = 0;
+ uint64_t temp = Rb;
+ if (!(temp<31:0>)) { temp >>= 32; count += 32; }
+ if (!(temp<15:0>)) { temp >>= 16; count += 16; }
+ if (!(temp<7:0>)) { temp >>= 8; count += 8; }
+ if (!(temp<3:0>)) { temp >>= 4; count += 4; }
+ if (!(temp<1:0>)) { temp >>= 2; count += 2; }
+ if (!(temp<0:0> & ULL(0x1))) count += 1;
+ Rc = count;
+ }}, IntAluOp);
format FailUnimpl {
0x30: ctpop();
0x31: perr();
- 0x32: ctlz();
- 0x33: cttz();
0x34: unpkbw();
0x35: unpkbl();
0x36: pkwb();
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 1a8ff663b..6559368e4 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/alpha/osfpal.cc b/arch/alpha/osfpal.cc
index 90d645ef1..2717079ab 100644
--- a/arch/alpha/osfpal.cc
+++ b/arch/alpha/osfpal.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/alpha/osfpal.hh b/arch/alpha/osfpal.hh
index 419235b4a..2a835633f 100644
--- a/arch/alpha/osfpal.hh
+++ b/arch/alpha/osfpal.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc
index 12dacebd9..f4201ab09 100644
--- a/arch/alpha/pseudo_inst.cc
+++ b/arch/alpha/pseudo_inst.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/alpha/pseudo_inst.hh b/arch/alpha/pseudo_inst.hh
index e5551a44b..e59487397 100644
--- a/arch/alpha/pseudo_inst.hh
+++ b/arch/alpha/pseudo_inst.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/alpha/vptr.hh b/arch/alpha/vptr.hh
index 7f0b036a3..cd4bc547b 100644
--- a/arch/alpha/vptr.hh
+++ b/arch/alpha/vptr.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc
index 5e14b06d3..7a38b296b 100644
--- a/arch/alpha/vtophys.cc
+++ b/arch/alpha/vtophys.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2002-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -96,6 +96,8 @@ vtophys(ExecContext *xc, Addr vaddr)
{
Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
Addr paddr = 0;
+ //@todo Andrew couldn't remember why he commented some of this code
+ //so I put it back in. Perhaps something to do with gdb debugging?
if (PC_PAL(vaddr)) {
paddr = vaddr & ~ULL(1);
} else if (!ptbr) {
@@ -111,6 +113,7 @@ vtophys(ExecContext *xc, Addr vaddr)
}
}
+
DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
return paddr;
diff --git a/arch/alpha/vtophys.hh b/arch/alpha/vtophys.hh
index f5696e9c8..497a53f0d 100644
--- a/arch/alpha/vtophys.hh
+++ b/arch/alpha/vtophys.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2002-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-05 14:51:26 +0000