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-rw-r--r--arch/alpha/SConscript1
-rw-r--r--arch/alpha/isa/decoder.isa14
-rw-r--r--arch/alpha/isa/main.isa6
-rw-r--r--arch/alpha/pseudo_inst.cc256
-rw-r--r--arch/alpha/pseudo_inst.hh54
-rw-r--r--arch/alpha/vptr.hh114
-rw-r--r--arch/mips/isa/bitfields.isa1
-rw-r--r--arch/mips/isa/decoder.isa403
8 files changed, 285 insertions, 564 deletions
diff --git a/arch/alpha/SConscript b/arch/alpha/SConscript
index 2c98125bc..8bf408c06 100644
--- a/arch/alpha/SConscript
+++ b/arch/alpha/SConscript
@@ -244,7 +244,6 @@ arch_full_system_sources = Split('''
arch/alpha/arguments.cc
arch/alpha/ev5.cc
arch/alpha/osfpal.cc
- arch/alpha/pseudo_inst.cc
arch/alpha/stacktrace.cc
arch/alpha/vtophys.cc
''')
diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index 29124f191..aff8571e9 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -768,23 +768,23 @@ decode OPCODE default Unknown::unknown() {
AlphaPseudo::m5exit_old(xc->xcBase());
}}, No_OpClass, IsNonSpeculative);
0x21: m5exit({{
- AlphaPseudo::m5exit(xc->xcBase());
+ AlphaPseudo::m5exit(xc->xcBase(), R16);
}}, No_OpClass, IsNonSpeculative);
0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
0x40: resetstats({{
- AlphaPseudo::resetstats(xc->xcBase());
+ AlphaPseudo::resetstats(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x41: dumpstats({{
- AlphaPseudo::dumpstats(xc->xcBase());
+ AlphaPseudo::dumpstats(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x42: dumpresetstats({{
- AlphaPseudo::dumpresetstats(xc->xcBase());
+ AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x43: m5checkpoint({{
- AlphaPseudo::m5checkpoint(xc->xcBase());
+ AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x50: m5readfile({{
- AlphaPseudo::readfile(xc->xcBase());
+ R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18);
}}, IsNonSpeculative);
0x51: m5break({{
AlphaPseudo::debugbreak(xc->xcBase());
@@ -793,7 +793,7 @@ decode OPCODE default Unknown::unknown() {
AlphaPseudo::switchcpu(xc->xcBase());
}}, IsNonSpeculative);
0x53: m5addsymbol({{
- AlphaPseudo::addsymbol(xc->xcBase());
+ AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
}
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index c082df8c8..ef4d83ce2 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -50,7 +50,7 @@ output exec {{
#include <math.h>
#if FULL_SYSTEM
-#include "arch/alpha/pseudo_inst.hh"
+#include "sim/pseudo_inst.hh"
#endif
#include "base/fenv.hh"
#include "config/ss_compatible_fp.hh"
@@ -160,7 +160,9 @@ def operands {{
'FPCR': (' ControlReg', 'uq', 'Fpcr', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
- 'R16': ('IntReg', 'uq', '16', None, 1)
+ 'R16': ('IntReg', 'uq', '16', None, 1),
+ 'R17': ('IntReg', 'uq', '17', None, 1),
+ 'R18': ('IntReg', 'uq', '18', None, 1)
}};
////////////////////////////////////////////////////////////////////
diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc
deleted file mode 100644
index e105b3cc8..000000000
--- a/arch/alpha/pseudo_inst.cc
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <cstdio>
-
-#include <string>
-
-#include "arch/alpha/pseudo_inst.hh"
-#include "arch/alpha/vtophys.hh"
-#include "cpu/base.hh"
-#include "cpu/sampler/sampler.hh"
-#include "cpu/exec_context.hh"
-#include "kern/kernel_stats.hh"
-#include "sim/param.hh"
-#include "sim/serialize.hh"
-#include "sim/sim_exit.hh"
-#include "sim/stat_control.hh"
-#include "sim/stats.hh"
-#include "sim/system.hh"
-#include "sim/debug.hh"
-#include "targetarch/vptr.hh"
-
-using namespace std;
-
-extern Sampler *SampCPU;
-
-using namespace Stats;
-
-namespace AlphaPseudo
-{
- bool doStatisticsInsts;
- bool doCheckpointInsts;
- bool doQuiesce;
-
- void
- arm(ExecContext *xc)
- {
- xc->kernelStats->arm();
- }
-
- void
- quiesce(ExecContext *xc)
- {
- if (!doQuiesce)
- return;
-
- xc->suspend();
- xc->kernelStats->quiesce();
- }
-
- void
- ivlb(ExecContext *xc)
- {
- xc->kernelStats->ivlb();
- }
-
- void
- ivle(ExecContext *xc)
- {
- }
-
- void
- m5exit_old(ExecContext *xc)
- {
- SimExit(curTick, "m5_exit_old instruction encountered");
- }
-
- void
- m5exit(ExecContext *xc)
- {
- Tick delay = xc->regs.intRegFile[16];
- Tick when = curTick + delay * Clock::Int::ns;
- SimExit(when, "m5_exit instruction encountered");
- }
-
- void
- resetstats(ExecContext *xc)
- {
- if (!doStatisticsInsts)
- return;
-
- Tick delay = xc->regs.intRegFile[16];
- Tick period = xc->regs.intRegFile[17];
-
- Tick when = curTick + delay * Clock::Int::ns;
- Tick repeat = period * Clock::Int::ns;
-
- using namespace Stats;
- SetupEvent(Reset, when, repeat);
- }
-
- void
- dumpstats(ExecContext *xc)
- {
- if (!doStatisticsInsts)
- return;
-
- Tick delay = xc->regs.intRegFile[16];
- Tick period = xc->regs.intRegFile[17];
-
- Tick when = curTick + delay * Clock::Int::ns;
- Tick repeat = period * Clock::Int::ns;
-
- using namespace Stats;
- SetupEvent(Dump, when, repeat);
- }
-
- void
- addsymbol(ExecContext *xc)
- {
- Addr addr = xc->regs.intRegFile[16];
- char symb[100];
- CopyString(xc, symb, xc->regs.intRegFile[17], 100);
- std::string symbol(symb);
-
- DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
-
- xc->system->kernelSymtab->insert(addr,symbol);
- }
-
- void
- dumpresetstats(ExecContext *xc)
- {
- if (!doStatisticsInsts)
- return;
-
- Tick delay = xc->regs.intRegFile[16];
- Tick period = xc->regs.intRegFile[17];
-
- Tick when = curTick + delay * Clock::Int::ns;
- Tick repeat = period * Clock::Int::ns;
-
- using namespace Stats;
- SetupEvent(Dump|Reset, when, repeat);
- }
-
- void
- m5checkpoint(ExecContext *xc)
- {
- if (!doCheckpointInsts)
- return;
-
- Tick delay = xc->regs.intRegFile[16];
- Tick period = xc->regs.intRegFile[17];
-
- Tick when = curTick + delay * Clock::Int::ns;
- Tick repeat = period * Clock::Int::ns;
-
- Checkpoint::setup(when, repeat);
- }
-
- void
- readfile(ExecContext *xc)
- {
- const string &file = xc->cpu->system->params->readfile;
- if (file.empty()) {
- xc->regs.intRegFile[0] = ULL(0);
- return;
- }
-
- Addr vaddr = xc->regs.intRegFile[16];
- uint64_t len = xc->regs.intRegFile[17];
- uint64_t offset = xc->regs.intRegFile[18];
- uint64_t result = 0;
-
- int fd = ::open(file.c_str(), O_RDONLY, 0);
- if (fd < 0)
- panic("could not open file %s\n", file);
-
- if (::lseek(fd, offset, SEEK_SET) < 0)
- panic("could not seek: %s", strerror(errno));
-
- char *buf = new char[len];
- char *p = buf;
- while (len > 0) {
- int bytes = ::read(fd, p, len);
- if (bytes <= 0)
- break;
-
- p += bytes;
- result += bytes;
- len -= bytes;
- }
-
- close(fd);
- CopyIn(xc, vaddr, buf, result);
- delete [] buf;
- xc->regs.intRegFile[0] = result;
- }
-
- class Context : public ParamContext
- {
- public:
- Context(const string &section) : ParamContext(section) {}
- void checkParams();
- };
-
- Context context("pseudo_inst");
-
- Param<bool> __quiesce(&context, "quiesce",
- "enable quiesce instructions",
- true);
- Param<bool> __statistics(&context, "statistics",
- "enable statistics pseudo instructions",
- true);
- Param<bool> __checkpoint(&context, "checkpoint",
- "enable checkpoint pseudo instructions",
- true);
-
- void
- Context::checkParams()
- {
- doQuiesce = __quiesce;
- doStatisticsInsts = __statistics;
- doCheckpointInsts = __checkpoint;
- }
-
- void debugbreak(ExecContext *xc)
- {
- debug_break();
- }
-
- void switchcpu(ExecContext *xc)
- {
- if (SampCPU)
- SampCPU->switchCPUs();
- }
-}
diff --git a/arch/alpha/pseudo_inst.hh b/arch/alpha/pseudo_inst.hh
deleted file mode 100644
index 0e7462a56..000000000
--- a/arch/alpha/pseudo_inst.hh
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-class ExecContext;
-
-namespace AlphaPseudo
-{
- /**
- * @todo these externs are only here for a hack in fullCPU::takeOver...
- */
- extern bool doStatisticsInsts;
- extern bool doCheckpointInsts;
- extern bool doQuiesce;
-
- void arm(ExecContext *xc);
- void quiesce(ExecContext *xc);
- void ivlb(ExecContext *xc);
- void ivle(ExecContext *xc);
- void m5exit(ExecContext *xc);
- void m5exit_old(ExecContext *xc);
- void resetstats(ExecContext *xc);
- void dumpstats(ExecContext *xc);
- void dumpresetstats(ExecContext *xc);
- void m5checkpoint(ExecContext *xc);
- void readfile(ExecContext *xc);
- void debugbreak(ExecContext *xc);
- void switchcpu(ExecContext *xc);
- void addsymbol(ExecContext *xc);
-}
diff --git a/arch/alpha/vptr.hh b/arch/alpha/vptr.hh
deleted file mode 100644
index d1bda4061..000000000
--- a/arch/alpha/vptr.hh
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_ALPHA_VPTR_HH__
-#define __ARCH_ALPHA_VPTR_HH__
-
-#include "arch/alpha/vtophys.hh"
-
-class ExecContext;
-
-template <class T>
-class VPtr
-{
- public:
- typedef T Type;
-
- private:
- ExecContext *xc;
- Addr ptr;
-
- public:
- ExecContext *GetXC() const { return xc; }
- Addr GetPointer() const { return ptr; }
-
- public:
- explicit VPtr(ExecContext *_xc, Addr p = 0) : xc(_xc), ptr(p) { }
- template <class U>
- VPtr(const VPtr<U> &vp) : xc(vp.GetXC()), ptr(vp.GetPointer()) {}
- ~VPtr() {}
-
- bool operator!() const
- {
- return ptr == 0;
- }
-
- VPtr<T> operator+(int offset)
- {
- VPtr<T> ptr(*this);
- ptr += offset;
-
- return ptr;
- }
-
- const VPtr<T> &operator+=(int offset)
- {
- ptr += offset;
- assert((ptr & (AlphaISA::PageBytes - 1)) + sizeof(T)
- < AlphaISA::PageBytes);
-
- return *this;
- }
-
- const VPtr<T> &operator=(Addr p)
- {
- assert((p & (AlphaISA::PageBytes)) + sizeof(T) < AlphaISA::PageBytes);
- ptr = p;
-
- return *this;
- }
-
- template <class U>
- const VPtr<T> &operator=(const VPtr<U> &vp)
- {
- xc = vp.GetXC();
- ptr = vp.GetPointer();
-
- return *this;
- }
-
- operator T *()
- {
- void *addr = vtomem(xc, ptr, sizeof(T));
- return (T *)addr;
- }
-
- T *operator->()
- {
- void *addr = vtomem(xc, ptr, sizeof(T));
- return (T *)addr;
- }
-
- T &operator*()
- {
- void *addr = vtomem(xc, ptr, sizeof(T));
- return *(T *)addr;
- }
-};
-
-#endif // __ARCH_ALPHA_VPTR_HH__
diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa
index 94a8a6467..bead9c151 100644
--- a/arch/mips/isa/bitfields.isa
+++ b/arch/mips/isa/bitfields.isa
@@ -15,6 +15,7 @@ def bitfield RT_HI <20:19>;
def bitfield RT_LO <18:16>;
def bitfield RS <25:21>;
+def bitfield RS_MSB <25:25>;
def bitfield RS_HI <25:24>;
def bitfield RS_LO <23:21>;
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index acd00e70d..2ec7da805 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -66,7 +66,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x3: movn({{ if (Rt != 0) Rd = Rs; }});
}
- format Trap {
+ format WarnUnimpl {
0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
0x5: break({{ }});
0x7: sync({{ }});
@@ -131,12 +131,12 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x6: decode FUNCTION_LO {
format Trap {
- 0x0: tge({{ }});
- 0x1: tgeu({{ }});
- 0x2: tlt({{ }});
- 0x3: tltu({{ }});
- 0x4: teq({{ }});
- 0x6: tne({{ }});
+ 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
+ 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
+ 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
+ 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
+ 0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
+ 0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
}
}
}
@@ -155,12 +155,12 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode REGIMM_LO {
format Trap {
- 0x0: tgei({{ }});
- 0x1: tgeiu({{ }});
- 0x2: tlti({{ }});
- 0x3: tltiu({{ }});
- 0x4: teqi({{ }});
- 0x6: tnei({{ }});
+ 0x0: tgei({{ cond = (Rs.sw >= INTIMM; }});
+ 0x1: tgeiu({{ cond = (Rs.uw < INTIMM); }});
+ 0x2: tlti({{ cond = (Rs.sw < INTIMM); }});
+ 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
+ 0x4: teqi({{ cond = (Rs.sw == INTIMM); }});
+ 0x6: tnei({{ cond = (Rs.sw != INTIMM); }});
}
}
@@ -176,7 +176,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}
0x3: decode REGIMM_LO {
- format Trap {
+ format WarnUnimpl {
0x7: synci({{ }});
}
}
@@ -229,7 +229,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
Rt = xc->miscRegs.cop0[reg_num];
}});
- 0xC: mtc0({{
+ 0x4: mtc0({{
//The contents of the coprocessor 0 register specified by the
//combination of rd and sel are loaded into general register
//rt. Note that not all coprocessor 0 registers support the
@@ -243,6 +243,25 @@ decode OPCODE_HI default FailUnimpl::unknown() {
xc->miscRegs.cop0[reg_num] = Rt;
}});
+ 0x8: mftr({{
+ //The contents of the coprocessor 0 register specified by the
+ //combination of rd and sel are loaded into general register
+ //rt. Note that not all coprocessor 0 registers support the
+ //sel field. In those instances, the sel field must be zero.
+
+ //MT Code Needed Here
+ }});
+
+ 0xC: mttr({{
+ //The contents of the coprocessor 0 register specified by the
+ //combination of rd and sel are loaded into general register
+ //rt. Note that not all coprocessor 0 registers support the
+ //sel field. In those instances, the sel field must be zero.
+
+ //MT Code Needed Here
+ }});
+
+
0xA: rdpgpr({{
//Accessing Previous Shadow Set Register Number
uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
@@ -252,23 +271,52 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}});
}
- 0xB: decode SC {
- format BasicOp {
- 0x0: di({{
- //Accessing Coprocessor 0 "Status" Register
- Rt.sw = xc->miscRegs.cop0[12];
- xc->miscRegs.cop0[12][INTERRUPT_ENABLE] = 0;
+ 0xB: decode RD {
+
+ 0x0: decode SC {
+ format BasicOp {
+ 0x0: dvpe({{
+ Rt.sw = xc->miscRegs.cop0.MVPControl;
+ xc->miscRegs.cop0.MVPControl[EVP] = 0;
}});
- 0x1: ei({{
- //Accessing Coprocessor 0 "Status" Register
- Rt.sw = xc->miscRegs.cop0[12];
- xc->miscRegs.cop0[12][INTERRUPT_ENABLE] = 1;
+ 0x1: evpe({{
+ Rt.sw = xc->miscRegs.cop0.MVPControl;
+ xc->miscRegs.cop0.MVPControl[EVP] = 1;
}});
+ }
+ }
+
+ 0x1: decode SC {
+ format BasicOp {
+ 0x0: dmt({{
+ Rt.sw = xc->miscRegs.cop0.VPEControl;
+ xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0;
+ }});
+
+ 0x1: emt({{
+ Rt.sw = xc->miscRegs.cop0.VPEControl;
+ xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1;
+ }});
+ }
+ }
+
+ 0xC: decode SC {
+ format BasicOp {
+ 0x0: di({{
+ Rt.sw = xc->miscRegs.cop0.Status;
+ xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0;
+ }});
+
+ 0x1: ei({{
+ Rt.sw = xc->miscRegs.cop0.Status;
+ xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1;
+ }});
+ }
+ }
}
- }
- 0xE: BasicOp::wrpgpr({{
+ 0xE: BasicOp::wrpgpr({{
//Accessing Previous Shadow Set Register Number
uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
uint64_t reg_num = Rd.uw;
@@ -334,61 +382,69 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x0: decode RS_HI {
0x0: decode RS_LO {
format FloatOp {
- 0x0: add_fmt({{ }});
- 0x1: sub_fmt({{ }});
- 0x2: mul_fmt({{ }});
- 0x3: div_fmt({{ }});
- 0x4: sqrt_fmt({{ }});
- 0x5: abs_fmt({{ }});
- 0x6: mov_fmt({{ }});
- 0x7: neg_fmt({{ }});
+ 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}});
+ 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}});
+ 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}});
+ 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}});
+ 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}});
+ 0x5: abss({{ Fd.sf = abs(Fs.sf);}});
+ 0x6: movs({{ Fd.sf = Fs.sf;}});
+ 0x7: negs({{ Fd.sf = -1 * Fs.sf;}});
}
}
0x1: decode RS_LO {
//only legal for 64 bit
format Float64Op {
- 0x0: round_l({{ }});
- 0x1: trunc_l({{ }});
- 0x2: ceil_l({{ }});
- 0x3: floor_l({{ }});
+ 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}});
+ 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}});
+ 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}});
+ 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}});
}
format FloatOp {
- 0x4: round_w({{ }});
- 0x5: trunc_w({{ }});
- 0x6: ceil_w({{ }});
- 0x7: floor_w({{ }});
+ 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}});
+ 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}});
+ 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}});
+ 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}});
}
}
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp {
- 0x0: movf_fmt({{ }});
- 0x1: movt_fmt({{ }});
+ 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }});
+ 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}});
}
}
format BasicOp {
- 0x2: movz({{ if (Rt == 0) Rd = Rs; }});
- 0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+ 0x2: movzs({{ if (Rt == 0) Fd = Fs; }});
+ 0x3: movns({{ if (Rt != 0) Fd = Fs; }});
}
format Float64Op {
- 0x2: recip({{ }});
- 0x3: rsqrt{{ }});
+ 0x2: recips({{ Fd = 1 / Fs; }});
+ 0x3: rsqrts{{ Fd = 1 / sqrt(Fs); }});
}
}
0x4: decode RS_LO {
- 0x1: cvt_d({{ }});
- 0x4: cvt_w({{ }});
+ 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
+ }});
+
+ 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
+ }});
//only legal for 64 bit
format Float64Op {
- 0x5: cvt_l({{ }});
- 0x6: cvt_ps({{ }});
+ 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
+ }});
+
+ 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }});
}
}
}
@@ -397,62 +453,72 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode RS_HI {
0x0: decode RS_LO {
format FloatOp {
- 0x0: add_fmt({{ }});
- 0x1: sub_fmt({{ }});
- 0x2: mul_fmt({{ }});
- 0x3: div_fmt({{ }});
- 0x4: sqrt_fmt({{ }});
- 0x5: abs_fmt({{ }});
- 0x6: mov_fmt({{ }});
- 0x7: neg_fmt({{ }});
+ 0x0: addd({{ Fd.df = Fs.df + Ft.df;}});
+ 0x1: subd({{ Fd.df = Fs.df - Ft.df;}});
+ 0x2: muld({{ Fd.df = Fs.df * Ft.df;}});
+ 0x3: divd({{ Fd.df = Fs.df / Ft.df;}});
+ 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}});
+ 0x5: absd({{ Fd.df = abs(Fs.df);}});
+ 0x6: movd({{ Fd.df = Fs.df;}});
+ 0x7: negd({{ Fd.df = -1 * Fs.df;}});
}
}
0x1: decode RS_LO {
//only legal for 64 bit
format FloatOp64 {
- 0x0: round_l({{ }});
- 0x1: trunc_l({{ }});
- 0x2: ceil_l({{ }});
- 0x3: floor_l({{ }});
+ 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
+ 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}});
+ 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}});
+ 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}});
}
format FloatOp {
- 0x4: round_w({{ }});
- 0x5: trunc_w({{ }});
- 0x6: ceil_w({{ }});
- 0x7: floor_w({{ }});
+ 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
+ 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }});
+ 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }});
+ 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }});
}
}
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp {
- 0x0: movf_fmt({{ }});
- 0x1: movt_fmt({{ }});
+ 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }});
+ 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }});
}
}
format BasicOp {
- 0x2: movz({{ if (Rt == 0) Rd = Rs; }});
- 0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+ 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }});
+ 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }});
}
format FloatOp64 {
- 0x5: recip({{ }});
- 0x6: rsqrt{{ }});
+ 0x5: recipd({{ Fd.df = 1 / Fs.df}});
+ 0x6: rsqrtd{{ Fd.df = 1 / sqrt(Fs.df) }});
}
}
0x4: decode RS_LO {
format FloatOp {
- 0x0: cvt_s({{ }});
- 0x4: cvt_w({{ }});
+ 0x0: cvt_s_d({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE);
+ }});
+
+ 0x4: cvt_w_d({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE);
+ }});
}
//only legal for 64 bit
format FloatOp64 {
- 0x5: cvt_l({{ }});
+ 0x5: cvt_l_d({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
+ }});
}
}
}
@@ -460,8 +526,15 @@ decode OPCODE_HI default FailUnimpl::unknown() {
//Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
0x4: decode FUNCTION {
format FloatOp {
- 0x10: cvt_s({{ }});
- 0x10: cvt_d({{ }});
+ 0x10: cvt_s({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD);
+ }});
+
+ 0x10: cvt_d({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD);
+ }});
}
}
@@ -470,8 +543,15 @@ decode OPCODE_HI default FailUnimpl::unknown() {
//are enabled."
0x5: decode FUNCTION_HI {
format FloatOp {
- 0x10: cvt_s({{ }});
- 0x11: cvt_d({{ }});
+ 0x10: cvt_s_l({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG);
+ }});
+
+ 0x11: cvt_d_l({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG);
+ }});
}
}
@@ -481,36 +561,65 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x6: decode RS_HI {
0x0: decode RS_LO {
format FloatOp64 {
- 0x0: add_fmt({{ }});
- 0x1: sub_fmt({{ }});
- 0x2: mul_fmt({{ }});
- 0x5: abs_fmt({{ }});
- 0x6: mov_fmt({{ }});
- 0x7: neg_fmt({{ }});
+ 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = Fs.df + Ft.df;
+ }});
+
+ 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = Fs.df - Ft.df;
+ }});
+
+ 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = Fs.df * Ft.df;
+ }});
+
+ 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = abs(Fs.df);
+ }});
+
+ 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = Fs<31:0> | Ft<31:0>;
+ }});
+
+ 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = -1 * Fs.df;
+ }});
}
}
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp64 {
- 0x0: movf_fmt({{ }});
- 0x1: movt_fmt({{ }});
+ 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}})
+ 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}})
}
}
}
0x4: decode RS_LO {
- 0x0: FloatOp64::cvt_s_pu({{ }});
+ 0x0: FloatOp64::cvt_s_pu({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI);
+ }});
}
0x5: decode RS_LO {
format FloatOp64 {
- 0x0: cvt_s_pl({{ }});
- 0x4: pll_s_pl({{ }});
- 0x5: plu_s_pl({{ }});
- 0x6: pul_s_pl({{ }});
- 0x7: puu_s_pl({{ }});
+ 0x0: cvt_s_pl({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
+ }});
+ 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}});
+ 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}});
+ 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}});
+ 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}});
}
}
}
@@ -532,14 +641,14 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode ND {
0x0: decode TF {
- format Branch {
+ format WarnUnimpl {
0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
}
}
0x1: decode TF {
- format Branch {
+ format WarnUnimpl {
0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
}
@@ -554,46 +663,70 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x3: decode FUNCTION_HI {
0x0: decode FUNCTION_LO {
format Memory {
- 0x0: lwxc1({{ }});
- 0x1: ldxc1({{ }});
- 0x5: luxc1({{ }});
+ 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.uf; }});
+ 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }});
+ 0x5: luxc1({{ //Need to make EA<2:0> = 0
+ EA = Rs + Rt;
+ }},
+ {{ Ft<31:0> = Mem.df; }});
}
}
0x1: decode FUNCTION_LO {
format Memory {
- 0x0: swxc1({{ }});
- 0x1: sdxc1({{ }});
- 0x5: suxc1({{ }});
+ 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<31:0>; }});
+ 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<63:0>}});
+ 0x5: suxc1({{ //Need to make EA<2:0> = 0
+ EA = Rs + Rt;
+ }},
+ {{ Mem.df = Ft<63:0>;}});
0x7: prefx({{ }});
}
}
format FloatOp {
- 0x3: alnv_ps({{ }});
+ 0x3: WarnUnimpl::alnv_ps({{ }});
- 0x4: decode FUNCTION_LO {
- 0x0: madd_s({{ }});
- 0x1: madd_d({{ }});
- 0x6: madd_ps({{ }});
- }
+ format BasicOp {
+ 0x4: decode FUNCTION_LO {
+ 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }});
+ 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }});
+ 0x6: madd_ps({{
+ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = (Fs.df * Fs.df) + Fr.df;
+ }});
+ }
- 0x5: decode FUNCTION_LO {
- 0x0: msub_s({{ }});
- 0x1: msub_d({{ }});
- 0x6: msub_ps({{ }});
- }
+ 0x5: decode FUNCTION_LO {
+ 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }});
+ 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }});
+ 0x6: msub_ps({{
+ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = (Fs.df * Fs.df) - Fr.df;
+ }});
+ }
- 0x6: decode FUNCTION_LO {
- 0x0: nmadd_s({{ }});
- 0x1: nmadd_d({{ }});
- 0x6: nmadd_ps({{ }});
- }
+ 0x6: decode FUNCTION_LO {
+ 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
+ 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }});
+ 0x6: nmadd_ps({{
+ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
+ }});
+ }
- 0x7: decode FUNCTION_LO {
- 0x0: nmsub_s({{ }});
- 0x1: nmsub_d({{ }});
- 0x6: nmsub_ps({{ }});
+ 0x7: decode FUNCTION_LO {
+ 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
+ 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }});
+ 0x6: nmsub_ps({{
+ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
+ }});
+ }
}
}
}
@@ -687,17 +820,27 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}
}
+ 0x1: decode FUNCTION_LO {
+ format WarnUnimpl {
+ 0x0: fork({{ }});
+ 0x1: yield({{ }});
+ }
+ }
+
+
//Table A-10 MIPS32 BSHFL Encoding of sa Field
0x4: decode SA {
+
+ 0x02: WarnUnimpl::wsbh({{ }});
+
format BasicOp {
- 0x02: wsbh({{ }});
0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}});
0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}});
}
}
0x6: decode FUNCTION_LO {
- 0x7: BasicOp::rdhwr({{ }});
+ 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}});
}
}
};
@@ -726,24 +869,24 @@ decode OPCODE_HI default FailUnimpl::unknown() {
};
format WarnUnimpl {
- 0x4: reserved({{ }});
- 0x5: reserved({{ }});
0x7: cache({{ }});
};
};
0x6: decode OPCODE_LO default FailUnimpl::reserved() {
+ 0x0: WarnUnimpl::ll({{ }});
+
format Memory {
- 0x0: ll({{ }});
0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
};
};
0x7: decode OPCODE_LO default FailUnimpl::reserved() {
+ 0x0: WarnUnimpl::sc({{ }});
+
format Memory {
- 0x0: sc({{ }});
0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
};
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-06 23:53:35 +0000