diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/alpha/ev5.cc | 6 | ||||
-rw-r--r-- | arch/alpha/isa_desc | 17 | ||||
-rw-r--r-- | arch/alpha/pseudo_inst.cc | 19 | ||||
-rw-r--r-- | arch/alpha/pseudo_inst.hh | 3 |
4 files changed, 25 insertions, 20 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 468acdc55..f037a34ac 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -1,7 +1,6 @@ /* $Id$ */ #include "targetarch/alpha_memory.hh" -#include "sim/annotation.hh" #ifdef DEBUG #include "sim/debug.hh" #endif @@ -126,8 +125,6 @@ ExecContext::ev5_trap(Fault fault) regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault]; regs.npc = regs.pc + sizeof(MachInst); - - Annotate::Ev5Trap(this, fault); } @@ -359,7 +356,6 @@ ExecContext::setIpr(int idx, uint64_t val) old = ipr[idx]; ipr[idx] = val; kernelStats.context(old, val); - Annotate::Context(this); break; case AlphaISA::IPR_DTB_PTE: @@ -387,11 +383,9 @@ ExecContext::setIpr(int idx, uint64_t val) // only write least significant five bits - interrupt level ipr[idx] = val & 0x1f; kernelStats.swpipl(ipr[idx]); - Annotate::IPL(this, val & 0x1f); break; case AlphaISA::IPR_DTB_CM: - Annotate::ChangeMode(this, (val & 0x18) != 0); kernelStats.mode((val & 0x18) != 0); case AlphaISA::IPR_ICM: diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 0d1e7138f..9bbdac9b4 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -25,7 +25,6 @@ let {{ #include "cpu/full_cpu/dyn_inst.hh" #include "cpu/simple_cpu/simple_cpu.hh" #include "cpu/static_inst.hh" -#include "sim/annotation.hh" #include "sim/sim_exit.hh" #ifdef FULL_SYSTEM @@ -2297,8 +2296,6 @@ decode OPCODE default Unknown::unknown() { // on this PAL call (including maybe suppress it) dopal = xc->simPalCheck(palFunc); - Annotate::Callpal(xc->xcBase(), palFunc); - if (dopal) { AlphaISA::swap_palshadow(&xc->xcBase()->regs, true); xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC); @@ -2357,24 +2354,20 @@ decode OPCODE default Unknown::unknown() { // M5 special opcodes use the reserved 0x01 opcode space 0x01: decode M5FUNC { 0x00: arm({{ - if (!xc->misspeculating()) { - Annotate::ARM(xc->xcBase()); - xc->xcBase()->kernelStats.arm(); - } + if (!xc->misspeculating()) + AlphaPseudo::arm(xc->xcBase()); }}); 0x01: quiesce({{ if (!xc->misspeculating()) AlphaPseudo::quiesce(xc->xcBase()); }}); 0x10: ivlb({{ - if (!xc->misspeculating()) { - Annotate::BeginInterval(xc->xcBase()); - xc->xcBase()->kernelStats.ivlb(); - } + if (!xc->misspeculating()) + AlphaPseudo::ivlb(xc->xcBase()); }}, No_OpClass); 0x11: ivle({{ if (!xc->misspeculating()) - Annotate::EndInterval(xc->xcBase()); + AlphaPseudo::ivle(xc->xcBase()); }}, No_OpClass); 0x20: m5exit_old({{ if (!xc->misspeculating()) diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc index 194dc6400..0a5c5b006 100644 --- a/arch/alpha/pseudo_inst.cc +++ b/arch/alpha/pseudo_inst.cc @@ -30,7 +30,6 @@ #include "arch/alpha/pseudo_inst.hh" #include "cpu/exec_context.hh" -#include "sim/annotation.hh" #include "sim/param.hh" #include "sim/serialize.hh" #include "sim/sim_exit.hh" @@ -47,17 +46,33 @@ namespace AlphaPseudo bool doQuiesce; void + arm(ExecContext *xc) + { + xc->kernelStats.arm(); + } + + void quiesce(ExecContext *xc) { if (!doQuiesce) return; - Annotate::QUIESCE(xc); xc->suspend(); xc->kernelStats.quiesce(); } void + ivlb(ExecContext *xc) + { + xc->kernelStats.ivlb(); + } + + void + ivle(ExecContext *xc) + { + } + + void m5exit_old(ExecContext *xc) { SimExit(curTick, "m5_exit_old instruction encountered"); diff --git a/arch/alpha/pseudo_inst.hh b/arch/alpha/pseudo_inst.hh index 85f432504..e5551a44b 100644 --- a/arch/alpha/pseudo_inst.hh +++ b/arch/alpha/pseudo_inst.hh @@ -37,7 +37,10 @@ namespace AlphaPseudo extern bool doCheckpointInsts; extern bool doQuiesce; + void arm(ExecContext *xc); void quiesce(ExecContext *xc); + void ivlb(ExecContext *xc); + void ivle(ExecContext *xc); void m5exit(ExecContext *xc); void m5exit_old(ExecContext *xc); void resetstats(ExecContext *xc); |