5 files changed, 88 insertions, 22 deletions

diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc
index 019390aeb..a782ea330 100644
--- a/arch/alpha/arguments.cc
+++ b/arch/alpha/arguments.cc
@@ -54,7 +54,7 @@ AlphaArguments::getArg(bool fp)
 {
     if (number < 6) {
         if (fp)
-            return xc->readFloatRegInt(16 + number);
+            return xc->readFloatRegBits(16 + number);
         else
             return xc->readIntReg(16 + number);
     } else {
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 019e83dd4..fed2f5358 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -134,7 +134,7 @@ AlphaISA::zeroRegisters(CPU *cpu)
     // (no longer very clean due to the change in setIntReg() in the
     // cpu model.  Consider changing later.)
     cpu->cpuXC->setIntReg(ZeroReg, 0);
-    cpu->cpuXC->setFloatRegDouble(ZeroReg, 0.0);
+    cpu->cpuXC->setFloatReg(ZeroReg, 0.0);
 }
 
 Fault
diff --git a/arch/alpha/registerfile.hh b/arch/alpha/registerfile.hh
index c2fb56ec1..13288e087 100644
--- a/arch/alpha/registerfile.hh
+++ b/arch/alpha/registerfile.hh
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_ALPHA_REGISTERFILE_HH__
-#define __ARCH_ALPHA_REGISTERFILE_HH__
+#ifndef __ARCH_ALPHA_REGFILE_HH__
+#define __ARCH_ALPHA_REGFILE_HH__
 
 #include "arch/alpha/types.hh"
 #include "arch/alpha/constants.hh"
@@ -40,10 +40,64 @@ namespace AlphaISA
 
     typedef IntReg IntRegFile[NumIntRegs];
 
-    typedef union {
-        uint64_t q[NumFloatRegs];	// integer qword view
-        double d[NumFloatRegs];		// double-precision floating point view
-    } FloatRegFile;
+    class FloatRegFile
+    {
+      protected:
+
+        union {
+            uint64_t q[NumFloatRegs];	// integer qword view
+            double d[NumFloatRegs];	// double-precision floating point view
+        };
+
+      public:
+
+        FloatReg readReg(int floatReg)
+        {
+            return d[floatReg];
+        }
+
+        FloatReg readReg(int floatReg, int width)
+        {
+            return readReg(floatReg);
+        }
+
+        FloatRegBits readRegBits(int floatReg)
+        {
+            return q[floatReg];
+        }
+
+        FloatRegBits readRegBits(int floatReg, int width)
+        {
+            return readRegBits(floatReg);
+        }
+
+        Fault setReg(int floatReg, const FloatReg &val)
+        {
+            d[floatReg] = val;
+            return NoFault;
+        }
+
+        Fault setReg(int floatReg, const FloatReg &val, int width)
+        {
+            return setReg(floatReg, val);
+        }
+
+        Fault setRegBits(int floatReg, const FloatRegBits &val)
+        {
+            q[floatReg] = val;
+            return NoFault;
+        }
+
+        Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
+        {
+            return setRegBits(floatReg, val);
+        }
+
+        void serialize(std::ostream &os);
+
+        void unserialize(Checkpoint *cp, const std::string &section);
+
+    };
 
     class MiscRegFile {
       protected:
diff --git a/arch/alpha/types.hh b/arch/alpha/types.hh
index 7af3bebd8..3cd93c6b0 100644
--- a/arch/alpha/types.hh
+++ b/arch/alpha/types.hh
@@ -54,10 +54,8 @@ namespace AlphaISA
     typedef uint64_t IntReg;
 
     // floating point register file entry type
-    typedef union {
-        uint64_t q;
-        double d;
-    } FloatReg;
+    typedef double FloatReg;
+    typedef uint64_t FloatRegBits;
 
     // control register file contents
     typedef uint64_t MiscReg;
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 570110d84..3f836ed7e 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -1217,16 +1217,23 @@ class FloatRegOperand(Operand):
 
     def makeRead(self):
         bit_select = 0
+        width = 0;
         if (self.ctype == 'float'):
-            func = 'readFloatRegSingle'
+            func = 'readFloatReg'
+            width = 32;
         elif (self.ctype == 'double'):
-            func = 'readFloatRegDouble'
+            func = 'readFloatReg'
+            width = 64;
         else:
-            func = 'readFloatRegInt'
+            func = 'readFloatRegBits'
             if (self.size != self.dflt_size):
                 bit_select = 1
-        base = 'xc->%s(this, %d)' % \
-               (func, self.src_reg_idx)
+        if width:
+            base = 'xc->%s(this, %d, %d)' % \
+                   (func, self.src_reg_idx, width)
+        else:
+            base = 'xc->%s(this, %d)' % \
+                   (func, self.src_reg_idx)
         if bit_select:
             return '%s = bits(%s, %d, 0);\n' % \
                    (self.base_name, base, self.size-1)
@@ -1236,21 +1243,28 @@ class FloatRegOperand(Operand):
     def makeWrite(self):
         final_val = self.base_name
         final_ctype = self.ctype
+        widthSpecifier = ''
+        width = 0
         if (self.ctype == 'float'):
-            func = 'setFloatRegSingle'
+            width = 32
+            func = 'setFloatReg'
         elif (self.ctype == 'double'):
-            func = 'setFloatRegDouble'
+            width = 64
+            func = 'setFloatReg'
         else:
-            func = 'setFloatRegInt'
+            func = 'setFloatRegBits'
             final_ctype = 'uint%d_t' % self.dflt_size
             if (self.size != self.dflt_size and self.is_signed):
                 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
+        if width:
+            widthSpecifier = ', %d' % width
         wb = '''
         {
             %s final_val = %s;
-            xc->%s(this, %d, final_val);\n
+            xc->%s(this, %d, final_val%s);\n
             if (traceData) { traceData->setData(final_val); }
-        }''' % (final_ctype, final_val, func, self.dest_reg_idx)
+        }''' % (final_ctype, final_val, func, self.dest_reg_idx,
+                widthSpecifier)
         return wb
 
 class ControlRegOperand(Operand):