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-rw-r--r--arch/alpha/alpha_memory.cc4
-rw-r--r--arch/alpha/alpha_memory.hh2
-rw-r--r--arch/alpha/isa_traits.hh4
3 files changed, 5 insertions, 5 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 7c0b1120f..c79b821d0 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -204,13 +204,13 @@ AlphaTlb::serialize(ostream &os)
}
void
-AlphaTlb::unserialize(const IniFile *db, const string &section)
+AlphaTlb::unserialize(Checkpoint *cp, const string &section)
{
UNSERIALIZE_SCALAR(size);
UNSERIALIZE_SCALAR(nlu);
for (int i = 0; i < size; i++) {
- table[i].unserialize(db, csprintf("%s.PTE%d", section, i));
+ table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
if (table[i].valid) {
lookupTable.insert(make_pair(table[i].tag, i));
}
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index fc4d46191..bfcd313e2 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -74,7 +74,7 @@ class AlphaTlb : public SimObject
// Checkpointing
virtual void serialize(std::ostream &os);
- virtual void unserialize(const IniFile *db, const std::string &section);
+ virtual void unserialize(Checkpoint *cp, const std::string &section);
};
class AlphaItb : public AlphaTlb
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index fbdcffbcf..406ffb6f3 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -34,7 +34,7 @@
#include "base/misc.hh"
class FullCPU;
-class IniFile;
+class Checkpoint;
#define TARGET_ALPHA
@@ -160,7 +160,7 @@ class AlphaISA
uint8_t opcode, ra; // current instruction details (for intr's)
void serialize(std::ostream &os);
- void unserialize(const IniFile *db, const std::string &section);
+ void unserialize(Checkpoint *cp, const std::string &section);
};
static StaticInstPtr<AlphaISA> decodeInst(MachInst);