diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/alpha/alpha_memory.cc | 4 | ||||
-rw-r--r-- | arch/alpha/ev5.cc | 67 | ||||
-rw-r--r-- | arch/alpha/ev5.hh | 2 | ||||
-rw-r--r-- | arch/alpha/isa_traits.hh | 10 |
4 files changed, 79 insertions, 4 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index 1608cc4a4..23815bf01 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -425,8 +425,8 @@ AlphaDTB::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const ipr[AlphaISA::IPR_VA] = vaddr; // set MM_STAT register flags - ipr[AlphaISA::IPR_MM_STAT] = (((xc->regs.opcode & 0x3f) << 11) - | ((xc->regs.ra & 0x1f) << 6) + ipr[AlphaISA::IPR_MM_STAT] = (((OPCODE(xc->getInst()) & 0x3f) << 11) + | ((RA(xc->getInst()) & 0x1f) << 6) | (flags & 0x3f)); // set VA_FORM register with faulting formatted address diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 96d54c54c..e88f6d0a3 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -7,6 +7,7 @@ #include "base/remote_gdb.hh" #include "base/stats/events.hh" #include "cpu/exec_context.hh" +#include "cpu/fast_cpu/fast_cpu.hh" #include "sim/debug.hh" #include "sim/sim_events.hh" @@ -98,6 +99,64 @@ AlphaISA::initIPRs(RegFile *regs) } +template <class XC> +void +AlphaISA::processInterrupts(XC *xc) +{ + //Check if there are any outstanding interrupts + //Handle the interrupts + int ipl = 0; + int summary = 0; + IntReg *ipr = xc->getIprPtr(); + + check_interrupts = 0; + + if (ipr[IPR_ASTRR]) + panic("asynchronous traps not implemented\n"); + + if (ipr[IPR_SIRR]) { + for (int i = INTLEVEL_SOFTWARE_MIN; + i < INTLEVEL_SOFTWARE_MAX; i++) { + if (ipr[IPR_SIRR] & (ULL(1) << i)) { + // See table 4-19 of the 21164 hardware reference + ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; + summary |= (ULL(1) << i); + } + } + } + + uint64_t interrupts = xc->intr_status(); + + if (interrupts) { + for (int i = INTLEVEL_EXTERNAL_MIN; + i < INTLEVEL_EXTERNAL_MAX; i++) { + if (interrupts & (ULL(1) << i)) { + // See table 4-19 of the 21164 hardware reference + ipl = i; + summary |= (ULL(1) << i); + } + } + } + + if (ipl && ipl > ipr[IPR_IPLR]) { + ipr[IPR_ISR] = summary; + ipr[IPR_INTID] = ipl; + xc->trap(Interrupt_Fault); + DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", + ipr[IPR_IPLR], ipl, summary); + } + +} + +template <class XC> +void +AlphaISA::zeroRegisters(XC *xc) +{ + // Insure ISA semantics + xc->setIntReg(ZeroReg, 0); + xc->setFloatRegDouble(ZeroReg, 0.0); +} + void ExecContext::ev5_trap(Fault fault) { @@ -582,4 +641,12 @@ ExecContext::simPalCheck(int palFunc) return true; } +//Forward instantiation for FastCPU object +template +void AlphaISA::processInterrupts(FastCPU *xc); + +//Forward instantiation for FastCPU object +template +void AlphaISA::zeroRegisters(FastCPU *xc); + #endif // FULL_SYSTEM diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh index aa3d7e226..6947ef708 100644 --- a/arch/alpha/ev5.hh +++ b/arch/alpha/ev5.hh @@ -71,6 +71,8 @@ #define MM_STAT_ACV_MASK 0x0002 #define MM_STAT_WR_MASK 0x0001 +#define OPCODE(X) (X >> 26) & 0x3f +#define RA(X) (X >> 21) & 0x1f //////////////////////////////////////////////////////////////////////// // diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 05ab89978..37ba77192 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -33,6 +33,7 @@ #include "targetarch/faults.hh" #include "base/misc.hh" +class FastCPU; class FullCPU; class Checkpoint; @@ -156,8 +157,6 @@ class AlphaISA int intrflag; // interrupt flag bool pal_shadow; // using pal_shadow registers #endif // FULL_SYSTEM - // Are these architectural, or just for convenience? - uint8_t opcode, ra; // current instruction details (for intr's) void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); @@ -233,6 +232,13 @@ class AlphaISA ConfigNode *node, RegFile ®s); #endif + + /** + * Function to insure ISA semantics about 0 registers. + * @param xc The execution context. + */ + template <class XC> + static void zeroRegisters(XC *xc); }; |