diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/alpha/SConscript | 488 | ||||
| -rwxr-xr-x | arch/isa_parser.py | 51 | ||||
| -rw-r--r-- | arch/sparc/isa_desc/operands.h | 33 | ||||
| -rw-r--r-- | arch/sparc/isa_traits.cc | 57 | ||||
| -rw-r--r-- | arch/sparc/isa_traits.hh | 528 |
5 files changed, 1155 insertions, 2 deletions
diff --git a/arch/alpha/SConscript b/arch/alpha/SConscript new file mode 100644 index 000000000..2c98125bc --- /dev/null +++ b/arch/alpha/SConscript @@ -0,0 +1,488 @@ +# -*- mode:python -*- + +# Copyright (c) 2004-2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import os +import sys +from os.path import isdir + +# This file defines how to build a particular configuration of M5 +# based on variable settings in the 'env' build environment. + +# Import build environment variable from SConstruct. +Import('env') + +################################################### +# +# Define needed sources. +# +################################################### + +# Base sources used by all configurations. +arch_base_sources = Split(''' + arch/alpha/decoder.cc + arch/alpha/alpha_o3_exec.cc + arch/alpha/fast_cpu_exec.cc + arch/alpha/simple_cpu_exec.cc + arch/alpha/full_cpu_exec.cc + arch/alpha/faults.cc + arch/alpha/isa_traits.cc + ''') + +# base/circlebuf.cc +# base/copyright.cc +# base/cprintf.cc +# base/embedfile.cc +# base/fast_alloc.cc +# base/fifo_buffer.cc +# base/hostinfo.cc +# base/hybrid_pred.cc +# base/inifile.cc +# base/intmath.cc +# base/match.cc +# base/misc.cc +# base/output.cc +# base/pollevent.cc +# base/range.cc +# base/random.cc +# base/sat_counter.cc +# base/socket.cc +# base/statistics.cc +# base/str.cc +# base/time.cc +# base/trace.cc +# base/traceflags.cc +# base/userinfo.cc +# base/compression/lzss_compression.cc +# base/loader/aout_object.cc +# base/loader/ecoff_object.cc +# base/loader/elf_object.cc +# base/loader/object_file.cc +# base/loader/symtab.cc +# base/stats/events.cc +# base/stats/statdb.cc +# base/stats/visit.cc +# base/stats/text.cc +# +# cpu/base.cc +# cpu/base_dyn_inst.cc +# cpu/exec_context.cc +# cpu/exetrace.cc +# cpu/pc_event.cc +# cpu/static_inst.cc +# cpu/o3/2bit_local_pred.cc +# cpu/o3/alpha_dyn_inst.cc +# cpu/o3/alpha_cpu.cc +# cpu/o3/alpha_cpu_builder.cc +# cpu/o3/bpred_unit.cc +# cpu/o3/btb.cc +# cpu/o3/commit.cc +# cpu/o3/decode.cc +# cpu/o3/fetch.cc +# cpu/o3/free_list.cc +# cpu/o3/cpu.cc +# cpu/o3/iew.cc +# cpu/o3/inst_queue.cc +# cpu/o3/ldstq.cc +# cpu/o3/mem_dep_unit.cc +# cpu/o3/ras.cc +# cpu/o3/rename.cc +# cpu/o3/rename_map.cc +# cpu/o3/rob.cc +# cpu/o3/sat_counter.cc +# cpu/o3/store_set.cc +# cpu/o3/tournament_pred.cc +# cpu/fast/cpu.cc +# cpu/sampler/sampler.cc +# cpu/simple/cpu.cc +# cpu/trace/reader/mem_trace_reader.cc +# cpu/trace/reader/ibm_reader.cc +# cpu/trace/reader/itx_reader.cc +# cpu/trace/reader/m5_reader.cc +# cpu/trace/opt_cpu.cc +# cpu/trace/trace_cpu.cc +# +# encumbered/cpu/full/bpred.cc +# encumbered/cpu/full/commit.cc +# encumbered/cpu/full/cpu.cc +# encumbered/cpu/full/create_vector.cc +# encumbered/cpu/full/cv_spec_state.cc +# encumbered/cpu/full/dd_queue.cc +# encumbered/cpu/full/dep_link.cc +# encumbered/cpu/full/dispatch.cc +# encumbered/cpu/full/dyn_inst.cc +# encumbered/cpu/full/execute.cc +# encumbered/cpu/full/fetch.cc +# encumbered/cpu/full/floss_reasons.cc +# encumbered/cpu/full/fu_pool.cc +# encumbered/cpu/full/inst_fifo.cc +# encumbered/cpu/full/instpipe.cc +# encumbered/cpu/full/issue.cc +# encumbered/cpu/full/ls_queue.cc +# encumbered/cpu/full/machine_queue.cc +# encumbered/cpu/full/pipetrace.cc +# encumbered/cpu/full/readyq.cc +# encumbered/cpu/full/reg_info.cc +# encumbered/cpu/full/rob_station.cc +# encumbered/cpu/full/spec_memory.cc +# encumbered/cpu/full/spec_state.cc +# encumbered/cpu/full/storebuffer.cc +# encumbered/cpu/full/writeback.cc +# encumbered/cpu/full/iq/iq_station.cc +# encumbered/cpu/full/iq/iqueue.cc +# encumbered/cpu/full/iq/segmented/chain_info.cc +# encumbered/cpu/full/iq/segmented/chain_wire.cc +# encumbered/cpu/full/iq/segmented/iq_seg.cc +# encumbered/cpu/full/iq/segmented/iq_segmented.cc +# encumbered/cpu/full/iq/segmented/seg_chain.cc +# encumbered/cpu/full/iq/seznec/iq_seznec.cc +# encumbered/cpu/full/iq/standard/iq_standard.cc +# encumbered/mem/functional/main.cc +# +# mem/base_hier.cc +# mem/base_mem.cc +# mem/hier_params.cc +# mem/mem_cmd.cc +# mem/mem_debug.cc +# mem/mem_req.cc +# mem/memory_interface.cc +# mem/bus/base_interface.cc +# mem/bus/bus.cc +# mem/bus/bus_bridge.cc +# mem/bus/bus_bridge_master.cc +# mem/bus/bus_bridge_slave.cc +# mem/bus/bus_interface.cc +# mem/bus/dma_bus_interface.cc +# mem/bus/dma_interface.cc +# mem/bus/master_interface.cc +# mem/bus/slave_interface.cc +# mem/cache/base_cache.cc +# mem/cache/cache.cc +# mem/cache/cache_builder.cc +# mem/cache/coherence/coherence_protocol.cc +# mem/cache/coherence/uni_coherence.cc +# mem/cache/miss/blocking_buffer.cc +# mem/cache/miss/miss_queue.cc +# mem/cache/miss/mshr.cc +# mem/cache/miss/mshr_queue.cc +# mem/cache/prefetch/base_prefetcher.cc +# mem/cache/prefetch/prefetcher.cc +# mem/cache/prefetch/tagged_prefetcher.cc +# mem/cache/tags/base_tags.cc +# mem/cache/tags/cache_tags.cc +# mem/cache/tags/fa_lru.cc +# mem/cache/tags/iic.cc +# mem/cache/tags/lru.cc +# mem/cache/tags/repl/gen.cc +# mem/cache/tags/repl/repl.cc +# mem/cache/tags/split.cc +# mem/cache/tags/split_lru.cc +# mem/cache/tags/split_lifo.cc +# mem/functional/functional.cc +# mem/timing/base_memory.cc +# mem/timing/memory_builder.cc +# mem/timing/simple_mem_bank.cc +# mem/trace/itx_writer.cc +# mem/trace/mem_trace_writer.cc +# mem/trace/m5_writer.cc +# +# python/pyconfig.cc +# python/embedded_py.cc +# +# sim/builder.cc +# sim/configfile.cc +# sim/debug.cc +# sim/eventq.cc +# sim/main.cc +# sim/param.cc +# sim/profile.cc +# sim/root.cc +# sim/serialize.cc +# sim/sim_events.cc +# sim/sim_exit.cc +# sim/sim_object.cc +# sim/startup.cc +# sim/stat_context.cc +# sim/stat_control.cc +# sim/trace_context.cc +# ''') + +# MySql sources +arch_mysql_sources = Split(''' + ''') +# base/mysql.cc +# base/stats/mysql.cc +# ''') + +# Full-system sources +arch_full_system_sources = Split(''' + arch/alpha/alpha_memory.cc + arch/alpha/arguments.cc + arch/alpha/ev5.cc + arch/alpha/osfpal.cc + arch/alpha/pseudo_inst.cc + arch/alpha/stacktrace.cc + arch/alpha/vtophys.cc + ''') + +# base/crc.cc +# base/inet.cc +# base/remote_gdb.cc +# +# cpu/intr_control.cc +# cpu/profile.cc +# +# dev/alpha_console.cc +# dev/baddev.cc +# dev/simconsole.cc +# dev/disk_image.cc +# dev/etherbus.cc +# dev/etherdump.cc +# dev/etherint.cc +# dev/etherlink.cc +# dev/etherpkt.cc +# dev/ethertap.cc +# dev/ide_ctrl.cc +# dev/ide_disk.cc +# dev/io_device.cc +# dev/ns_gige.cc +# dev/pciconfigall.cc +# dev/pcidev.cc +# dev/pcifake.cc +# dev/pktfifo.cc +# dev/platform.cc +# dev/sinic.cc +# dev/simple_disk.cc +# dev/tsunami.cc +# dev/tsunami_cchip.cc +# dev/isa_fake.cc +# dev/tsunami_io.cc +# dev/tsunami_pchip.cc +# dev/uart.cc +# dev/uart8250.cc +# +# kern/kernel_binning.cc +# kern/kernel_stats.cc +# kern/system_events.cc +# kern/freebsd/freebsd_system.cc +# kern/linux/linux_syscalls.cc +# kern/linux/linux_system.cc +# kern/linux/printk.cc +# kern/tru64/dump_mbuf.cc +# kern/tru64/printf.cc +# kern/tru64/tru64_events.cc +# kern/tru64/tru64_syscalls.cc +# kern/tru64/tru64_system.cc +# +# mem/functional/memory_control.cc +# mem/functional/physical.cc +# +# sim/system.cc +# ''') + +# turbolaser encumbered sources +arch_turbolaser_sources = Split(''' + ''') +# encumbered/dev/dma.cc +# encumbered/dev/etherdev.cc +# encumbered/dev/scsi.cc +# encumbered/dev/scsi_ctrl.cc +# encumbered/dev/scsi_disk.cc +# encumbered/dev/scsi_none.cc +# encumbered/dev/tlaser_clock.cc +# encumbered/dev/tlaser_ipi.cc +# encumbered/dev/tlaser_mbox.cc +# encumbered/dev/tlaser_mc146818.cc +# encumbered/dev/tlaser_node.cc +# encumbered/dev/tlaser_pcia.cc +# encumbered/dev/tlaser_pcidev.cc +# encumbered/dev/tlaser_serial.cc +# encumbered/dev/turbolaser.cc +# encumbered/dev/uart8530.cc +# ''') + +# Syscall emulation (non-full-system) sources +arch_syscall_emulation_sources = Split(''' + arch/alpha/alpha_common_syscall_emul.cc + arch/alpha/alpha_linux_process.cc + arch/alpha/alpha_tru64_process.cc + ''') +# cpu/memtest/memtest.cc +# encumbered/eio/eio.cc +# encumbered/eio/exolex.cc +# encumbered/eio/libexo.cc +# sim/process.cc +# sim/syscall_emul.cc +# ''') + +#targetarch_files = Split(''' +# alpha_common_syscall_emul.hh +# alpha_linux_process.hh +# alpha_memory.hh +# alpha_tru64_process.hh +# aout_machdep.h +# arguments.hh +# byte_swap.hh +# ecoff_machdep.h +# ev5.hh +# faults.hh +# isa_fullsys_traits.hh +# isa_traits.hh +# osfpal.hh +# pseudo_inst.hh +# stacktrace.hh +# vptr.hh +# vtophys.hh +# ''') + +#for f in targetarch_files: +# env.Command('targetarch/' + f, 'arch/alpha/' + f, +# '''echo '#include "arch/alpha/%s"' > $TARGET''' % f) + + +# Set up complete list of sources based on configuration. +sources = arch_base_sources + +if env['FULL_SYSTEM']: + sources += arch_full_system_sources + if env['ALPHA_TLASER']: + sources += arch_turbolaser_sources +else: + sources += arch_syscall_emulation_sources + +if env['USE_MYSQL']: + sources += arch_mysql_sources + +for opt in env.ExportOptions: + env.ConfigFile(opt) + +################################################### +# +# Special build rules. +# +################################################### + +# base/traceflags.{cc,hh} are generated from base/traceflags.py. +# $TARGET.base will expand to "<build-dir>/base/traceflags". +# env.Command(Split('base/traceflags.hh base/traceflags.cc'), +# 'base/traceflags.py', +# 'python $SOURCE $TARGET.base') + +# several files are generated from arch/$TARGET_ISA/isa_desc. +#env.Command(Split('''decoder.cc +# decoder.hh +# alpha_o3_exec.cc +# fast_cpu_exec.cc +# simple_cpu_exec.cc +# full_cpu_exec.cc'''), +# Split('''isa_desc +# ../isa_parser.py'''), +# '$SRCDIR/arch/isa_parser.py $SOURCE $TARGET.dir arch/alpha') + + +# libelf build is described in its own SConscript file. +# SConscript-local is the per-config build, which just copies some +# header files into a place where they can be found. +# SConscript('libelf/SConscript-local', exports = 'env', duplicate=0) +# SConscript('python/SConscript', exports = ['env'], duplicate=0) + +# This function adds the specified sources to the given build +# environment, and returns a list of all the corresponding SCons +# Object nodes (including an extra one for date.cc). We explicitly +# add the Object nodes so we can set up special dependencies for +# date.cc. +# def make_objs(sources, env): +# objs = [env.Object(s) for s in sources] +# # make date.cc depend on all other objects so it always gets +# # recompiled whenever anything else does +# date_obj = env.Object('base/date.cc') +# base/traceflags.{cc,hh} are generated from base/traceflags.py. +# $TARGET.base will expand to "<build-dir>/base/traceflags". +# env.Command(Split('base/traceflags.hh base/traceflags.cc'), +# 'base/traceflags.py', +# 'python $SOURCE $TARGET.base') +# +# Split('''arch/alpha/isa_desc +# arch/isa_parser.py'''), +# env.Depends(date_obj, objs) +# objs.append(date_obj) +# return objs + +################################################### +# +# Define binaries. Each different build type (debug, opt, etc.) gets +# a slightly different build environment. +# +################################################### + +# Include file paths are rooted in this directory. SCons will +# automatically expand '.' to refer to both the source directory and +# the corresponding build directory to pick up generated include +# files. +# env.Append(CPPPATH='.') + +# Debug binary +# debugEnv = env.Copy(OBJSUFFIX='.do') +# debugEnv.Label = 'debug' +# debugEnv.Append(CCFLAGS=Split('-g -gstabs+ -O0')) +# debugEnv.Append(CPPDEFINES='DEBUG') +# tlist = debugEnv.Program(target = 'm5.debug', +# source = make_objs(sources, debugEnv)) +# debugEnv.M5Binary = tlist[0] + +# Optimized binary +# optEnv = env.Copy() +# optEnv.Label = 'opt' +# optEnv.Append(CCFLAGS=Split('-g -O5')) +# tlist = optEnv.Program(target = 'm5.opt', +# source = make_objs(sources, optEnv)) +# optEnv.M5Binary = tlist[0] + +# "Fast" binary +# fastEnv = env.Copy(OBJSUFFIX='.fo') +# fastEnv.Label = 'fast' +# fastEnv.Append(CCFLAGS=Split('-O5')) +# fastEnv.Append(CPPDEFINES='NDEBUG') +# fastEnv.Program(target = 'm5.fast.unstripped', +# source = make_objs(sources, fastEnv)) +# tlist = fastEnv.Command(target = 'm5.fast', +# source = 'm5.fast.unstripped', +# action = 'strip $SOURCE -o $TARGET') +# fastEnv.M5Binary = tlist[0] + +# Profiled binary +# profEnv = env.Copy(OBJSUFFIX='.po') +# profEnv.Label = 'prof' +# profEnv.Append(CCFLAGS=Split('-O5 -g -pg'), LINKFLAGS='-pg') +# tlist = profEnv.Program(target = 'm5.prof', +# source = make_objs(sources, profEnv)) +# profEnv.M5Binary = tlist[0] +# +# envList = [debugEnv, optEnv, fastEnv, profEnv] +# +# Return('envList') +Return('sources') diff --git a/arch/isa_parser.py b/arch/isa_parser.py index 8f4c6bce7..6a8935963 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -91,6 +91,14 @@ tokens = reserved + ( # C preprocessor directives 'CPPDIRECTIVE' + +# The following are matched but never returned. commented out to +# suppress PLY warning + # newfile directive +# 'NEWFILE', + + # endfile directive +# 'ENDFILE' ) # Regular expressions for token matching @@ -149,10 +157,20 @@ def t_CODELIT(t): return t def t_CPPDIRECTIVE(t): - r'^\#.*\n' + r'^\#[^\#].*\n' t.lineno += t.value.count('\n') return t +def t_NEWFILE(t): + r'^\#\#newfile[ /t]*\"[A-Za-z0-9\\/-_.]*\"' + global fileNameStack + fileNameStack.append((t.value[11:-1], t.lineno)) + t.lineno = 0 + +def t_ENDFILE(t): + r'^\#\#endfile' + (filename, t.lineno) = fileNameStack.pop() + # # The functions t_NEWLINE, t_ignore, and t_error are # special for the lex module. @@ -852,7 +870,12 @@ def fixPythonIndentation(s): # Error handler. Just call exit. Output formatted to work under # Emacs compile-mode. def error(lineno, string): - sys.exit("%s:%d: %s" % (input_filename, lineno, string)) + global fileNameStack + spaces = "" + for (filename, line) in fileNameStack[0:-1]: + print spaces + "In file included from " + filename + spaces += " " + sys.exit(spaces + "%s:%d: %s" % (fileNameStack[-1][0], lineno, string)) # Like error(), but include a Python stack backtrace (for processing # Python exceptions). @@ -1601,6 +1624,25 @@ def update_if_needed(file, contents): f.write(contents) f.close() +# This regular expression matches include directives +regExp = re.compile('(?P<include>^[ \t]*##include[ \t]*\"[ \t]*(?P<filename>[A-Za-z0-9\\/-_.]*)[ \t]*\"[ \t]*\n)', re.MULTILINE) + +def preprocess_isa_desc(isa_desc): + # Find any includes and include them + + # Look for an include + m = re.search(regExp, isa_desc) + while m: + filename = m.group('filename') + print 'Including file "%s"' % filename + includeFile = open(filename) + includecontents = includeFile.read() + isa_desc = isa_desc[:m.start('include')] + '##newfile "' + filename + '"\n' + includecontents + '##endfile\n' + isa_desc[m.end('include'):] + # Look for the next include + m = re.search(regExp, isa_desc) + return isa_desc + + # # Read in and parse the ISA description. # @@ -1608,12 +1650,17 @@ def parse_isa_desc(isa_desc_file, output_dir, include_path): # set a global var for the input filename... used in error messages global input_filename input_filename = isa_desc_file + global fileNameStack + fileNameStack = [(input_filename, 1)] # Suck the ISA description file in. input = open(isa_desc_file) isa_desc = input.read() input.close() + # Perform Preprocessing + isa_desc = preprocess_isa_desc(isa_desc) + # Parse it. (isa_name, namespace, global_code, namespace_code) = yacc.parse(isa_desc) diff --git a/arch/sparc/isa_desc/operands.h b/arch/sparc/isa_desc/operands.h new file mode 100644 index 000000000..77de6c9c4 --- /dev/null +++ b/arch/sparc/isa_desc/operands.h @@ -0,0 +1,33 @@ +def operand_types {{ + 'sb' : ('signed int', 8), + 'ub' : ('unsigned int', 8), + 'shw' : ('signed int', 16), + 'uhw' : ('unsigned int', 16), + 'sw' : ('signed int', 32), + 'uw' : ('unsigned int', 32), + 'sdw' : ('signed int', 64), + 'udw' : ('unsigned int', 64), + 'sf' : ('float', 32), + 'df' : ('float', 64), + 'qf' : ('float', 128) +}}; + +def operands {{ + # Int regs default to unsigned, but code should not count on this. + # For clarity, descriptions that depend on unsigned behavior should + # explicitly specify '.uq'. + 'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1), + 'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2), + 'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3), + #'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1), + #'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2), + #'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3), + 'Mem': MemOperandTraits('udw', None, + ('IsMemRef', 'IsLoad', 'IsStore'), 4) + #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4), + #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1), + #'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1), + # The next two are hacks for non-full-system call-pal emulation + #'R0': IntRegOperandTraits('uq', '0', None, 1), + #'R16': IntRegOperandTraits('uq', '16', None, 1) +}}; diff --git a/arch/sparc/isa_traits.cc b/arch/sparc/isa_traits.cc new file mode 100644 index 000000000..c7a25f88d --- /dev/null +++ b/arch/sparc/isa_traits.cc @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/sparc/isa_traits.hh" +#include "cpu/static_inst.hh" +#include "sim/serialize.hh" + +// Alpha UNOP (ldq_u r31,0(r0)) +const MachInst SPARCISA::NoopMachInst = 0x2ffe0000; + +void +SPARCISA::RegFile::serialize(std::ostream &os) +{ + intRegFile.serialize(os); + floatRegFile.serialize(os); + miscRegs.serialize(os); + SERIALIZE_SCALAR(pc); + SERIALIZE_SCALAR(npc); +} + + +void +AlphaISA::RegFile::unserialize(Checkpoint *cp, const std::string §ion) +{ + intRegFile.unserialize(cp, section); + floatRegFile.unserialize(cp, section); + miscRegs.unserialize(cp, section); + UNSERIALIZE_SCALAR(pc); + UNSERIALIZE_SCALAR(npc); +} + +#endif //FULL_SYSTEM diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh new file mode 100644 index 000000000..9513b99fc --- /dev/null +++ b/arch/sparc/isa_traits.hh @@ -0,0 +1,528 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ +#define __ARCH_SPARC_ISA_TRAITS_HH__ + +#include "arch/sparc/faults.hh" +#include "base/misc.hh" +#include "sim/host.hh" + +class FastCPU; +//class FullCPU; +//class Checkpoint; + +#define TARGET_SPARC + +template <class ISA> class StaticInst; +template <class ISA> class StaticInstPtr; + +//namespace EV5 +//{ +// int DTB_ASN_ASN(uint64_t reg); +// int ITB_ASN_ASN(uint64_t reg); +//} + +class SPARCISA +{ + public: + + typedef uint32_t MachInst; + typedef uint64_t Addr; + typedef uint8_t RegIndex; + + enum + { + MemoryEnd = 0xffffffffffffffffULL, + + NumFloatRegs = 32, + NumMiscRegs = 32, + + MaxRegsOfAnyType = 32, + // Static instruction parameters + MaxInstSrcRegs = 3, + MaxInstDestRegs = 2, + + // Maximum trap level + MaxTL = 4 + + // semantically meaningful register indices + ZeroReg = 0, // architecturally meaningful + // the rest of these depend on the ABI + } + typedef uint64_t IntReg; + + class IntRegFile + { + private: + //For right now, let's pretend the register file is static + IntReg regs[32]; + public: + IntReg & operator [] (RegIndex index) + { + //Don't allow indexes outside of the 32 registers + index &= 0x1F + return regs[index]; + } + }; + + void inline serialize(std::ostream & os) + { + SERIALIZE_ARRAY(regs, 32); + } + + void inline unserialize(Checkpoint &*cp, const std::string §ion) + { + UNSERIALIZE_ARRAY(regs, 32); + } + + class FloatRegFile + { + private: + //By using the largest data type, we ensure everything + //is aligned correctly in memory + union + { + double double rawRegs[16]; + uint64_t regDump[32]; + }; + class QuadRegs + { + private: + FloatRegFile * parent; + public: + QuadRegs(FloatRegFile * p) : parent(p) {;} + double double & operator [] (RegIndex index) + { + //Quad floats are index by the single + //precision register the start on, + //and only 16 should be accessed + index = (index >> 2) & 0xF; + return parent->rawRegs[index]; + } + }; + class DoubleRegs + { + private: + FloatRegFile * parent; + public: + DoubleRegs(FloatRegFile * p) : parent(p) {;} + double & operator [] (RegIndex index) + { + //Double floats are index by the single + //precision register the start on, + //and only 32 should be accessed + index = (index >> 1) & 0x1F + return ((double [])parent->rawRegs)[index]; + } + } + class SingleRegs + { + private: + FloatRegFile * parent; + public: + SingleRegs(FloatRegFile * p) : parent(p) {;} + double & operator [] (RegFile index) + { + //Only 32 single floats should be accessed + index &= 0x1F + return ((float [])parent->rawRegs)[index]; + } + } + public: + void inline serialize(std::ostream & os) + { + SERIALIZE_ARRAY(regDump, 32); + } + + void inline unserialize(Checkpoint &* cp, std::string & section) + { + UNSERIALIZE_ARRAY(regDump, 32); + } + + QuadRegs quadRegs; + DoubleRegs doubleRegs; + SingleRegs singleRegs; + FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this) + {;} + }; + + // control register file contents + typedef uint64_t MiscReg; + // The control registers, broken out into fields + class MiscRegFile + { + public: + union + { + uint16_t pstate; // Process State Register + struct + { + uint16_t ag:1; // Alternate Globals + uint16_t ie:1; // Interrupt enable + uint16_t priv:1; // Privelege mode + uint16_t am:1; // Address mask + uint16_t pef:1; // PSTATE enable floating-point + uint16_t red:1; // RED (reset, error, debug) state + uint16_t mm:2; // Memory Model + uint16_t tle:1; // Trap little-endian + uint16_t cle:1; // Current little-endian + } pstateFields; + } + uint64_t tba; // Trap Base Address + union + { + uint64_t y; // Y (used in obsolete multiplication) + struct + { + uint64_t value:32; // The actual value stored in y + const uint64_t :32; // reserved bits + } yFields; + } + uint8_t pil; // Process Interrupt Register + uint8_t cwp; // Current Window Pointer + uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured on the previous level) + union + { + uint8_t ccr; // Condition Code Register + struct + { + union + { + uint8_t icc:4; // 32-bit condition codes + struct + { + uint8_t c:1; // Carry + uint8_t v:1; // Overflow + uint8_t z:1; // Zero + uint8_t n:1; // Negative + } iccFields:4; + } :4; + union + { + uint8_t xcc:4; // 64-bit condition codes + struct + { + uint8_t c:1; // Carry + uint8_t v:1; // Overflow + uint8_t z:1; // Zero + uint8_t n:1; // Negative + } xccFields:4; + } :4; + } ccrFields; + } + uint8_t asi; // Address Space Identifier + uint8_t tl; // Trap Level + uint64_t tpc[MaxTL]; // Trap Program Counter (value from previous trap level) + uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from previous trap level) + union + { + uint64_t tstate[MaxTL]; // Trap State + struct + { + //Values are from previous trap level + uint64_t cwp:5; // Current Window Pointer + const uint64_t :2; // Reserved bits + uint64_t pstate:10; // Process State + const uint64_t :6; // Reserved bits + uint64_t asi:8; // Address Space Identifier + uint64_t ccr:8; // Condition Code Register + } tstateFields[MaxTL]; + } + union + { + uint64_t tick; // Hardware clock-tick counter + struct + { + uint64_t counter:63; // Clock-tick count + uint64_t npt:1; // Non-priveleged trap + } tickFields; + } + uint8_t cansave; // Savable windows + uint8_t canrestore; // Restorable windows + uint8_t otherwin; // Other windows + uint8_t cleanwin; // Clean windows + union + { + uint8_t wstate; // Window State + struct + { + uint8_t normal:3; // Bits TT<4:2> are set to on a normal + // register window trap + uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin" + // register window trap + } wstateFields; + } + union + { + uint64_t ver; // Version + struct + { + uint64_t maxwin:5; // Max CWP value + const uint64_t :2; // Reserved bits + uint64_t maxtl:8; // Maximum trap level + const uint64_t :8; // Reserved bits + uint64_t mask:8; // Processor mask set revision number + uint64_t impl:16; // Implementation identification number + uint64_t manuf:16; // Manufacturer code + } verFields; + } + union + { + uint64_t fsr; // Floating-Point State Register + struct + { + union + { + uint64_t cexc:5; // Current excpetion + struct + { + uint64_t nxc:1; // Inexact + uint64_t dzc:1; // Divide by zero + uint64_t ufc:1; // Underflow + uint64_t ofc:1; // Overflow + uint64_t nvc:1; // Invalid operand + } cexecFields:5; + } :5; + union + { + uint64_t aexc:5; // Accrued exception + struct + { + uint64_t nxc:1; // Inexact + uint64_t dzc:1; // Divide by zero + uint64_t ufc:1; // Underflow + uint64_t ofc:1; // Overflow + uint64_t nvc:1; // Invalid operand + } aexecFields:5; + } :5; + uint64_t fcc0:2; // Floating-Point condtion codes + const uint64_t :1; // Reserved bits + uint64_t qne:1; // Deferred trap queue not empty + // with no queue, it should read 0 + uint64_t ftt:3; // Floating-Point trap type + uint64_t ver:3; // Version (of the FPU) + const uint64_t :2; // Reserved bits + uint64_t ns:1; // Nonstandard floating point + union + { + uint64_t tem:5; // Trap Enable Mask + struct + { + uint64_t nxm:1; // Inexact + uint64_t dzm:1; // Divide by zero + uint64_t ufm:1; // Underflow + uint64_t ofm:1; // Overflow + uint64_t nvm:1; // Invalid operand + } temFields:5; + } :5; + const uint64_t :2; // Reserved bits + uint64_t rd:2; // Rounding direction + uint64_t fcc1:2; // Floating-Point condition codes + uint64_t fcc2:2; // Floating-Point condition codes + uint64_t fcc3:2; // Floating-Point condition codes + const uint64_t :26; // Reserved bits + } fsrFields; + } + union + { + uint8_t fprs; // Floating-Point Register State + struct + { + dl:1; // Dirty lower + du:1; // Dirty upper + fef:1; // FPRS enable floating-Point + } fprsFields; + }; + + void serialize(std::ostream & os) + { + SERIALIZE_SCALAR(pstate); + SERIAlIZE_SCALAR(tba); + SERIALIZE_SCALAR(y); + SERIALIZE_SCALAR(pil); + SERIALIZE_SCALAR(cwp); + SERIALIZE_ARRAY(tt, MaxTL); + SERIALIZE_SCALAR(ccr); + SERIALIZE_SCALAR(asi); + SERIALIZE_SCALAR(tl); + SERIALIZE_SCALAR(tpc); + SERIALIZE_SCALAR(tnpc); + SERIALIZE_ARRAY(tstate, MaxTL); + SERIALIZE_SCALAR(tick); + SERIALIZE_SCALAR(cansave); + SERIALIZE_SCALAR(canrestore); + SERIALIZE_SCALAR(otherwin); + SERIALIZE_SCALAR(cleanwin); + SERIALIZE_SCALAR(wstate); + SERIALIZE_SCALAR(ver); + SERIALIZE_SCALAR(fsr); + SERIALIZE_SCALAR(fprs); + } + + void unserialize(Checkpoint &* cp, std::string & section) + { + UNSERIALIZE_SCALAR(pstate); + UNSERIAlIZE_SCALAR(tba); + UNSERIALIZE_SCALAR(y); + UNSERIALIZE_SCALAR(pil); + UNSERIALIZE_SCALAR(cwp); + UNSERIALIZE_ARRAY(tt, MaxTL); + UNSERIALIZE_SCALAR(ccr); + UNSERIALIZE_SCALAR(asi); + UNSERIALIZE_SCALAR(tl); + UNSERIALIZE_SCALAR(tpc); + UNSERIALIZE_SCALAR(tnpc); + UNSERIALIZE_ARRAY(tstate, MaxTL); + UNSERIALIZE_SCALAR(tick); + UNSERIALIZE_SCALAR(cansave); + UNSERIALIZE_SCALAR(canrestore); + UNSERIALIZE_SCALAR(otherwin); + UNSERIALIZE_SCALAR(cleanwin); + UNSERIALIZE_SCALAR(wstate); + UNSERIALIZE_SCALAR(ver); + UNSERIALIZE_SCALAR(fsr); + UNSERIALIZE_SCALAR(fprs); + } + }; + + typedef union + { + IntReg intreg; + FloatReg fpreg; + MiscReg ctrlreg; + } AnyReg; + + struct RegFile + { + IntRegFile intRegFile; // (signed) integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegFile; // control register file + + Addr pc; // Program Counter + Addr npc; // Next Program Counter + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); + }; + + static StaticInstPtr<AlphaISA> decodeInst(MachInst); + + // return a no-op instruction... used for instruction fetch faults + static const MachInst NoopMachInst; + + // Instruction address compression hooks + static inline Addr realPCToFetchPC(const Addr &addr) + { + return addr; + } + + static inline Addr fetchPCToRealPC(const Addr &addr) + { + return addr; + } + + // the size of "fetched" instructions (not necessarily the size + // of real instructions for PISA) + static inline size_t fetchInstSize() + { + return sizeof(MachInst); + } + + /** + * Function to insure ISA semantics about 0 registers. + * @param xc The execution context. + */ + template <class XC> + static void zeroRegisters(XC *xc); +}; + + +typedef SPARCISA TheISA; + +typedef TheISA::MachInst MachInst; +typedef TheISA::Addr Addr; +typedef TheISA::RegIndex RegIndex; +typedef TheISA::IntReg IntReg; +typedef TheISA::IntRegFile IntRegFile; +typedef TheISA::FloatReg FloatReg; +typedef TheISA::FloatRegFile FloatRegFile; +typedef TheISA::MiscReg MiscReg; +typedef TheISA::MiscRegFile MiscRegFile; +typedef TheISA::AnyReg AnyReg; +typedef TheISA::RegFile RegFile; + +const int VMPageSize = TheISA::VMPageSize; +const int LogVMPageSize = TheISA::LogVMPageSize; +const int ZeroReg = TheISA::ZeroReg; +const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; +const int MaxAddr = (Addr)-1; + +#ifndef FULL_SYSTEM +class SyscallReturn { + public: + template <class T> + SyscallReturn(T v, bool s) + { + retval = (uint64_t)v; + success = s; + } + + template <class T> + SyscallReturn(T v) + { + success = (v >= 0); + retval = (uint64_t)v; + } + + ~SyscallReturn() {} + + SyscallReturn& operator=(const SyscallReturn& s) { + retval = s.retval; + success = s.success; + return *this; + } + + bool successful() { return success; } + uint64_t value() { return retval; } + + + private: + uint64_t retval; + bool success; +}; + +#endif + + +#ifdef FULL_SYSTEM + +#include "arch/alpha/ev5.hh" +#endif + +#endif // __ARCH_SPARC_ISA_TRAITS_HH__ |