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-rw-r--r--arch/alpha/alpha_memory.cc72
-rw-r--r--arch/alpha/ev5.hh20
-rw-r--r--arch/alpha/vtophys.cc12
3 files changed, 64 insertions, 40 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 23815bf01..31f5a9b20 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -44,6 +44,11 @@ using namespace std;
//
// Alpha TLB
//
+#ifdef DEBUG
+bool uncacheBit39 = false;
+bool uncacheBit40 = false;
+#endif
+
AlphaTLB::AlphaTLB(const string &name, int s)
: SimObject(name), size(s), nlu(0)
{
@@ -87,24 +92,27 @@ AlphaTLB::checkCacheability(MemReqPtr &req)
{
// in Alpha, cacheability is controlled by upper-level bits of the
// physical address
- if (req->paddr & PA_UNCACHED_BIT) {
- if (PA_IPR_SPACE(req->paddr)) {
- // IPR memory space not implemented
- if (!req->xc->misspeculating()) {
- switch (req->paddr) {
- case ULL(0xFFFFF00188):
- req->data = 0;
- break;
-
- default:
- panic("IPR memory space not implemented! PA=%x\n",
- req->paddr);
- }
- }
- } else {
- // mark request as uncacheable
- req->flags |= UNCACHEABLE;
- }
+
+ /*
+ * We support having the uncacheable bit in either bit 39 or bit 40.
+ * The Turbolaser platform (and EV5) support having the bit in 39, but
+ * Tsunami (which Linux assumes uses an EV6) generates accesses with
+ * the bit in 40. So we must check for both, but we have debug flags
+ * to catch a weird case where both are used, which shouldn't happen.
+ */
+
+ if (req->paddr & PA_UNCACHED_BIT_43) {
+ // IPR memory space not implemented
+ if (PA_IPR_SPACE(req->paddr))
+ if (!req->xc->misspeculating())
+ panic("IPR memory space not implemented! PA=%x\n",
+ req->paddr);
+
+ // mark request as uncacheable
+ req->flags |= UNCACHEABLE;
+
+ // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
+ req->paddr &= PA_UNCACHED_MASK;
}
}
@@ -290,10 +298,10 @@ AlphaITB::translate(MemReqPtr &req) const
return ITB_Acv_Fault;
}
- // Check for "superpage" mapping: when SP<1> is set, and
- // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
- if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
- VA_SPACE(req->vaddr) == 2) {
+
+ // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
+ // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
+ if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
// only valid in kernel mode
if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) {
@@ -303,6 +311,13 @@ AlphaITB::translate(MemReqPtr &req) const
}
req->paddr = req->vaddr & PA_IMPL_MASK;
+
+ // sign extend the physical address properly
+ if (req->paddr & PA_UNCACHED_BIT_40)
+ req->paddr |= ULL(0xf0000000000);
+ else
+ req->paddr &= ULL(0xffffffffff);
+
} else {
// not a physical address: need to look up pte
AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr),
@@ -468,10 +483,8 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
return DTB_Fault_Fault;
}
- // Check for "superpage" mapping: when SP<1> is set, and
- // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
- if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
- VA_SPACE(req->vaddr) == 2) {
+ // Check for "superpage" mapping
+ if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
// only valid in kernel mode
if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
@@ -484,6 +497,13 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
}
req->paddr = req->vaddr & PA_IMPL_MASK;
+
+ // sign extend the physical address properly
+ if (req->paddr & PA_UNCACHED_BIT_40)
+ req->paddr |= ULL(0xf0000000000);
+ else
+ req->paddr &= ULL(0xffffffffff);
+
} else {
if (write)
write_accesses++;
diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index 6947ef708..517e1111f 100644
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -32,8 +32,8 @@
#define ALT_MODE_AM(X) (((X) >> 3) & 0x3)
#define DTB_CM_CM(X) (((X) >> 3) & 0x3)
-#define DTB_ASN_ASN(X) (((X) >> 57) & 0x7f)
-#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
+#define DTB_ASN_ASN(X) (((X) >> 57) & 0xff)
+#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
#define DTB_PTE_XRE(X) (((X) >> 8) & 0xf)
#define DTB_PTE_XWE(X) (((X) >> 12) & 0xf)
#define DTB_PTE_FONR(X) (((X) >> 1) & 0x1)
@@ -42,8 +42,8 @@
#define DTB_PTE_ASMA(X) (((X) >> 4) & 0x1)
#define ICM_CM(X) (((X) >> 3) & 0x3)
-#define ITB_ASN_ASN(X) (((X) >> 4) & 0x7f)
-#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
+#define ITB_ASN_ASN(X) (((X) >> 4) & 0xff)
+#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
#define ITB_PTE_XRE(X) (((X) >> 8) & 0xf)
#define ITB_PTE_FONR(X) (((X) >> 1) & 0x1)
#define ITB_PTE_FONW(X) (((X) >> 2) & 0x1)
@@ -54,12 +54,16 @@
#define VA_IMPL_MASK ULL(0x000007ffffffffff)
#define VA_IMPL(X) ((X) & VA_IMPL_MASK)
#define VA_VPN(X) (VA_IMPL(X) >> 13)
-#define VA_SPACE(X) (((X) >> 41) & 0x3)
+#define VA_SPACE_EV5(X) (((X) >> 41) & 0x3)
+#define VA_SPACE_EV6(X) (((X) >> 41) & 0x7f)
#define VA_POFS(X) ((X) & 0x1fff)
-#define PA_IMPL_MASK ULL(0xffffffffff)
-#define PA_UNCACHED_BIT ULL(0x8000000000)
-#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFF00000))
+#define PA_IMPL_MASK ULL(0xfffffffffff) // for Tsunami
+#define PA_UNCACHED_BIT_39 ULL(0x8000000000)
+#define PA_UNCACHED_BIT_40 ULL(0x10000000000)
+#define PA_UNCACHED_BIT_43 ULL(0x80000000000)
+#define PA_UNCACHED_MASK ULL(0x807ffffffff) // Clear PA<42:35>
+#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFFF00000))
#define PA_PFN2PA(X) ((X) << 13)
diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc
index 5e14b06d3..d91d80c83 100644
--- a/arch/alpha/vtophys.cc
+++ b/arch/alpha/vtophys.cc
@@ -96,20 +96,20 @@ vtophys(ExecContext *xc, Addr vaddr)
{
Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
Addr paddr = 0;
- if (PC_PAL(vaddr)) {
- paddr = vaddr & ~ULL(1);
- } else if (!ptbr) {
- paddr = vaddr;
- } else {
+// if (PC_PAL(vaddr)) {
+// paddr = vaddr & ~ULL(1);
+// } else {
if (vaddr >= ALPHA_K0SEG_BASE && vaddr <= ALPHA_K0SEG_END) {
paddr = ALPHA_K0SEG_TO_PHYS(vaddr);
+ } else if (!ptbr) {
+ paddr = vaddr;
} else {
Addr pte = kernel_pte_lookup(xc->physmem, ptbr, vaddr);
uint64_t entry = xc->physmem->phys_read_qword(pte);
if (pte && entry_valid(entry))
paddr = PMAP_PTE_PA(entry) | (vaddr & PGOFSET);
}
- }
+// }
DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 16:38:01 +0000