diff options
Diffstat (limited to 'configs/common/CacheConfig.py')
| -rw-r--r-- | configs/common/CacheConfig.py | 29 |
1 files changed, 23 insertions, 6 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 00517dfc4..364b20f28 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -32,11 +32,17 @@ import m5 from m5.objects import * from Caches import * +from O3_ARM_v7a import * def config_cache(options, system): if options.l2cache: - system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, - block_size=options.cacheline_size) + if options.cpu_type == "arm_detailed": + system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc, + block_size=options.cacheline_size) + else: + system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, + block_size=options.cacheline_size) + system.tol2bus = Bus() system.l2.cpu_side = system.tol2bus.port system.l2.mem_side = system.membus.port @@ -44,10 +50,21 @@ def config_cache(options, system): for i in xrange(options.num_cpus): if options.caches: - icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, - block_size=options.cacheline_size) - dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, - block_size=options.cacheline_size) + if options.cpu_type == "arm_detailed": + icache = O3_ARM_v7a_ICache(size = options.l1i_size, + assoc = options.l1i_assoc, + block_size=options.cacheline_size) + dcache = O3_ARM_v7a_DCache(size = options.l1d_size, + assoc = options.l1d_assoc, + block_size=options.cacheline_size) + else: + icache = L1Cache(size = options.l1i_size, + assoc = options.l1i_assoc, + block_size=options.cacheline_size) + dcache = L1Cache(size = options.l1d_size, + assoc = options.l1d_assoc, + block_size=options.cacheline_size) + if buildEnv['TARGET_ISA'] == 'x86': system.cpu[i].addPrivateSplitL1Caches(icache, dcache, PageTableWalkerCache(), |