diff options
Diffstat (limited to 'configs/common/CacheConfig.py')
| -rw-r--r-- | configs/common/CacheConfig.py | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 288a633ce..4b4ce7553 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012 ARM Limited +# Copyright (c) 2012-2013 ARM Limited # All rights reserved # # The license below extends only to copyright in the software and shall @@ -64,12 +64,13 @@ def config_cache(options, system): # are not connected using addTwoLevelCacheHierarchy. Use the # same clock as the CPUs, and set the L1-to-L2 bus width to 32 # bytes (256 bits). - system.l2 = l2_cache_class(clock=options.cpu_clock, + system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain, size=options.l2_size, assoc=options.l2_assoc, block_size=options.cacheline_size) - system.tol2bus = CoherentBus(clock = options.cpu_clock, width = 32) + system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain, + width = 32) system.l2.cpu_side = system.tol2bus.master system.l2.mem_side = system.membus.slave |