diff options
Diffstat (limited to 'configs/common/Caches.py')
| -rw-r--r-- | configs/common/Caches.py | 28 |
1 files changed, 20 insertions, 8 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py index f16a83559..0b5f9e182 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -1,3 +1,15 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # @@ -31,8 +43,8 @@ from m5.objects import * class L1Cache(BaseCache): assoc = 2 block_size = 64 - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 mshrs = 10 tgts_per_mshr = 20 is_top_level = True @@ -40,16 +52,16 @@ class L1Cache(BaseCache): class L2Cache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 20 tgts_per_mshr = 12 class PageTableWalkerCache(BaseCache): assoc = 2 block_size = 64 - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 mshrs = 10 size = '1kB' tgts_per_mshr = 12 @@ -58,8 +70,8 @@ class PageTableWalkerCache(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 |