diff options
Diffstat (limited to 'configs/common/O3_ARM_v7a.py')
| -rw-r--r-- | configs/common/O3_ARM_v7a.py | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index dbfdf6c41..9f250f57d 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -142,7 +142,7 @@ class O3_ARM_v7a_3(DerivO3CPU): branchPred = O3_ARM_v7a_BP() # Instruction Cache -class O3_ARM_v7a_ICache(BaseCache): +class O3_ARM_v7a_ICache(Cache): hit_latency = 1 response_latency = 1 mshrs = 2 @@ -153,7 +153,7 @@ class O3_ARM_v7a_ICache(BaseCache): is_read_only = True # Data Cache -class O3_ARM_v7a_DCache(BaseCache): +class O3_ARM_v7a_DCache(Cache): hit_latency = 2 response_latency = 2 mshrs = 6 @@ -164,7 +164,7 @@ class O3_ARM_v7a_DCache(BaseCache): # TLB Cache # Use a cache as a L2 TLB -class O3_ARM_v7aWalkCache(BaseCache): +class O3_ARM_v7aWalkCache(Cache): hit_latency = 4 response_latency = 4 mshrs = 6 @@ -176,7 +176,7 @@ class O3_ARM_v7aWalkCache(BaseCache): is_read_only = True # L2 Cache -class O3_ARM_v7aL2(BaseCache): +class O3_ARM_v7aL2(Cache): hit_latency = 12 response_latency = 12 mshrs = 16 |