diff options
Diffstat (limited to 'configs/common/O3_ARM_v7a.py')
| -rw-r--r-- | configs/common/O3_ARM_v7a.py | 21 |
1 files changed, 9 insertions, 12 deletions
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index 20ef10ebc..c971df7fb 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -145,10 +145,9 @@ class O3_ARM_v7a_3(DerivO3CPU): defer_registration= False # Instruction Cache -# All latencys assume a 1GHz clock rate, with a faster clock they would be faster class O3_ARM_v7a_ICache(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 1 + response_latency = 1 block_size = 64 mshrs = 2 tgts_per_mshr = 8 @@ -157,10 +156,9 @@ class O3_ARM_v7a_ICache(BaseCache): is_top_level = 'true' # Data Cache -# All latencys assume a 1GHz clock rate, with a faster clock they would be faster class O3_ARM_v7a_DCache(BaseCache): - hit_latency = '2ns' - response_latency = '2ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 6 tgts_per_mshr = 8 @@ -172,8 +170,8 @@ class O3_ARM_v7a_DCache(BaseCache): # TLB Cache # Use a cache as a L2 TLB class O3_ARM_v7aWalkCache(BaseCache): - hit_latency = '4ns' - response_latency = '4ns' + hit_latency = 4 + response_latency = 4 block_size = 64 mshrs = 6 tgts_per_mshr = 8 @@ -184,10 +182,9 @@ class O3_ARM_v7aWalkCache(BaseCache): # L2 Cache -# All latencys assume a 1GHz clock rate, with a faster clock they would be faster class O3_ARM_v7aL2(BaseCache): - hit_latency = '12ns' - response_latency = '12ns' + hit_latency = 12 + response_latency = 12 block_size = 64 mshrs = 16 tgts_per_mshr = 8 @@ -196,5 +193,5 @@ class O3_ARM_v7aL2(BaseCache): write_buffers = 8 prefetch_on_access = 'true' # Simple stride prefetcher - prefetcher = StridePrefetcher(degree=8, latency='1.0ns') + prefetcher = StridePrefetcher(degree=8, latency = 1) |