diff options
Diffstat (limited to 'configs/common')
| -rw-r--r-- | configs/common/CacheConfig.py | 7 | ||||
| -rw-r--r-- | configs/common/Simulation.py | 10 |
2 files changed, 9 insertions, 8 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 288a633ce..4b4ce7553 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012 ARM Limited +# Copyright (c) 2012-2013 ARM Limited # All rights reserved # # The license below extends only to copyright in the software and shall @@ -64,12 +64,13 @@ def config_cache(options, system): # are not connected using addTwoLevelCacheHierarchy. Use the # same clock as the CPUs, and set the L1-to-L2 bus width to 32 # bytes (256 bits). - system.l2 = l2_cache_class(clock=options.cpu_clock, + system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain, size=options.l2_size, assoc=options.l2_assoc, block_size=options.cacheline_size) - system.tol2bus = CoherentBus(clock = options.cpu_clock, width = 32) + system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain, + width = 32) system.l2.cpu_side = system.tol2bus.master system.l2.mem_side = system.membus.slave diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 27b1a510a..deccdad5c 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012 ARM Limited +# Copyright (c) 2012-2013 ARM Limited # All rights reserved # # The license below extends only to copyright in the software and shall @@ -308,7 +308,7 @@ def run(options, root, testsys, cpu_class): testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) switch_cpus[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload - switch_cpus[i].clock = testsys.cpu[i].clock + switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain # simulation period if options.maxinsts: switch_cpus[i].max_insts_any_thread = options.maxinsts @@ -335,7 +335,7 @@ def run(options, root, testsys, cpu_class): for i in xrange(np): repeat_switch_cpus[i].system = testsys repeat_switch_cpus[i].workload = testsys.cpu[i].workload - repeat_switch_cpus[i].clock = testsys.cpu[i].clock + repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain if options.maxinsts: repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts @@ -363,8 +363,8 @@ def run(options, root, testsys, cpu_class): switch_cpus_1[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus_1[i].workload = testsys.cpu[i].workload - switch_cpus[i].clock = testsys.cpu[i].clock - switch_cpus_1[i].clock = testsys.cpu[i].clock + switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain + switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain # if restoring, make atomic cpu simulate only a few instructions if options.checkpoint_restore != None: |