diff options
Diffstat (limited to 'configs/common')
-rw-r--r-- | configs/common/CacheConfig.py | 4 | ||||
-rw-r--r-- | configs/common/Options.py | 3 |
2 files changed, 5 insertions, 2 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 5dd564f0c..288a633ce 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -64,12 +64,12 @@ def config_cache(options, system): # are not connected using addTwoLevelCacheHierarchy. Use the # same clock as the CPUs, and set the L1-to-L2 bus width to 32 # bytes (256 bits). - system.l2 = l2_cache_class(clock=options.clock, + system.l2 = l2_cache_class(clock=options.cpu_clock, size=options.l2_size, assoc=options.l2_assoc, block_size=options.cacheline_size) - system.tol2bus = CoherentBus(clock = options.clock, width = 32) + system.tol2bus = CoherentBus(clock = options.cpu_clock, width = 32) system.l2.cpu_side = system.tol2bus.master system.l2.mem_side = system.membus.slave diff --git a/configs/common/Options.py b/configs/common/Options.py index f2bcbef0c..08881cf11 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -78,6 +78,9 @@ def addCommonOptions(parser): parser.add_option("--simpoint-interval", type="int", default=10000000, help="SimPoint interval in num of instructions") parser.add_option("--clock", action="store", type="string", default='2GHz') + parser.add_option("--cpu-clock", action="store", type="string", + default='2GHz', + help="Clock for blocks running at CPU speed") parser.add_option("--num-dirs", type="int", default=1) parser.add_option("--num-l2caches", type="int", default=1) parser.add_option("--num-l3caches", type="int", default=1) |