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-rw-r--r--configs/common/Caches.py7
-rw-r--r--configs/common/FSConfig.py4
-rw-r--r--configs/common/Options.py1
3 files changed, 10 insertions, 2 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 43a1c6378..f1ea957b5 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -43,3 +43,10 @@ class L2Cache(BaseCache):
mshrs = 20
tgts_per_mshr = 12
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = '10ns'
+ mshrs = 20
+ size = '1kB'
+ tgts_per_mshr = 12
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6bcdafb14..e2d6b710b 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -53,7 +53,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
self.membus = Bus(bus_id=1)
- self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns')
+ self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
self.bridge.side_a = self.iobus.port
self.bridge.side_b = self.membus.port
@@ -93,7 +93,7 @@ def makeSparcSystem(mem_mode, mdesc = None):
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
self.membus = Bus(bus_id=1)
- self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns')
+ self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 4f2b317c0..225916840 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -32,6 +32,7 @@ parser.add_option("-t", "--timing", action="store_true")
parser.add_option("-n", "--num_cpus", type="int", default=1)
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")
+parser.add_option("--fastmem", action="store_true")
# Run duration options
parser.add_option("-m", "--maxtick", type="int")