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-rw-r--r--configs/common/CacheConfig.py29
-rw-r--r--configs/common/FSConfig.py103
-rw-r--r--configs/common/O3_ARM_v7a.py199
-rw-r--r--configs/common/Options.py3
-rw-r--r--configs/common/Simulation.py10
5 files changed, 321 insertions, 23 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 00517dfc4..364b20f28 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -32,11 +32,17 @@
import m5
from m5.objects import *
from Caches import *
+from O3_ARM_v7a import *
def config_cache(options, system):
if options.l2cache:
- system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
- block_size=options.cacheline_size)
+ if options.cpu_type == "arm_detailed":
+ system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc,
+ block_size=options.cacheline_size)
+ else:
+ system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
+ block_size=options.cacheline_size)
+
system.tol2bus = Bus()
system.l2.cpu_side = system.tol2bus.port
system.l2.mem_side = system.membus.port
@@ -44,10 +50,21 @@ def config_cache(options, system):
for i in xrange(options.num_cpus):
if options.caches:
- icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc,
- block_size=options.cacheline_size)
- dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
- block_size=options.cacheline_size)
+ if options.cpu_type == "arm_detailed":
+ icache = O3_ARM_v7a_ICache(size = options.l1i_size,
+ assoc = options.l1i_assoc,
+ block_size=options.cacheline_size)
+ dcache = O3_ARM_v7a_DCache(size = options.l1d_size,
+ assoc = options.l1d_assoc,
+ block_size=options.cacheline_size)
+ else:
+ icache = L1Cache(size = options.l1i_size,
+ assoc = options.l1i_assoc,
+ block_size=options.cacheline_size)
+ dcache = L1Cache(size = options.l1d_size,
+ assoc = options.l1d_assoc,
+ block_size=options.cacheline_size)
+
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(),
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index f54d63852..6154f9877 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2010 ARM Limited
+# Copyright (c) 2010-2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -56,6 +56,7 @@ class MemBus(Bus):
def makeLinuxAlphaSystem(mem_mode, mdesc = None):
+ IO_address_space_base = 0x80000000000
class BaseTsunami(Tsunami):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
@@ -68,10 +69,13 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
self.membus = MemBus(bus_id=1)
- self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ # By default the bridge responds to all addresses above the I/O
+ # base address (including the PCI config space)
+ self.bridge = Bridge(delay='50ns', nack_delay='4ns',
+ ranges = [AddrRange(IO_address_space_base, Addr.max)])
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
- self.bridge.side_a = self.iobus.port
- self.bridge.side_b = self.membus.port
+ self.bridge.master = self.iobus.port
+ self.bridge.slave = self.membus.port
self.physmem.port = self.membus.port
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
@@ -80,7 +84,11 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self.tsunami = BaseTsunami()
self.tsunami.attachIO(self.iobus)
self.tsunami.ide.pio = self.iobus.port
+ self.tsunami.ide.config = self.iobus.port
+ self.tsunami.ide.dma = self.iobus.port
self.tsunami.ethernet.pio = self.iobus.port
+ self.tsunami.ethernet.config = self.iobus.port
+ self.tsunami.ethernet.dma = self.iobus.port
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
@@ -91,6 +99,8 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self.console = binary('console')
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+ self.system_port = self.membus.port
+
return self
def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
@@ -123,7 +133,11 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
self.tsunami = BaseTsunami()
self.tsunami.attachIO(self.piobus)
self.tsunami.ide.pio = self.piobus.port
+ self.tsunami.ide.config = self.piobus.port
+ self.tsunami.ide.dma = self.piobus.port
self.tsunami.ethernet.pio = self.piobus.port
+ self.tsunami.ethernet.config = self.piobus.port
+ self.tsunami.ethernet.dma = self.piobus.port
#
# Store the dma devices for later connection to dma ruby ports.
@@ -144,6 +158,10 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
return self
def makeSparcSystem(mem_mode, mdesc = None):
+ # Constants from iob.cc and uart8250.cc
+ iob_man_addr = 0x9800000000
+ uart_pio_size = 8
+
class CowMmDisk(MmDisk):
image = CowDiskImage(child=RawDiskImage(read_only=True),
read_only=False)
@@ -164,8 +182,8 @@ def makeSparcSystem(mem_mode, mdesc = None):
self.t1000.attachIO(self.iobus)
self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
- self.bridge.side_a = self.iobus.port
- self.bridge.side_b = self.membus.port
+ self.bridge.master = self.iobus.port
+ self.bridge.slave = self.membus.port
self.physmem.port = self.membus.port
self.physmem2.port = self.membus.port
self.rom.port = self.membus.port
@@ -176,6 +194,25 @@ def makeSparcSystem(mem_mode, mdesc = None):
self.disk0 = CowMmDisk()
self.disk0.childImage(disk('disk.s10hw2'))
self.disk0.pio = self.iobus.port
+
+ # The puart0 and hvuart are placed on the IO bus, so create ranges
+ # for them. The remaining IO range is rather fragmented, so poke
+ # holes for the iob and partition descriptors etc.
+ self.bridge.ranges = \
+ [
+ AddrRange(self.t1000.puart0.pio_addr,
+ self.t1000.puart0.pio_addr + uart_pio_size - 1),
+ AddrRange(self.disk0.pio_addr,
+ self.t1000.fake_jbi.pio_addr +
+ self.t1000.fake_jbi.pio_size - 1),
+ AddrRange(self.t1000.fake_clk.pio_addr,
+ iob_man_addr - 1),
+ AddrRange(self.t1000.fake_l2_1.pio_addr,
+ self.t1000.fake_ssi.pio_addr +
+ self.t1000.fake_ssi.pio_size - 1),
+ AddrRange(self.t1000.hvuart.pio_addr,
+ self.t1000.hvuart.pio_addr + uart_pio_size - 1)
+ ]
self.reset_bin = binary('reset_new.bin')
self.hypervisor_bin = binary('q_new.bin')
self.openboot_bin = binary('openboot_new.bin')
@@ -183,6 +220,8 @@ def makeSparcSystem(mem_mode, mdesc = None):
self.hypervisor_desc_bin = binary('1up-hv.bin')
self.partition_desc_bin = binary('1up-md.bin')
+ self.system_port = self.membus.port
+
return self
def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
@@ -202,8 +241,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
self.membus = MemBus(bus_id=1)
self.membus.badaddr_responder.warn_access = "warn"
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
- self.bridge.side_a = self.iobus.port
- self.bridge.side_b = self.membus.port
+ self.bridge.master = self.iobus.port
+ self.bridge.slave = self.membus.port
self.mem_mode = mem_mode
@@ -257,12 +296,14 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
self.boot_osflags = boot_flags
self.physmem.port = self.membus.port
- self.realview.attachOnChipIO(self.membus)
+ self.realview.attachOnChipIO(self.membus, self.bridge)
self.realview.attachIO(self.iobus)
self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()
+ self.system_port = self.membus.port
+
return self
@@ -281,8 +322,8 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
self.membus = MemBus(bus_id=1)
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.physmem = PhysicalMemory(range = AddrRange('1GB'))
- self.bridge.side_a = self.iobus.port
- self.bridge.side_b = self.membus.port
+ self.bridge.master = self.iobus.port
+ self.bridge.slave = self.membus.port
self.physmem.port = self.membus.port
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
@@ -291,7 +332,11 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
self.malta = BaseMalta()
self.malta.attachIO(self.iobus)
self.malta.ide.pio = self.iobus.port
+ self.malta.ide.config = self.iobus.port
+ self.malta.ide.dma = self.iobus.port
self.malta.ethernet.pio = self.iobus.port
+ self.malta.ethernet.config = self.iobus.port
+ self.malta.ethernet.dma = self.iobus.port
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
@@ -301,6 +346,8 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
self.console = binary('mips/console')
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+ self.system_port = self.membus.port
+
return self
def x86IOAddress(port):
@@ -308,18 +355,48 @@ def x86IOAddress(port):
return IO_address_space_base + port
def connectX86ClassicSystem(x86_sys):
+ # Constants similar to x86_traits.hh
+ IO_address_space_base = 0x8000000000000000
+ pci_config_address_space_base = 0xc000000000000000
+ interrupts_address_space_base = 0xa000000000000000
+ APIC_range_size = 1 << 12;
+
x86_sys.membus = MemBus(bus_id=1)
x86_sys.physmem.port = x86_sys.membus.port
# North Bridge
x86_sys.iobus = Bus(bus_id=0)
x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
- x86_sys.bridge.side_a = x86_sys.iobus.port
- x86_sys.bridge.side_b = x86_sys.membus.port
+ x86_sys.bridge.master = x86_sys.iobus.port
+ x86_sys.bridge.slave = x86_sys.membus.port
+ # Allow the bridge to pass through the IO APIC (two pages),
+ # everything in the IO address range up to the local APIC, and
+ # then the entire PCI address space and beyond
+ x86_sys.bridge.ranges = \
+ [
+ AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
+ x86_sys.pc.south_bridge.io_apic.pio_addr +
+ APIC_range_size - 1),
+ AddrRange(IO_address_space_base,
+ interrupts_address_space_base - 1),
+ AddrRange(pci_config_address_space_base,
+ Addr.max)
+ ]
+
+ # Create a bridge from the IO bus to the memory bus to allow access to
+ # the local APIC (two pages)
+ x86_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns')
+ x86_sys.iobridge.slave = x86_sys.iobus.port
+ x86_sys.iobridge.master = x86_sys.membus.port
+ x86_sys.iobridge.ranges = [AddrRange(interrupts_address_space_base,
+ interrupts_address_space_base +
+ APIC_range_size - 1)]
# connect the io bus
x86_sys.pc.attachIO(x86_sys.iobus)
+ x86_sys.system_port = x86_sys.membus.port
+
def connectX86RubySystem(x86_sys):
# North Bridge
x86_sys.piobus = Bus(bus_id=0)
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py
new file mode 100644
index 000000000..a2b769f27
--- /dev/null
+++ b/configs/common/O3_ARM_v7a.py
@@ -0,0 +1,199 @@
+# Copyright (c) 2012 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+
+from m5.objects import *
+
+# Simple ALU Instructions have a latency of 1
+class O3_ARM_v7a_Simple_Int(FUDesc):
+ opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
+ count = 2
+
+# Complex ALU instructions have a variable latencies
+class O3_ARM_v7a_Complex_Int(FUDesc):
+ opList = [ OpDesc(opClass='IntMult', opLat=3, issueLat=1),
+ OpDesc(opClass='IntDiv', opLat=12, issueLat=12),
+ OpDesc(opClass='IprAccess', opLat=3, issueLat=1) ]
+ count = 1
+
+
+# Floating point and SIMD instructions
+class O3_ARM_v7a_FP(FUDesc):
+ opList = [ OpDesc(opClass='SimdAdd', opLat=4),
+ OpDesc(opClass='SimdAddAcc', opLat=4),
+ OpDesc(opClass='SimdAlu', opLat=4),
+ OpDesc(opClass='SimdCmp', opLat=4),
+ OpDesc(opClass='SimdCvt', opLat=3),
+ OpDesc(opClass='SimdMisc', opLat=3),
+ OpDesc(opClass='SimdMult',opLat=5),
+ OpDesc(opClass='SimdMultAcc',opLat=5),
+ OpDesc(opClass='SimdShift',opLat=3),
+ OpDesc(opClass='SimdShiftAcc', opLat=3),
+ OpDesc(opClass='SimdSqrt', opLat=9),
+ OpDesc(opClass='SimdFloatAdd',opLat=5),
+ OpDesc(opClass='SimdFloatAlu',opLat=5),
+ OpDesc(opClass='SimdFloatCmp', opLat=3),
+ OpDesc(opClass='SimdFloatCvt', opLat=3),
+ OpDesc(opClass='SimdFloatDiv', opLat=3),
+ OpDesc(opClass='SimdFloatMisc', opLat=3),
+ OpDesc(opClass='SimdFloatMult', opLat=3),
+ OpDesc(opClass='SimdFloatMultAcc',opLat=1),
+ OpDesc(opClass='SimdFloatSqrt', opLat=9),
+ OpDesc(opClass='FloatAdd', opLat=5),
+ OpDesc(opClass='FloatCmp', opLat=5),
+ OpDesc(opClass='FloatCvt', opLat=5),
+ OpDesc(opClass='FloatDiv', opLat=9, issueLat=9),
+ OpDesc(opClass='FloatSqrt', opLat=33, issueLat=33),
+ OpDesc(opClass='FloatMult', opLat=4) ]
+ count = 2
+
+
+# Load/Store Units
+class O3_ARM_v7a_Load(FUDesc):
+ opList = [ OpDesc(opClass='MemRead',opLat=2) ]
+ count = 1
+
+class O3_ARM_v7a_Store(FUDesc):
+ opList = [OpDesc(opClass='MemWrite',opLat=2) ]
+ count = 1
+
+# Functional Units for this CPU
+class O3_ARM_v7a_FUP(FUPool):
+ FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(),
+ O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()]
+
+
+class O3_ARM_v7a_3(DerivO3CPU):
+ predType = "tournament"
+ localPredictorSize = 64
+ localCtrBits = 2
+ localHistoryTableSize = 64
+ localHistoryBits = 6
+ globalPredictorSize = 8192
+ globalCtrBits = 2
+ globalHistoryBits = 13
+ choicePredictorSize = 8192
+ choiceCtrBits = 2
+ BTBEntries = 2048
+ BTBTagSize = 18
+ RASSize = 16
+ instShiftAmt = 2
+ LQEntries = 16
+ SQEntries = 16
+ LSQDepCheckShift = 0
+ LFSTSize = 1024
+ SSITSize = 1024
+ decodeToFetchDelay = 1
+ renameToFetchDelay = 1
+ iewToFetchDelay = 1
+ commitToFetchDelay = 1
+ renameToDecodeDelay = 1
+ iewToDecodeDelay = 1
+ commitToDecodeDelay = 1
+ iewToRenameDelay = 1
+ commitToRenameDelay = 1
+ commitToIEWDelay = 1
+ fetchWidth = 3
+ fetchToDecodeDelay = 3
+ decodeWidth = 3
+ decodeToRenameDelay = 2
+ renameWidth = 3
+ renameToIEWDelay = 1
+ issueToExecuteDelay = 1
+ dispatchWidth = 6
+ issueWidth = 8
+ wbWidth = 8
+ wbDepth = 1
+ fuPool = O3_ARM_v7a_FUP()
+ iewToCommitDelay = 1
+ renameToROBDelay = 1
+ commitWidth = 8
+ squashWidth = 8
+ trapLatency = 13
+ backComSize = 5
+ forwardComSize = 5
+ numPhysIntRegs = 128
+ numPhysFloatRegs = 128
+ numIQEntries = 32
+ numROBEntries = 40
+
+ defer_registration= False
+
+# Instruction Cache
+# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
+class O3_ARM_v7a_ICache(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 2
+ tgts_per_mshr = 8
+ size = '32kB'
+ assoc = 2
+ is_top_level = 'true'
+
+# Data Cache
+# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
+class O3_ARM_v7a_DCache(BaseCache):
+ latency = '2ns'
+ block_size = 64
+ mshrs = 6
+ tgts_per_mshr = 8
+ size = '32kB'
+ assoc = 2
+ write_buffers = 16
+ is_top_level = 'true'
+
+# TLB Cache
+# Use a cache as a L2 TLB
+class O3_ARM_v7aWalkCache(BaseCache):
+ latency = '4ns'
+ block_size = 64
+ mshrs = 6
+ tgts_per_mshr = 8
+ size = '1kB'
+ assoc = 8
+ write_buffers = 16
+ is_top_level = 'true'
+
+
+# L2 Cache
+# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
+class O3_ARM_v7aL2(BaseCache):
+ latency = '12ns'
+ block_size = 64
+ mshrs = 16
+ tgts_per_mshr = 8
+ size = '1MB'
+ assoc = 16
+ write_buffers = 8
+ # Simple stride prefetcher
+ prefetch_policy = 'stride'
+ prefetch_on_access = 'true'
+ prefetch_latency = '1.0ns'
+ prefetch_degree = 8
+
+
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 1941875bc..0932f2629 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -28,7 +28,8 @@
# system options
parser.add_option("--cpu-type", type="choice", default="atomic",
- choices = ["atomic", "timing", "detailed", "inorder"],
+ choices = ["atomic", "timing", "detailed", "inorder",
+ "arm_detailed"],
help = "type of cpu to run with")
parser.add_option("-n", "--num-cpus", type="int", default=1)
parser.add_option("--caches", action="store_true")
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 434fe8369..193f8d487 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -34,6 +34,7 @@ import m5
from m5.defines import buildEnv
from m5.objects import *
from m5.util import *
+from O3_ARM_v7a import *
addToPath('../common')
@@ -42,11 +43,14 @@ def setCPUClass(options):
atomic = False
if options.cpu_type == "timing":
class TmpClass(TimingSimpleCPU): pass
- elif options.cpu_type == "detailed":
- if not options.caches:
+ elif options.cpu_type == "detailed" or options.cpu_type == "arm_detailed":
+ if not options.caches and not options.ruby:
print "O3 CPU must be used with caches"
sys.exit(1)
- class TmpClass(DerivO3CPU): pass
+ if options.cpu_type == "arm_detailed":
+ class TmpClass(O3_ARM_v7a_3): pass
+ else:
+ class TmpClass(DerivO3CPU): pass
elif options.cpu_type == "inorder":
if not options.caches:
print "InOrder CPU must be used with caches"
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-13 22:53:10 +0000