diff options
Diffstat (limited to 'configs/common')
| -rw-r--r-- | configs/common/CacheConfig.py | 4 | ||||
| -rw-r--r-- | configs/common/FSConfig.py | 14 |
2 files changed, 9 insertions, 9 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index b467b1656..c7a724b34 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -71,8 +71,8 @@ def config_cache(options, system): size=options.l2_size, assoc=options.l2_assoc) - system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain, - width = 32) + system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain, + width = 32) system.l2.cpu_side = system.tol2bus.master system.l2.mem_side = system.membus.slave diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index cc921229e..e93bd68f2 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -50,7 +50,7 @@ class CowIdeDisk(IdeDisk): def childImage(self, ci): self.image.child.image_file = ci -class MemBus(CoherentBus): +class MemBus(CoherentXBar): badaddr_responder = BadAddr() default = Self.badaddr_responder.pio @@ -71,7 +71,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False): self.tsunami = BaseTsunami() # Create the io bus to connect all device ports - self.iobus = NoncoherentBus() + self.iobus = NoncoherentXBar() self.tsunami.attachIO(self.iobus) self.tsunami.ide.pio = self.iobus.master @@ -134,7 +134,7 @@ def makeSparcSystem(mem_mode, mdesc = None): # generic system mdesc = SysConfig() self.readfile = mdesc.script() - self.iobus = NoncoherentBus() + self.iobus = NoncoherentXBar() self.membus = MemBus() self.bridge = Bridge(delay='50ns') self.t1000 = T1000() @@ -196,7 +196,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, mdesc = SysConfig() self.readfile = mdesc.script() - self.iobus = NoncoherentBus() + self.iobus = NoncoherentXBar() self.membus = MemBus() self.membus.badaddr_responder.warn_access = "warn" self.bridge = Bridge(delay='50ns') @@ -299,7 +299,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None): # generic system mdesc = SysConfig() self.readfile = mdesc.script() - self.iobus = NoncoherentBus() + self.iobus = NoncoherentXBar() self.membus = MemBus() self.bridge = Bridge(delay='50ns') self.mem_ranges = [AddrRange('1GB')] @@ -344,7 +344,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs): x86_sys.membus = MemBus() # North Bridge - x86_sys.iobus = NoncoherentBus() + x86_sys.iobus = NoncoherentXBar() x86_sys.bridge = Bridge(delay='50ns') x86_sys.bridge.master = x86_sys.iobus.slave x86_sys.bridge.slave = x86_sys.membus.master @@ -379,7 +379,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs): def connectX86RubySystem(x86_sys): # North Bridge - x86_sys.iobus = NoncoherentBus() + x86_sys.iobus = NoncoherentXBar() # add the ide to the list of dma devices that later need to attach to # dma controllers |