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-rw-r--r--configs/common/CacheConfig.py7
-rw-r--r--configs/common/CpuConfig.py25
-rw-r--r--configs/common/MemConfig.py10
-rw-r--r--configs/common/Options.py13
-rw-r--r--configs/common/Simulation.py10
5 files changed, 63 insertions, 2 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index d54df7490..b96a7011c 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -69,6 +69,13 @@ def config_cache(options, system):
# Set the cache line size of the system
system.cache_line_size = options.cacheline_size
+ # If elastic trace generation is enabled, make sure the memory system is
+ # minimal so that compute delays do not include memory access latencies.
+ # Configure the compulsory L1 caches for the O3CPU, do not configure
+ # any more caches.
+ if options.l2cache and options.elastic_trace_en:
+ fatal("When elastic trace is enabled, do not configure L2 caches.")
+
if options.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
# are not connected using addTwoLevelCacheHierarchy. Use the
diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index 6b530623d..3220acecd 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -53,6 +53,7 @@ _cpu_aliases_all = [
("minor", "MinorCPU"),
("detailed", "DerivO3CPU"),
("kvm", ("ArmKvmCPU", "ArmV8KvmCPU", "X86KvmCPU")),
+ ("trace", "TraceCPU"),
]
# Filtered list of aliases. Only aliases for existing CPUs exist in
@@ -108,6 +109,30 @@ def cpu_names():
"""Return a list of valid CPU names."""
return _cpu_classes.keys() + _cpu_aliases.keys()
+def config_etrace(cpu_cls, cpu_list, options):
+ if issubclass(cpu_cls, m5.objects.DerivO3CPU):
+ # Assign the same file name to all cpus for now. This must be
+ # revisited when creating elastic traces for multi processor systems.
+ for cpu in cpu_list:
+ # Attach the elastic trace probe listener. Set the protobuf trace
+ # file names. Set the dependency window size equal to the cpu it
+ # is attached to.
+ cpu.traceListener = m5.objects.ElasticTrace(
+ instFetchTraceFile = options.inst_trace_file,
+ dataDepTraceFile = options.data_trace_file,
+ depWindowSize = 3 * cpu.numROBEntries)
+ # Make the number of entries in the ROB, LQ and SQ very
+ # large so that there are no stalls due to resource
+ # limitation as such stalls will get captured in the trace
+ # as compute delay. For replay, ROB, LQ and SQ sizes are
+ # modelled in the Trace CPU.
+ cpu.numROBEntries = 512;
+ cpu.LQEntries = 128;
+ cpu.SQEntries = 128;
+ else:
+ fatal("%s does not support data dependency tracing. Use a CPU model of"
+ " type or inherited from DerivO3CPU.", cpu_cls)
+
# The ARM detailed CPU is special in the sense that it doesn't exist
# in the normal object hierarchy, so we have to add it manually.
try:
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 286898798..4685cd5d1 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -187,6 +187,11 @@ def config_mem(options, system):
cls = get(options.mem_type)
mem_ctrls = []
+ if options.elastic_trace_en and not issubclass(cls, \
+ m5.objects.SimpleMemory):
+ fatal("When elastic trace is enabled, configure mem-type as "
+ "simple-mem.")
+
# The default behaviour is to interleave memory channels on 128
# byte granularity, or cache line granularity if larger than 128
# byte. This value is based on the locality seen across a large
@@ -206,6 +211,11 @@ def config_mem(options, system):
options.mem_ranks:
mem_ctrl.ranks_per_channel = options.mem_ranks
+ if options.elastic_trace_en:
+ mem_ctrl.latency = '1ns'
+ print "For elastic trace, over-riding Simple Memory " \
+ "latency to 1ns."
+
mem_ctrls.append(mem_ctrl)
subsystem.mem_ctrls = mem_ctrls
diff --git a/configs/common/Options.py b/configs/common/Options.py
index f4cf9fbd6..45be8e2f8 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -87,6 +87,19 @@ def addCommonOptions(parser):
Only used if multiple programs are specified. If true,
then the number of threads per cpu is same as the
number of programs.""")
+ parser.add_option("--elastic-trace-en", action="store_true",
+ help="""Enable capture of data dependency and instruction
+ fetch traces using elastic trace probe.""")
+ # Trace file paths input to trace probe in a capture simulation and input
+ # to Trace CPU in a replay simulation
+ parser.add_option("--inst-trace-file", action="store", type="string",
+ help="""Instruction fetch trace file input to
+ Elastic Trace probe in a capture simulation and
+ Trace CPU in a replay simulation""", default="")
+ parser.add_option("--data-trace-file", action="store", type="string",
+ help="""Data dependency trace file input to
+ Elastic Trace probe in a capture simulation and
+ Trace CPU in a replay simulation""", default="")
# Memory Options
parser.add_option("--list-mem-types",
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 73874674c..13edf601b 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -459,10 +459,11 @@ def run(options, root, testsys, cpu_class):
for i in xrange(np):
if options.fast_forward:
testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
- switch_cpus[i].system = testsys
+ switch_cpus[i].system = testsys
switch_cpus[i].workload = testsys.cpu[i].workload
switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
- switch_cpus[i].progress_interval = testsys.cpu[i].progress_interval
+ switch_cpus[i].progress_interval = \
+ testsys.cpu[i].progress_interval
# simulation period
if options.maxinsts:
switch_cpus[i].max_insts_any_thread = options.maxinsts
@@ -470,6 +471,11 @@ def run(options, root, testsys, cpu_class):
if options.checker:
switch_cpus[i].addCheckerCpu()
+ # If elastic tracing is enabled attach the elastic trace probe
+ # to the switch CPUs
+ if options.elastic_trace_en:
+ CpuConfig.config_etrace(cpu_class, switch_cpus, options)
+
testsys.switch_cpus = switch_cpus
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]