summaryrefslogtreecommitdiff
path: root/configs/dram/lat_mem_rd.py
diff options
context:
space:
mode:
Diffstat (limited to 'configs/dram/lat_mem_rd.py')
-rw-r--r--configs/dram/lat_mem_rd.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/dram/lat_mem_rd.py b/configs/dram/lat_mem_rd.py
index 374f1d4be..d4015a522 100644
--- a/configs/dram/lat_mem_rd.py
+++ b/configs/dram/lat_mem_rd.py
@@ -44,8 +44,8 @@ from m5.objects import *
from m5.util import addToPath
from m5.internal.stats import periodicStatDump
-addToPath('../common')
-import MemConfig
+addToPath('../')
+from common import MemConfig
addToPath('../../util')
import protolib
@@ -258,7 +258,7 @@ system.tgen.port = system.monitor.slave
# create the actual cache hierarchy, for now just go with something
# basic to explore some of the options
-from Caches import *
+from common.Caches import *
# a starting point for an L3 cache
class L3Cache(Cache):